| if_bgereg.h (214251) | if_bgereg.h (214428) |
|---|---|
| 1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 16 unchanged lines hidden (view full) --- 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * | 1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 16 unchanged lines hidden (view full) --- 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * |
| 33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 214251 2010-10-23 21:25:50Z yongari $ | 33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 214428 2010-10-27 17:20:19Z yongari $ |
| 34 */ 35 36/* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and --- 35 unchanged lines hidden (view full) --- 77#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81#define BGE_UNMAPPED 0x00001000 82#define BGE_UNMAPPED_END 0x00001FFF 83#define BGE_DMA_DESCRIPTORS 0x00002000 84#define BGE_DMA_DESCRIPTORS_END 0x00003FFF | 34 */ 35 36/* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and --- 35 unchanged lines hidden (view full) --- 77#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81#define BGE_UNMAPPED 0x00001000 82#define BGE_UNMAPPED_END 0x00001FFF 83#define BGE_DMA_DESCRIPTORS 0x00002000 84#define BGE_DMA_DESCRIPTORS_END 0x00003FFF |
| 85#define BGE_SEND_RING_5717 0x00004000 |
|
| 85#define BGE_SEND_RING_1_TO_4 0x00004000 86#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 87 88/* Firmware interface */ 89#define BGE_FW_DRV_ALIVE 0x00000001 90#define BGE_FW_PAUSE 0x00000002 91 92/* Mappings for internal memory configuration */ 93#define BGE_STD_RX_RINGS 0x00006000 94#define BGE_STD_RX_RINGS_END 0x00006FFF 95#define BGE_JUMBO_RX_RINGS 0x00007000 96#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 97#define BGE_BUFFPOOL_1 0x00008000 98#define BGE_BUFFPOOL_1_END 0x0000FFFF 99#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 100#define BGE_BUFFPOOL_2_END 0x00017FFF 101#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 102#define BGE_BUFFPOOL_3_END 0x0001FFFF | 86#define BGE_SEND_RING_1_TO_4 0x00004000 87#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 88 89/* Firmware interface */ 90#define BGE_FW_DRV_ALIVE 0x00000001 91#define BGE_FW_PAUSE 0x00000002 92 93/* Mappings for internal memory configuration */ 94#define BGE_STD_RX_RINGS 0x00006000 95#define BGE_STD_RX_RINGS_END 0x00006FFF 96#define BGE_JUMBO_RX_RINGS 0x00007000 97#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 98#define BGE_BUFFPOOL_1 0x00008000 99#define BGE_BUFFPOOL_1_END 0x0000FFFF 100#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 101#define BGE_BUFFPOOL_2_END 0x00017FFF 102#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 103#define BGE_BUFFPOOL_3_END 0x0001FFFF |
| 104#define BGE_STD_RX_RINGS_5717 0x00040000 105#define BGE_JUMBO_RX_RINGS_5717 0x00044400 |
|
| 103 104/* Mappings for external SSRAM configurations */ 105#define BGE_SEND_RING_5_TO_6 0x00006000 106#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 107#define BGE_SEND_RING_7_TO_8 0x00007000 108#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 109#define BGE_SEND_RING_9_TO_16 0x00008000 110#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF --- 103 unchanged lines hidden (view full) --- 214#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 215#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 216#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 217#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 218#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 219#define BGE_PCI_ISR_MBX_HI 0xB0 220#define BGE_PCI_ISR_MBX_LO 0xB4 221#define BGE_PCI_PRODID_ASICREV 0xBC | 106 107/* Mappings for external SSRAM configurations */ 108#define BGE_SEND_RING_5_TO_6 0x00006000 109#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 110#define BGE_SEND_RING_7_TO_8 0x00007000 111#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 112#define BGE_SEND_RING_9_TO_16 0x00008000 113#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF --- 103 unchanged lines hidden (view full) --- 217#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 218#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 219#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 220#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 221#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 222#define BGE_PCI_ISR_MBX_HI 0xB0 223#define BGE_PCI_ISR_MBX_LO 0xB4 224#define BGE_PCI_PRODID_ASICREV 0xBC |
| 225#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 |
|
| 222 223/* PCI Misc. Host control register */ 224#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 225#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 226#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 227#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 228#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 229#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 230#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 231#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 | 226 227/* PCI Misc. Host control register */ 228#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 229#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 230#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 231#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 232#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 233#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 234#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 235#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 |
| 236#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 |
|
| 232#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 233#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 234 235#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 236#if BYTE_ORDER == LITTLE_ENDIAN 237#define BGE_DMA_SWAP_OPTIONS \ 238 BGE_MODECTL_WORDSWAP_NONFRAME| \ 239 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA --- 66 unchanged lines hidden (view full) --- 306#define BGE_CHIPID_BCM5787_A0 0xb000 307#define BGE_CHIPID_BCM5787_A1 0xb001 308#define BGE_CHIPID_BCM5787_A2 0xb002 309#define BGE_CHIPID_BCM5906_A0 0xc000 310#define BGE_CHIPID_BCM5906_A1 0xc001 311#define BGE_CHIPID_BCM5906_A2 0xc002 312#define BGE_CHIPID_BCM57780_A0 0x57780000 313#define BGE_CHIPID_BCM57780_A1 0x57780001 | 237#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 238#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 239 240#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 241#if BYTE_ORDER == LITTLE_ENDIAN 242#define BGE_DMA_SWAP_OPTIONS \ 243 BGE_MODECTL_WORDSWAP_NONFRAME| \ 244 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA --- 66 unchanged lines hidden (view full) --- 311#define BGE_CHIPID_BCM5787_A0 0xb000 312#define BGE_CHIPID_BCM5787_A1 0xb001 313#define BGE_CHIPID_BCM5787_A2 0xb002 314#define BGE_CHIPID_BCM5906_A0 0xc000 315#define BGE_CHIPID_BCM5906_A1 0xc001 316#define BGE_CHIPID_BCM5906_A2 0xc002 317#define BGE_CHIPID_BCM57780_A0 0x57780000 318#define BGE_CHIPID_BCM57780_A1 0x57780001 |
| 319#define BGE_CHIPID_BCM5717_A0 0x05717000 320#define BGE_CHIPID_BCM5717_B0 0x05717100 |
|
| 314 315/* shorthand one */ 316#define BGE_ASICREV(x) ((x) >> 12) 317#define BGE_ASICREV_BCM5701 0x00 318#define BGE_ASICREV_BCM5703 0x01 319#define BGE_ASICREV_BCM5704 0x02 320#define BGE_ASICREV_BCM5705 0x03 321#define BGE_ASICREV_BCM5750 0x04 --- 4 unchanged lines hidden (view full) --- 326#define BGE_ASICREV_BCM5714 0x09 327#define BGE_ASICREV_BCM5755 0x0a 328#define BGE_ASICREV_BCM5754 0x0b 329#define BGE_ASICREV_BCM5787 0x0b 330#define BGE_ASICREV_BCM5906 0x0c 331/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 332#define BGE_ASICREV_USE_PRODID_REG 0x0f 333/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ | 321 322/* shorthand one */ 323#define BGE_ASICREV(x) ((x) >> 12) 324#define BGE_ASICREV_BCM5701 0x00 325#define BGE_ASICREV_BCM5703 0x01 326#define BGE_ASICREV_BCM5704 0x02 327#define BGE_ASICREV_BCM5705 0x03 328#define BGE_ASICREV_BCM5750 0x04 --- 4 unchanged lines hidden (view full) --- 333#define BGE_ASICREV_BCM5714 0x09 334#define BGE_ASICREV_BCM5755 0x0a 335#define BGE_ASICREV_BCM5754 0x0b 336#define BGE_ASICREV_BCM5787 0x0b 337#define BGE_ASICREV_BCM5906 0x0c 338/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 339#define BGE_ASICREV_USE_PRODID_REG 0x0f 340/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ |
| 341#define BGE_ASICREV_BCM5717 0x5717 |
|
| 334#define BGE_ASICREV_BCM5761 0x5761 335#define BGE_ASICREV_BCM5784 0x5784 336#define BGE_ASICREV_BCM5785 0x5785 337#define BGE_ASICREV_BCM57780 0x57780 338 339/* chip revisions */ 340#define BGE_CHIPREV(x) ((x) >> 8) 341#define BGE_CHIPREV_5700_AX 0x70 342#define BGE_CHIPREV_5700_BX 0x71 343#define BGE_CHIPREV_5700_CX 0x72 344#define BGE_CHIPREV_5701_AX 0x00 345#define BGE_CHIPREV_5703_AX 0x10 346#define BGE_CHIPREV_5704_AX 0x20 347#define BGE_CHIPREV_5704_BX 0x21 348#define BGE_CHIPREV_5750_AX 0x40 349#define BGE_CHIPREV_5750_BX 0x41 350/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ | 342#define BGE_ASICREV_BCM5761 0x5761 343#define BGE_ASICREV_BCM5784 0x5784 344#define BGE_ASICREV_BCM5785 0x5785 345#define BGE_ASICREV_BCM57780 0x57780 346 347/* chip revisions */ 348#define BGE_CHIPREV(x) ((x) >> 8) 349#define BGE_CHIPREV_5700_AX 0x70 350#define BGE_CHIPREV_5700_BX 0x71 351#define BGE_CHIPREV_5700_CX 0x72 352#define BGE_CHIPREV_5701_AX 0x00 353#define BGE_CHIPREV_5703_AX 0x10 354#define BGE_CHIPREV_5704_AX 0x20 355#define BGE_CHIPREV_5704_BX 0x21 356#define BGE_CHIPREV_5750_AX 0x40 357#define BGE_CHIPREV_5750_BX 0x41 358/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ |
| 359#define BGE_CHIPREV_5717_AX 0x57170 360#define BGE_CHIPREV_5717_BX 0x57171 |
|
| 351#define BGE_CHIPREV_5761_AX 0x57611 352#define BGE_CHIPREV_5784_AX 0x57841 353 354/* PCI DMA Read/Write Control register */ 355#define BGE_PCIDMARWCTL_MINDMA 0x000000FF | 361#define BGE_CHIPREV_5761_AX 0x57611 362#define BGE_CHIPREV_5784_AX 0x57841 363 364/* PCI DMA Read/Write Control register */ 365#define BGE_PCIDMARWCTL_MINDMA 0x000000FF |
| 366#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 |
|
| 356#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 357#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 358#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 359#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 360#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 361#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 362#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 363#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 --- 197 unchanged lines hidden (view full) --- 561#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 562#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 563#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 564#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 565 566#define BGE_TX_RINGS_MAX 4 567#define BGE_TX_RINGS_EXTSSRAM_MAX 16 568#define BGE_RX_RINGS_MAX 16 | 367#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 368#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 369#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 370#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 371#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 372#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 373#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 374#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 --- 197 unchanged lines hidden (view full) --- 572#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 573#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 574#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 575#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 576 577#define BGE_TX_RINGS_MAX 4 578#define BGE_TX_RINGS_EXTSSRAM_MAX 16 579#define BGE_RX_RINGS_MAX 16 |
| 580#define BGE_RX_RINGS_MAX_5717 17 |
|
| 569 570/* Ethernet MAC control registers */ 571#define BGE_MAC_MODE 0x0400 572#define BGE_MAC_STS 0x0404 573#define BGE_MAC_EVT_ENB 0x0408 574#define BGE_MAC_LED_CTL 0x040C 575#define BGE_MAC_ADDR1_LO 0x0410 576#define BGE_MAC_ADDR1_HI 0x0414 --- 261 unchanged lines hidden (view full) --- 838 839/* SGDIG config (not documented) */ 840#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 841#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 842#define BGE_SGDIGCFG_SEND 0x40000000 843#define BGE_SGDIGCFG_AUTO 0x80000000 844 845/* SGDIG status (not documented) */ | 581 582/* Ethernet MAC control registers */ 583#define BGE_MAC_MODE 0x0400 584#define BGE_MAC_STS 0x0404 585#define BGE_MAC_EVT_ENB 0x0408 586#define BGE_MAC_LED_CTL 0x040C 587#define BGE_MAC_ADDR1_LO 0x0410 588#define BGE_MAC_ADDR1_HI 0x0414 --- 261 unchanged lines hidden (view full) --- 850 851/* SGDIG config (not documented) */ 852#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 853#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 854#define BGE_SGDIGCFG_SEND 0x40000000 855#define BGE_SGDIGCFG_AUTO 0x80000000 856 857/* SGDIG status (not documented) */ |
| 858#define BGE_SGDIGSTS_DONE 0x00000002 859#define BGE_SGDIGSTS_IS_SERDES 0x00000100 |
|
| 846#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 847#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 | 860#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 861#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 |
| 848#define BGE_SGDIGSTS_DONE 0x00000002 | |
| 849 850 851/* MI communication register */ 852#define BGE_MICOMM_DATA 0x0000FFFF 853#define BGE_MICOMM_REG 0x001F0000 854#define BGE_MICOMM_PHY 0x03E00000 855#define BGE_MICOMM_CMD 0x0C000000 856#define BGE_MICOMM_READFAIL 0x10000000 --- 49 unchanged lines hidden (view full) --- 906#define BGE_LOCSTATS_IRQS 0x0CD4 907#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 908#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 909 910/* Send Data Initiator mode register */ 911#define BGE_SDIMODE_RESET 0x00000001 912#define BGE_SDIMODE_ENABLE 0x00000002 913#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 | 862 863 864/* MI communication register */ 865#define BGE_MICOMM_DATA 0x0000FFFF 866#define BGE_MICOMM_REG 0x001F0000 867#define BGE_MICOMM_PHY 0x03E00000 868#define BGE_MICOMM_CMD 0x0C000000 869#define BGE_MICOMM_READFAIL 0x10000000 --- 49 unchanged lines hidden (view full) --- 919#define BGE_LOCSTATS_IRQS 0x0CD4 920#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 921#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 922 923/* Send Data Initiator mode register */ 924#define BGE_SDIMODE_RESET 0x00000001 925#define BGE_SDIMODE_ENABLE 0x00000002 926#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 |
| 927#define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 |
|
| 914 915/* Send Data Initiator stats register */ 916#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 917 918/* Send Data Initiator stats control register */ 919#define BGE_SDISTATSCTL_ENABLE 0x00000001 920#define BGE_SDISTATSCTL_FASTER 0x00000002 921#define BGE_SDISTATSCTL_CLEAR 0x00000004 --- 261 unchanged lines hidden (view full) --- 1183#define BGE_RBDI_STATUS 0x2C04 1184#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1185#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1186#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1187#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1188#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1189#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1190 | 928 929/* Send Data Initiator stats register */ 930#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 931 932/* Send Data Initiator stats control register */ 933#define BGE_SDISTATSCTL_ENABLE 0x00000001 934#define BGE_SDISTATSCTL_FASTER 0x00000002 935#define BGE_SDISTATSCTL_CLEAR 0x00000004 --- 261 unchanged lines hidden (view full) --- 1197#define BGE_RBDI_STATUS 0x2C04 1198#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1199#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1200#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1201#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1202#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1203#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1204 |
| 1205#define BGE_STD_REPLENISH_LWM 0x2D00 1206#define BGE_JMB_REPLENISH_LWM 0x2D04 1207 |
|
| 1191/* Receive BD Initiator Mode register */ 1192#define BGE_RBDIMODE_RESET 0x00000001 1193#define BGE_RBDIMODE_ENABLE 0x00000002 1194#define BGE_RBDIMODE_ATTN 0x00000004 1195 1196/* Receive BD Initiator Status register */ 1197#define BGE_RBDISTAT_ATTN 0x00000004 1198 --- 297 unchanged lines hidden (view full) --- 1496#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1497#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1498#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1499#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1500#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1501#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1502#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1503#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 | 1208/* Receive BD Initiator Mode register */ 1209#define BGE_RBDIMODE_RESET 0x00000001 1210#define BGE_RBDIMODE_ENABLE 0x00000002 1211#define BGE_RBDIMODE_ATTN 0x00000004 1212 1213/* Receive BD Initiator Status register */ 1214#define BGE_RBDISTAT_ATTN 0x00000004 1215 --- 297 unchanged lines hidden (view full) --- 1513#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1514#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1515#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1516#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1517#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1518#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1519#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1520#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 |
| 1521#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 |
|
| 1504#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1505#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1506 1507/* Read DMA status register */ 1508#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1509#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1510#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1511#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 --- 551 unchanged lines hidden (view full) --- 2063 uint16_t bge_vlan_tag; 2064#endif 2065}; 2066 2067#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2068#define BGE_TXBDFLAG_IP_CSUM 0x0002 2069#define BGE_TXBDFLAG_END 0x0004 2070#define BGE_TXBDFLAG_IP_FRAG 0x0008 | 1522#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1523#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1524 1525/* Read DMA status register */ 1526#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1527#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1528#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1529#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 --- 551 unchanged lines hidden (view full) --- 2081 uint16_t bge_vlan_tag; 2082#endif 2083}; 2084 2085#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2086#define BGE_TXBDFLAG_IP_CSUM 0x0002 2087#define BGE_TXBDFLAG_END 0x0004 2088#define BGE_TXBDFLAG_IP_FRAG 0x0008 |
| 2089#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ |
|
| 2071#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 | 2090#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 |
| 2091#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */ 2092#define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ |
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| 2072#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2073#define BGE_TXBDFLAG_COAL_NOW 0x0080 2074#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2075#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 | 2093#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2094#define BGE_TXBDFLAG_COAL_NOW 0x0080 2095#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2096#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 |
| 2097#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */ 2098#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */ |
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| 2076#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 | 2099#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 |
| 2100#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */ 2101#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */ 2102#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */ |
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| 2077#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2078#define BGE_TXBDFLAG_NO_CRC 0x8000 2079 | 2103#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2104#define BGE_TXBDFLAG_NO_CRC 0x8000 2105 |
| 2106#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ 2107/* Bits [1:0] of the MSS header length. */ 2108#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ 2109 |
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| 2080#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2081 BGE_SEND_RING_1_TO_4 + \ 2082 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2083 2084struct bge_rx_bd { 2085 bge_hostaddr bge_addr; 2086#if BYTE_ORDER == LITTLE_ENDIAN 2087 uint16_t bge_len; --- 60 unchanged lines hidden (view full) --- 2148#define BGE_RXBDFLAG_END 0x0004 2149#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2150#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2151#define BGE_RXBDFLAG_ERROR 0x0400 2152#define BGE_RXBDFLAG_MINI_RING 0x0800 2153#define BGE_RXBDFLAG_IP_CSUM 0x1000 2154#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2155#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 | 2110#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2111 BGE_SEND_RING_1_TO_4 + \ 2112 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2113 2114struct bge_rx_bd { 2115 bge_hostaddr bge_addr; 2116#if BYTE_ORDER == LITTLE_ENDIAN 2117 uint16_t bge_len; --- 60 unchanged lines hidden (view full) --- 2178#define BGE_RXBDFLAG_END 0x0004 2179#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2180#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2181#define BGE_RXBDFLAG_ERROR 0x0400 2182#define BGE_RXBDFLAG_MINI_RING 0x0800 2183#define BGE_RXBDFLAG_IP_CSUM 0x1000 2184#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2185#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 |
| 2186#define BGE_RXBDFLAG_IPV6 0x8000 |
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| 2156 2157#define BGE_RXERRFLAG_BAD_CRC 0x0001 2158#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2159#define BGE_RXERRFLAG_LINK_LOST 0x0004 2160#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2161#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2162#define BGE_RXERRFLAG_RUNT 0x0020 2163#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2164#define BGE_RXERRFLAG_GIANT 0x0080 | 2187 2188#define BGE_RXERRFLAG_BAD_CRC 0x0001 2189#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2190#define BGE_RXERRFLAG_LINK_LOST 0x0004 2191#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2192#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2193#define BGE_RXERRFLAG_RUNT 0x0020 2194#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2195#define BGE_RXERRFLAG_GIANT 0x0080 |
| 2196#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ |
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| 2165 2166struct bge_sts_idx { 2167#if BYTE_ORDER == LITTLE_ENDIAN 2168 uint16_t bge_rx_prod_idx; 2169 uint16_t bge_tx_cons_idx; 2170#else 2171 uint16_t bge_tx_cons_idx; 2172 uint16_t bge_rx_prod_idx; 2173#endif 2174}; 2175 2176struct bge_status_block { 2177 uint32_t bge_status; | 2197 2198struct bge_sts_idx { 2199#if BYTE_ORDER == LITTLE_ENDIAN 2200 uint16_t bge_rx_prod_idx; 2201 uint16_t bge_tx_cons_idx; 2202#else 2203 uint16_t bge_tx_cons_idx; 2204 uint16_t bge_rx_prod_idx; 2205#endif 2206}; 2207 2208struct bge_status_block { 2209 uint32_t bge_status; |
| 2178 uint32_t bge_rsvd0; | 2210 uint32_t bge_status_tag; |
| 2179#if BYTE_ORDER == LITTLE_ENDIAN 2180 uint16_t bge_rx_jumbo_cons_idx; 2181 uint16_t bge_rx_std_cons_idx; 2182 uint16_t bge_rx_mini_cons_idx; 2183 uint16_t bge_rsvd1; 2184#else 2185 uint16_t bge_rx_std_cons_idx; 2186 uint16_t bge_rx_jumbo_cons_idx; --- 29 unchanged lines hidden (view full) --- 2216#define BCOM_DEVICEID_BCM5705K 0x1654 2217#define BCOM_DEVICEID_BCM5705F 0x166E 2218#define BCOM_DEVICEID_BCM5705M 0x165D 2219#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2220#define BCOM_DEVICEID_BCM5714C 0x1668 2221#define BCOM_DEVICEID_BCM5714S 0x1669 2222#define BCOM_DEVICEID_BCM5715 0x1678 2223#define BCOM_DEVICEID_BCM5715S 0x1679 | 2211#if BYTE_ORDER == LITTLE_ENDIAN 2212 uint16_t bge_rx_jumbo_cons_idx; 2213 uint16_t bge_rx_std_cons_idx; 2214 uint16_t bge_rx_mini_cons_idx; 2215 uint16_t bge_rsvd1; 2216#else 2217 uint16_t bge_rx_std_cons_idx; 2218 uint16_t bge_rx_jumbo_cons_idx; --- 29 unchanged lines hidden (view full) --- 2248#define BCOM_DEVICEID_BCM5705K 0x1654 2249#define BCOM_DEVICEID_BCM5705F 0x166E 2250#define BCOM_DEVICEID_BCM5705M 0x165D 2251#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2252#define BCOM_DEVICEID_BCM5714C 0x1668 2253#define BCOM_DEVICEID_BCM5714S 0x1669 2254#define BCOM_DEVICEID_BCM5715 0x1678 2255#define BCOM_DEVICEID_BCM5715S 0x1679 |
| 2256#define BCOM_DEVICEID_BCM5717 0x1655 2257#define BCOM_DEVICEID_BCM5718 0x1656 |
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| 2224#define BCOM_DEVICEID_BCM5720 0x1658 2225#define BCOM_DEVICEID_BCM5721 0x1659 2226#define BCOM_DEVICEID_BCM5722 0x165A 2227#define BCOM_DEVICEID_BCM5723 0x165B 2228#define BCOM_DEVICEID_BCM5750 0x1676 2229#define BCOM_DEVICEID_BCM5750M 0x167C 2230#define BCOM_DEVICEID_BCM5751 0x1677 2231#define BCOM_DEVICEID_BCM5751F 0x167E --- 480 unchanged lines hidden (view full) --- 2712 int bge_msicap; 2713 int bge_pcixcap; 2714 uint32_t bge_flags; 2715#define BGE_FLAG_TBI 0x00000001 2716#define BGE_FLAG_JUMBO 0x00000002 2717#define BGE_FLAG_EADDR 0x00000008 2718#define BGE_FLAG_MII_SERDES 0x00000010 2719#define BGE_FLAG_CPMU_PRESENT 0x00000020 | 2258#define BCOM_DEVICEID_BCM5720 0x1658 2259#define BCOM_DEVICEID_BCM5721 0x1659 2260#define BCOM_DEVICEID_BCM5722 0x165A 2261#define BCOM_DEVICEID_BCM5723 0x165B 2262#define BCOM_DEVICEID_BCM5750 0x1676 2263#define BCOM_DEVICEID_BCM5750M 0x167C 2264#define BCOM_DEVICEID_BCM5751 0x1677 2265#define BCOM_DEVICEID_BCM5751F 0x167E --- 480 unchanged lines hidden (view full) --- 2746 int bge_msicap; 2747 int bge_pcixcap; 2748 uint32_t bge_flags; 2749#define BGE_FLAG_TBI 0x00000001 2750#define BGE_FLAG_JUMBO 0x00000002 2751#define BGE_FLAG_EADDR 0x00000008 2752#define BGE_FLAG_MII_SERDES 0x00000010 2753#define BGE_FLAG_CPMU_PRESENT 0x00000020 |
| 2754#define BGE_FLAG_TAGGED_STATUS 0x00000040 |
|
| 2720#define BGE_FLAG_MSI 0x00000100 2721#define BGE_FLAG_PCIX 0x00000200 2722#define BGE_FLAG_PCIE 0x00000400 2723#define BGE_FLAG_TSO 0x00000800 | 2755#define BGE_FLAG_MSI 0x00000100 2756#define BGE_FLAG_PCIX 0x00000200 2757#define BGE_FLAG_PCIE 0x00000400 2758#define BGE_FLAG_TSO 0x00000800 |
| 2759#define BGE_FLAG_TSO3 0x00001000 2760#define BGE_FLAG_JUMBO_FRAME 0x00002000 |
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| 2724#define BGE_FLAG_5700_FAMILY 0x00010000 2725#define BGE_FLAG_5705_PLUS 0x00020000 2726#define BGE_FLAG_5714_FAMILY 0x00040000 2727#define BGE_FLAG_575X_PLUS 0x00080000 2728#define BGE_FLAG_5755_PLUS 0x00100000 2729#define BGE_FLAG_5788 0x00200000 | 2761#define BGE_FLAG_5700_FAMILY 0x00010000 2762#define BGE_FLAG_5705_PLUS 0x00020000 2763#define BGE_FLAG_5714_FAMILY 0x00040000 2764#define BGE_FLAG_575X_PLUS 0x00080000 2765#define BGE_FLAG_5755_PLUS 0x00100000 2766#define BGE_FLAG_5788 0x00200000 |
| 2767#define BGE_FLAG_5717_PLUS 0x00400000 |
|
| 2730#define BGE_FLAG_40BIT_BUG 0x01000000 2731#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2732#define BGE_FLAG_RX_ALIGNBUG 0x04000000 2733#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 2734 uint32_t bge_phy_flags; 2735#define BGE_PHY_WIRESPEED 0x00000001 2736#define BGE_PHY_ADC_BUG 0x00000002 2737#define BGE_PHY_5704_A0_BUG 0x00000004 --- 51 unchanged lines hidden --- | 2768#define BGE_FLAG_40BIT_BUG 0x01000000 2769#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2770#define BGE_FLAG_RX_ALIGNBUG 0x04000000 2771#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 2772 uint32_t bge_phy_flags; 2773#define BGE_PHY_WIRESPEED 0x00000001 2774#define BGE_PHY_ADC_BUG 0x00000002 2775#define BGE_PHY_5704_A0_BUG 0x00000004 --- 51 unchanged lines hidden --- |