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if_bge.c (214292) if_bge.c (214428)
1/*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 18 unchanged lines hidden (view full) ---

27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 18 unchanged lines hidden (view full) ---

27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 214292 2010-10-24 20:54:46Z yongari $");
35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 214428 2010-10-27 17:20:19Z yongari $");
36
37/*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external

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164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
36
37/*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external

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164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },

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284 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
285 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
286 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
287 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
288 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
289 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
290 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
291 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },

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286 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
287 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
288 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
289 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
290 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
291 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
292 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
293 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
294 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
295 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
292 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
293 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
294 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
295 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
296 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
297 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
298 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
299 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },

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327 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
328 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
329 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
330 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
331 /* 5754 and 5787 share the same ASIC ID */
332 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
333 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
334 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
296 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
297 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
298 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
299 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
300 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
301 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
302 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
303 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },

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331 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
332 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
333 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
334 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
335 /* 5754 and 5787 share the same ASIC ID */
336 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
337 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
338 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
339 { BGE_ASICREV_BCM5717, "unknown BCM5717" },
335
336 { 0, NULL }
337};
338
339#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
340#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
341#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
342#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
343#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
344#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
340
341 { 0, NULL }
342};
343
344#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
345#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
346#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
347#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
348#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
349#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
350#define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
345
346const struct bge_revision * bge_lookup_rev(uint32_t);
347const struct bge_vendor * bge_lookup_vendor(uint16_t);
348
349typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
350
351static int bge_probe(device_t);
352static int bge_attach(device_t);

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362
363static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
364static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
365static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
366static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
367static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
368
369static void bge_txeof(struct bge_softc *, uint16_t);
351
352const struct bge_revision * bge_lookup_rev(uint32_t);
353const struct bge_vendor * bge_lookup_vendor(uint16_t);
354
355typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
356
357static int bge_probe(device_t);
358static int bge_attach(device_t);

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368
369static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
370static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
371static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
372static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
373static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
374
375static void bge_txeof(struct bge_softc *, uint16_t);
376static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
370static int bge_rxeof(struct bge_softc *, uint16_t, int);
371
372static void bge_asf_driver_up (struct bge_softc *);
373static void bge_tick(void *);
374static void bge_stats_clear_regs(struct bge_softc *);
375static void bge_stats_update(struct bge_softc *);
376static void bge_stats_update_regs(struct bge_softc *);
377static struct mbuf *bge_check_short_dma(struct mbuf *);
378static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
377static int bge_rxeof(struct bge_softc *, uint16_t, int);
378
379static void bge_asf_driver_up (struct bge_softc *);
380static void bge_tick(void *);
381static void bge_stats_clear_regs(struct bge_softc *);
382static void bge_stats_update(struct bge_softc *);
383static void bge_stats_update_regs(struct bge_softc *);
384static struct mbuf *bge_check_short_dma(struct mbuf *);
385static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
379 uint16_t *);
386 uint16_t *, uint16_t *);
380static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
381
382static void bge_intr(void *);
383static int bge_msi_intr(void *);
384static void bge_intr_task(void *, int);
385static void bge_start_locked(struct ifnet *);
386static void bge_start(struct ifnet *);
387static int bge_ioctl(struct ifnet *, u_long, caddr_t);

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1344}
1345
1346/*
1347 * Do endian, PCI and DMA initialization.
1348 */
1349static int
1350bge_chipinit(struct bge_softc *sc)
1351{
387static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
388
389static void bge_intr(void *);
390static int bge_msi_intr(void *);
391static void bge_intr_task(void *, int);
392static void bge_start_locked(struct ifnet *);
393static void bge_start(struct ifnet *);
394static int bge_ioctl(struct ifnet *, u_long, caddr_t);

--- 956 unchanged lines hidden (view full) ---

1351}
1352
1353/*
1354 * Do endian, PCI and DMA initialization.
1355 */
1356static int
1357bge_chipinit(struct bge_softc *sc)
1358{
1352 uint32_t dma_rw_ctl;
1359 uint32_t dma_rw_ctl, misc_ctl;
1353 uint16_t val;
1354 int i;
1355
1356 /* Set endianness before we access any non-PCI registers. */
1360 uint16_t val;
1361 int i;
1362
1363 /* Set endianness before we access any non-PCI registers. */
1357 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1364 misc_ctl = BGE_INIT;
1365 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1366 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1367 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1358
1359 /* Clear the MAC control register */
1360 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1361
1362 /*
1363 * Clear the MAC statistics block in the NIC's
1364 * internal memory.
1365 */

--- 75 unchanged lines hidden (view full) ---

1441 }
1442 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1443 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1444 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1445 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1446 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1447 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1448 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1368
1369 /* Clear the MAC control register */
1370 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1371
1372 /*
1373 * Clear the MAC statistics block in the NIC's
1374 * internal memory.
1375 */

--- 75 unchanged lines hidden (view full) ---

1451 }
1452 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1453 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1454 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1455 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1456 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1457 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1458 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1459 if (BGE_IS_5717_PLUS(sc))
1460 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1449 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1450
1451 /*
1452 * Set up general mode register.
1453 */
1454 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1455 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1456 BGE_MODECTL_TX_NO_PHDR_CSUM);

--- 67 unchanged lines hidden (view full) ---

1524
1525 /* Configure DMA resource pool */
1526 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1527 BGE_DMA_DESCRIPTORS);
1528 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1529 }
1530
1531 /* Configure mbuf pool watermarks */
1461 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1462
1463 /*
1464 * Set up general mode register.
1465 */
1466 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1467 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1468 BGE_MODECTL_TX_NO_PHDR_CSUM);

--- 67 unchanged lines hidden (view full) ---

1536
1537 /* Configure DMA resource pool */
1538 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1539 BGE_DMA_DESCRIPTORS);
1540 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1541 }
1542
1543 /* Configure mbuf pool watermarks */
1532 if (!BGE_IS_5705_PLUS(sc)) {
1544 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) {
1545 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1546 if (sc->bge_ifp->if_mtu > ETHERMTU) {
1547 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1548 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1549 } else {
1550 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1551 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1552 }
1553 } else if (!BGE_IS_5705_PLUS(sc)) {
1533 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1534 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1535 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1536 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1537 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1538 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1539 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1540 } else {

--- 75 unchanged lines hidden (view full) ---

1616 /* Initialize the standard receive producer ring control block. */
1617 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1618 rcb->bge_hostaddr.bge_addr_lo =
1619 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1620 rcb->bge_hostaddr.bge_addr_hi =
1621 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1622 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1623 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1554 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1555 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1556 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1557 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1558 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1559 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1560 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1561 } else {

--- 75 unchanged lines hidden (view full) ---

1637 /* Initialize the standard receive producer ring control block. */
1638 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1639 rcb->bge_hostaddr.bge_addr_lo =
1640 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1641 rcb->bge_hostaddr.bge_addr_hi =
1642 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1643 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1644 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1624 if (BGE_IS_5705_PLUS(sc)) {
1645 if (BGE_IS_5717_PLUS(sc)) {
1625 /*
1646 /*
1647 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1648 * Bits 15-2 : Maximum RX frame size
1649 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
1650 * Bit 0 : Reserved
1651 */
1652 rcb->bge_maxlen_flags =
1653 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
1654 } else if (BGE_IS_5705_PLUS(sc)) {
1655 /*
1626 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1627 * Bits 15-2 : Reserved (should be 0)
1628 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1629 * Bit 0 : Reserved
1630 */
1631 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1632 } else {
1633 /*
1634 * Ring size is always XXX entries
1635 * Bits 31-16: Maximum RX frame size
1636 * Bits 15-2 : Reserved (should be 0)
1637 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1638 * Bit 0 : Reserved
1639 */
1640 rcb->bge_maxlen_flags =
1641 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1642 }
1656 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1657 * Bits 15-2 : Reserved (should be 0)
1658 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1659 * Bit 0 : Reserved
1660 */
1661 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1662 } else {
1663 /*
1664 * Ring size is always XXX entries
1665 * Bits 31-16: Maximum RX frame size
1666 * Bits 15-2 : Reserved (should be 0)
1667 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1668 * Bit 0 : Reserved
1669 */
1670 rcb->bge_maxlen_flags =
1671 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1672 }
1643 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1673 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
1674 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1675 else
1676 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1644 /* Write the standard receive producer ring control block. */
1645 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1646 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1647 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1648 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1649
1650 /* Reset the standard receive producer ring producer index. */
1651 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);

--- 12 unchanged lines hidden (view full) ---

1664 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1665 rcb->bge_hostaddr.bge_addr_hi =
1666 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1667 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1668 sc->bge_cdata.bge_rx_jumbo_ring_map,
1669 BUS_DMASYNC_PREREAD);
1670 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1671 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1677 /* Write the standard receive producer ring control block. */
1678 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1679 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1680 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1681 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1682
1683 /* Reset the standard receive producer ring producer index. */
1684 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);

--- 12 unchanged lines hidden (view full) ---

1697 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1698 rcb->bge_hostaddr.bge_addr_hi =
1699 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1700 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1701 sc->bge_cdata.bge_rx_jumbo_ring_map,
1702 BUS_DMASYNC_PREREAD);
1703 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1704 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1672 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1705 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
1706 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1707 else
1708 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1673 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1674 rcb->bge_hostaddr.bge_addr_hi);
1675 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1676 rcb->bge_hostaddr.bge_addr_lo);
1677 /* Program the jumbo receive producer ring RCB parameters. */
1678 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1679 rcb->bge_maxlen_flags);
1680 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);

--- 40 unchanged lines hidden (view full) ---

1721 if (BGE_IS_5705_PLUS(sc))
1722 val = 8;
1723 else
1724 val = BGE_STD_RX_RING_CNT / 8;
1725 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1726 if (BGE_IS_JUMBO_CAPABLE(sc))
1727 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1728 BGE_JUMBO_RX_RING_CNT/8);
1709 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1710 rcb->bge_hostaddr.bge_addr_hi);
1711 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1712 rcb->bge_hostaddr.bge_addr_lo);
1713 /* Program the jumbo receive producer ring RCB parameters. */
1714 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1715 rcb->bge_maxlen_flags);
1716 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);

--- 40 unchanged lines hidden (view full) ---

1757 if (BGE_IS_5705_PLUS(sc))
1758 val = 8;
1759 else
1760 val = BGE_STD_RX_RING_CNT / 8;
1761 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1762 if (BGE_IS_JUMBO_CAPABLE(sc))
1763 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1764 BGE_JUMBO_RX_RING_CNT/8);
1765 if (BGE_IS_5717_PLUS(sc)) {
1766 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1767 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1768 }
1729
1730 /*
1731 * Disable all send rings by setting the 'ring disabled' bit
1732 * in the flags field of all the TX send ring control blocks,
1733 * located in NIC memory.
1734 */
1735 if (!BGE_IS_5705_PLUS(sc))
1736 /* 5700 to 5704 had 16 send rings. */

--- 8 unchanged lines hidden (view full) ---

1745 vrcb += sizeof(struct bge_rcb);
1746 }
1747
1748 /* Configure send ring RCB 0 (we use only the first ring) */
1749 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1750 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1751 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1752 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1769
1770 /*
1771 * Disable all send rings by setting the 'ring disabled' bit
1772 * in the flags field of all the TX send ring control blocks,
1773 * located in NIC memory.
1774 */
1775 if (!BGE_IS_5705_PLUS(sc))
1776 /* 5700 to 5704 had 16 send rings. */

--- 8 unchanged lines hidden (view full) ---

1785 vrcb += sizeof(struct bge_rcb);
1786 }
1787
1788 /* Configure send ring RCB 0 (we use only the first ring) */
1789 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1790 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1791 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1792 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1753 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1754 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1793 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
1794 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1795 else
1796 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1797 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1755 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1756 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1757
1758 /*
1759 * Disable all receive return rings by setting the
1760 * 'ring diabled' bit in the flags field of all the receive
1761 * return ring control blocks, located in NIC memory.
1762 */
1798 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1799 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1800
1801 /*
1802 * Disable all receive return rings by setting the
1803 * 'ring diabled' bit in the flags field of all the receive
1804 * return ring control blocks, located in NIC memory.
1805 */
1763 if (!BGE_IS_5705_PLUS(sc))
1806 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) {
1807 /* Should be 17, use 16 until we get an SRAM map. */
1808 limit = 16;
1809 } else if (!BGE_IS_5705_PLUS(sc))
1764 limit = BGE_RX_RINGS_MAX;
1765 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1766 limit = 4;
1767 else
1768 limit = 1;
1769 /* Disable all receive return rings. */
1770 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1771 for (i = 0; i < limit; i++) {

--- 159 unchanged lines hidden (view full) ---

1931 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1932
1933 /* Turn on write DMA state machine */
1934 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1935 DELAY(40);
1936
1937 /* Turn on read DMA state machine */
1938 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1810 limit = BGE_RX_RINGS_MAX;
1811 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1812 limit = 4;
1813 else
1814 limit = 1;
1815 /* Disable all receive return rings. */
1816 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1817 for (i = 0; i < limit; i++) {

--- 159 unchanged lines hidden (view full) ---

1977 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1978
1979 /* Turn on write DMA state machine */
1980 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1981 DELAY(40);
1982
1983 /* Turn on read DMA state machine */
1984 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1985
1986 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
1987 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1988
1939 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1940 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1941 sc->bge_asicrev == BGE_ASICREV_BCM57780)
1942 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1943 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1944 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1945 if (sc->bge_flags & BGE_FLAG_PCIE)
1946 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1989 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1990 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1991 sc->bge_asicrev == BGE_ASICREV_BCM57780)
1992 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1993 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1994 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1995 if (sc->bge_flags & BGE_FLAG_PCIE)
1996 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1947 if (sc->bge_flags & BGE_FLAG_TSO) {
1997 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
1948 val |= BGE_RDMAMODE_TSO4_ENABLE;
1998 val |= BGE_RDMAMODE_TSO4_ENABLE;
1949 if (sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1999 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2000 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1950 sc->bge_asicrev == BGE_ASICREV_BCM57780)
1951 val |= BGE_RDMAMODE_TSO6_ENABLE;
1952 }
1953 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1954 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1955 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2001 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2002 val |= BGE_RDMAMODE_TSO6_ENABLE;
2003 }
2004 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2005 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2006 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1956 sc->bge_asicrev == BGE_ASICREV_BCM57780) {
2007 sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2008 BGE_IS_5717_PLUS(sc)) {
1957 /*
1958 * Enable fix for read DMA FIFO overruns.
1959 * The fix is to limit the number of RX BDs
1960 * the hardware would fetch at a fime.
1961 */
1962 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1963 CSR_READ_4(sc, BGE_RDMA_RSRVCTRL) |
1964 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);

--- 19 unchanged lines hidden (view full) ---

1984
1985 /* Turn on send data completion state machine */
1986 val = BGE_SDCMODE_ENABLE;
1987 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1988 val |= BGE_SDCMODE_CDELAY;
1989 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1990
1991 /* Turn on send data initiator state machine */
2009 /*
2010 * Enable fix for read DMA FIFO overruns.
2011 * The fix is to limit the number of RX BDs
2012 * the hardware would fetch at a fime.
2013 */
2014 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
2015 CSR_READ_4(sc, BGE_RDMA_RSRVCTRL) |
2016 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);

--- 19 unchanged lines hidden (view full) ---

2036
2037 /* Turn on send data completion state machine */
2038 val = BGE_SDCMODE_ENABLE;
2039 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2040 val |= BGE_SDCMODE_CDELAY;
2041 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2042
2043 /* Turn on send data initiator state machine */
1992 if (sc->bge_flags & BGE_FLAG_TSO)
1993 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08);
2044 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2045 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2046 BGE_SDIMODE_HW_LSO_PRE_DMA);
1994 else
1995 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1996
1997 /* Turn on send BD initiator state machine */
1998 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1999
2000 /* Turn on send BD selector state machine */
2001 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);

--- 97 unchanged lines hidden (view full) ---

2099 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2100 char model[64], buf[96];
2101 const struct bge_revision *br;
2102 const struct bge_vendor *v;
2103 uint32_t id;
2104
2105 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2106 BGE_PCIMISCCTL_ASICREV_SHIFT;
2047 else
2048 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2049
2050 /* Turn on send BD initiator state machine */
2051 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2052
2053 /* Turn on send BD selector state machine */
2054 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);

--- 97 unchanged lines hidden (view full) ---

2152 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2153 char model[64], buf[96];
2154 const struct bge_revision *br;
2155 const struct bge_vendor *v;
2156 uint32_t id;
2157
2158 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2159 BGE_PCIMISCCTL_ASICREV_SHIFT;
2107 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG)
2108 id = pci_read_config(dev,
2109 BGE_PCI_PRODID_ASICREV, 4);
2160 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2161 /*
2162 * Find the ASCI revision. Different chips
2163 * use different registers.
2164 */
2165 switch (pci_get_device(dev)) {
2166 case BCOM_DEVICEID_BCM5717:
2167 case BCOM_DEVICEID_BCM5718:
2168 id = pci_read_config(dev,
2169 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2170 break;
2171 default:
2172 id = pci_read_config(dev,
2173 BGE_PCI_PRODID_ASICREV, 4);
2174 }
2175 }
2110 br = bge_lookup_rev(id);
2111 v = bge_lookup_vendor(vid);
2112 {
2113#if __FreeBSD_version > 700024
2114 const char *pname;
2115
2116 if (bge_has_eaddr(sc) &&
2117 pci_get_vpd_ident(dev, &pname) == 0)

--- 300 unchanged lines hidden (view full) ---

2418 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2419 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag);
2420 if (error != 0) {
2421 device_printf(sc->bge_dev,
2422 "could not allocate buffer dma tag\n");
2423 return (ENOMEM);
2424 }
2425 /* Create tag for Tx mbufs. */
2176 br = bge_lookup_rev(id);
2177 v = bge_lookup_vendor(vid);
2178 {
2179#if __FreeBSD_version > 700024
2180 const char *pname;
2181
2182 if (bge_has_eaddr(sc) &&
2183 pci_get_vpd_ident(dev, &pname) == 0)

--- 300 unchanged lines hidden (view full) ---

2484 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2485 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag);
2486 if (error != 0) {
2487 device_printf(sc->bge_dev,
2488 "could not allocate buffer dma tag\n");
2489 return (ENOMEM);
2490 }
2491 /* Create tag for Tx mbufs. */
2426 if (sc->bge_flags & BGE_FLAG_TSO) {
2492 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2427 txsegsz = BGE_TSOSEG_SZ;
2428 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2429 } else {
2430 txsegsz = MCLBYTES;
2431 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2432 }
2433 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
2434 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,

--- 99 unchanged lines hidden (view full) ---

2534/*
2535 * Return true if MSI can be used with this device.
2536 */
2537static int
2538bge_can_use_msi(struct bge_softc *sc)
2539{
2540 int can_use_msi = 0;
2541
2493 txsegsz = BGE_TSOSEG_SZ;
2494 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2495 } else {
2496 txsegsz = MCLBYTES;
2497 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2498 }
2499 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
2500 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,

--- 99 unchanged lines hidden (view full) ---

2600/*
2601 * Return true if MSI can be used with this device.
2602 */
2603static int
2604bge_can_use_msi(struct bge_softc *sc)
2605{
2606 int can_use_msi = 0;
2607
2608 /* Disable MSI for polling(4). */
2609#ifdef DEVICE_POLLING
2610 return (0);
2611#endif
2542 switch (sc->bge_asicrev) {
2543 case BGE_ASICREV_BCM5714_A0:
2544 case BGE_ASICREV_BCM5714:
2545 /*
2546 * Apparently, MSI doesn't work when these chips are
2547 * configured in single-port mode.
2548 */
2549 if (bge_has_multiple_ports(sc))

--- 13 unchanged lines hidden (view full) ---

2563
2564static int
2565bge_attach(device_t dev)
2566{
2567 struct ifnet *ifp;
2568 struct bge_softc *sc;
2569 uint32_t hwcfg = 0, misccfg;
2570 u_char eaddr[ETHER_ADDR_LEN];
2612 switch (sc->bge_asicrev) {
2613 case BGE_ASICREV_BCM5714_A0:
2614 case BGE_ASICREV_BCM5714:
2615 /*
2616 * Apparently, MSI doesn't work when these chips are
2617 * configured in single-port mode.
2618 */
2619 if (bge_has_multiple_ports(sc))

--- 13 unchanged lines hidden (view full) ---

2633
2634static int
2635bge_attach(device_t dev)
2636{
2637 struct ifnet *ifp;
2638 struct bge_softc *sc;
2639 uint32_t hwcfg = 0, misccfg;
2640 u_char eaddr[ETHER_ADDR_LEN];
2571 int error, msicount, phy_addr, reg, rid, trys;
2641 int error, f, msicount, phy_addr, reg, rid, trys;
2572
2573 sc = device_get_softc(dev);
2574 sc->bge_dev = dev;
2575
2576 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2577
2578 /*
2579 * Map control/status registers.

--- 9 unchanged lines hidden (view full) ---

2589 error = ENXIO;
2590 goto fail;
2591 }
2592
2593 /* Save various chip information. */
2594 sc->bge_chipid =
2595 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2596 BGE_PCIMISCCTL_ASICREV_SHIFT;
2642
2643 sc = device_get_softc(dev);
2644 sc->bge_dev = dev;
2645
2646 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2647
2648 /*
2649 * Map control/status registers.

--- 9 unchanged lines hidden (view full) ---

2659 error = ENXIO;
2660 goto fail;
2661 }
2662
2663 /* Save various chip information. */
2664 sc->bge_chipid =
2665 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2666 BGE_PCIMISCCTL_ASICREV_SHIFT;
2597 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
2598 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV,
2599 4);
2667 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) {
2668 /*
2669 * Find the ASCI revision. Different chips use different
2670 * registers.
2671 */
2672 switch (pci_get_device(dev)) {
2673 case BCOM_DEVICEID_BCM5717:
2674 case BCOM_DEVICEID_BCM5718:
2675 sc->bge_chipid = pci_read_config(dev,
2676 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2677 break;
2678 default:
2679 sc->bge_chipid = pci_read_config(dev,
2680 BGE_PCI_PRODID_ASICREV, 4);
2681 }
2682 }
2600 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2601 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2602
2603 /* Set default PHY address. */
2604 phy_addr = 1;
2683 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2684 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2685
2686 /* Set default PHY address. */
2687 phy_addr = 1;
2688 /*
2689 * PHY address mapping for various devices.
2690 *
2691 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2692 * ---------+-------+-------+-------+-------+
2693 * BCM57XX | 1 | X | X | X |
2694 * BCM5704 | 1 | X | 1 | X |
2695 * BCM5717 | 1 | 8 | 2 | 9 |
2696 *
2697 * Other addresses may respond but they are not
2698 * IEEE compliant PHYs and should be ignored.
2699 */
2700 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) {
2701 f = pci_get_function(dev);
2702 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) {
2703 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2704 BGE_SGDIGSTS_IS_SERDES)
2705 phy_addr = f + 8;
2706 else
2707 phy_addr = f + 1;
2708 } else if (sc->bge_chipid == BGE_CHIPID_BCM5717_B0) {
2709 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2710 BGE_CPMU_PHY_STRAP_IS_SERDES)
2711 phy_addr = f + 8;
2712 else
2713 phy_addr = f + 1;
2714 }
2715 }
2605
2606 /*
2607 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2608 * 5705 A0 and A1 chips.
2609 */
2610 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2611 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2612 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2716
2717 /*
2718 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2719 * 5705 A0 and A1 chips.
2720 */
2721 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2722 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2723 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2613 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
2724 sc->bge_chipid != BGE_CHIPID_BCM5705_A1 &&
2725 !BGE_IS_5717_PLUS(sc))
2614 sc->bge_phy_flags |= BGE_PHY_WIRESPEED;
2615
2616 if (bge_has_eaddr(sc))
2617 sc->bge_flags |= BGE_FLAG_EADDR;
2618
2619 /* Save chipset family. */
2620 switch (sc->bge_asicrev) {
2726 sc->bge_phy_flags |= BGE_PHY_WIRESPEED;
2727
2728 if (bge_has_eaddr(sc))
2729 sc->bge_flags |= BGE_FLAG_EADDR;
2730
2731 /* Save chipset family. */
2732 switch (sc->bge_asicrev) {
2733 case BGE_ASICREV_BCM5717:
2734 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
2735 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
2736 BGE_FLAG_SHORT_DMA_BUG | BGE_FLAG_JUMBO_FRAME;
2737 break;
2621 case BGE_ASICREV_BCM5755:
2622 case BGE_ASICREV_BCM5761:
2623 case BGE_ASICREV_BCM5784:
2624 case BGE_ASICREV_BCM5785:
2625 case BGE_ASICREV_BCM5787:
2626 case BGE_ASICREV_BCM57780:
2627 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2628 BGE_FLAG_5705_PLUS;

--- 29 unchanged lines hidden (view full) ---

2658 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2659 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
2660 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2661 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
2662 if (pci_get_subvendor(dev) == DELL_VENDORID)
2663 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
2664 if ((BGE_IS_5705_PLUS(sc)) &&
2665 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2738 case BGE_ASICREV_BCM5755:
2739 case BGE_ASICREV_BCM5761:
2740 case BGE_ASICREV_BCM5784:
2741 case BGE_ASICREV_BCM5785:
2742 case BGE_ASICREV_BCM5787:
2743 case BGE_ASICREV_BCM57780:
2744 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2745 BGE_FLAG_5705_PLUS;

--- 29 unchanged lines hidden (view full) ---

2775 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2776 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
2777 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2778 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
2779 if (pci_get_subvendor(dev) == DELL_VENDORID)
2780 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
2781 if ((BGE_IS_5705_PLUS(sc)) &&
2782 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2783 sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
2666 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2667 sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2668 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2669 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2670 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2671 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2672 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
2673 pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
2674 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
2675 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
2676 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
2677 } else
2678 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
2679 }
2680
2681 /* Identify the chips that use an CPMU. */
2784 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2785 sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2786 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2787 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2788 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2789 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2790 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
2791 pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
2792 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
2793 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
2794 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
2795 } else
2796 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
2797 }
2798
2799 /* Identify the chips that use an CPMU. */
2682 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2800 if (BGE_IS_5717_PLUS(sc) ||
2801 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2683 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2684 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2685 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2686 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
2687 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
2688 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2689 else
2690 sc->bge_mi_mode = BGE_MIMODE_BASE;

--- 26 unchanged lines hidden (view full) ---

2717 * hardware based TSO. Moreover the firmware based TSO has one
2718 * known bug which can't handle TSO if ethernet header + IP/TCP
2719 * header is greater than 80 bytes. The workaround for the TSO
2720 * bug exist but it seems it's too expensive than not using
2721 * TSO at all. Some hardwares also have the TSO bug so limit
2722 * the TSO to the controllers that are not affected TSO issues
2723 * (e.g. 5755 or higher).
2724 */
2802 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2803 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2804 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2805 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
2806 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
2807 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2808 else
2809 sc->bge_mi_mode = BGE_MIMODE_BASE;

--- 26 unchanged lines hidden (view full) ---

2836 * hardware based TSO. Moreover the firmware based TSO has one
2837 * known bug which can't handle TSO if ethernet header + IP/TCP
2838 * header is greater than 80 bytes. The workaround for the TSO
2839 * bug exist but it seems it's too expensive than not using
2840 * TSO at all. Some hardwares also have the TSO bug so limit
2841 * the TSO to the controllers that are not affected TSO issues
2842 * (e.g. 5755 or higher).
2843 */
2725 if (BGE_IS_5755_PLUS(sc)) {
2844 if (BGE_IS_5717_PLUS(sc)) {
2845 /* BCM5717 requires different TSO configuration. */
2846 sc->bge_flags |= BGE_FLAG_TSO3;
2847 } else if (BGE_IS_5755_PLUS(sc)) {
2726 /*
2727 * BCM5754 and BCM5787 shares the same ASIC id so
2728 * explicit device id check is required.
2729 * Due to unknown reason TSO does not work on BCM5755M.
2730 */
2731 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
2732 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
2733 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)

--- 46 unchanged lines hidden (view full) ---

2780 } else
2781 msicount = 0;
2782 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2783 rid = 1;
2784 sc->bge_flags |= BGE_FLAG_MSI;
2785 }
2786 }
2787
2848 /*
2849 * BCM5754 and BCM5787 shares the same ASIC id so
2850 * explicit device id check is required.
2851 * Due to unknown reason TSO does not work on BCM5755M.
2852 */
2853 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
2854 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
2855 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)

--- 46 unchanged lines hidden (view full) ---

2902 } else
2903 msicount = 0;
2904 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2905 rid = 1;
2906 sc->bge_flags |= BGE_FLAG_MSI;
2907 }
2908 }
2909
2910 /*
2911 * All controllers except BCM5700 supports tagged status but
2912 * we use tagged status only for MSI case on BCM5717. Otherwise
2913 * MSI on BCM5717 does not work.
2914 */
2915#ifndef DEVICE_POLLING
2916 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
2917 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
2918#endif
2919
2788 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2789 RF_SHAREABLE | RF_ACTIVE);
2790
2791 if (sc->bge_irq == NULL) {
2792 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2793 error = ENXIO;
2794 goto fail;
2795 }

--- 47 unchanged lines hidden (view full) ---

2843 if (error) {
2844 device_printf(sc->bge_dev,
2845 "failed to read station address\n");
2846 error = ENXIO;
2847 goto fail;
2848 }
2849
2850 /* 5705 limits RX return ring to 512 entries. */
2920 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2921 RF_SHAREABLE | RF_ACTIVE);
2922
2923 if (sc->bge_irq == NULL) {
2924 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2925 error = ENXIO;
2926 goto fail;
2927 }

--- 47 unchanged lines hidden (view full) ---

2975 if (error) {
2976 device_printf(sc->bge_dev,
2977 "failed to read station address\n");
2978 error = ENXIO;
2979 goto fail;
2980 }
2981
2982 /* 5705 limits RX return ring to 512 entries. */
2851 if (BGE_IS_5705_PLUS(sc))
2983 if (BGE_IS_5717_PLUS(sc))
2984 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2985 else if (BGE_IS_5705_PLUS(sc))
2852 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2853 else
2854 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2855
2856 if (bge_dma_alloc(sc)) {
2857 device_printf(sc->bge_dev,
2858 "failed to allocate DMA resources\n");
2859 error = ENXIO;

--- 28 unchanged lines hidden (view full) ---

2888 ifp->if_start = bge_start;
2889 ifp->if_init = bge_init;
2890 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2891 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2892 IFQ_SET_READY(&ifp->if_snd);
2893 ifp->if_hwassist = sc->bge_csum_features;
2894 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2895 IFCAP_VLAN_MTU;
2986 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2987 else
2988 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2989
2990 if (bge_dma_alloc(sc)) {
2991 device_printf(sc->bge_dev,
2992 "failed to allocate DMA resources\n");
2993 error = ENXIO;

--- 28 unchanged lines hidden (view full) ---

3022 ifp->if_start = bge_start;
3023 ifp->if_init = bge_init;
3024 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
3025 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
3026 IFQ_SET_READY(&ifp->if_snd);
3027 ifp->if_hwassist = sc->bge_csum_features;
3028 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3029 IFCAP_VLAN_MTU;
2896 if ((sc->bge_flags & BGE_FLAG_TSO) != 0) {
3030 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
2897 ifp->if_hwassist |= CSUM_TSO;
2898 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
2899 }
2900#ifdef IFCAP_VLAN_HWCSUM
2901 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2902#endif
2903 ifp->if_capenable = ifp->if_capabilities;
2904#ifdef DEVICE_POLLING

--- 430 unchanged lines hidden (view full) ---

3335 sc->bge_flags & BGE_FLAG_TBI) {
3336 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3337 val = (val & ~0xFFF) | 0x880;
3338 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3339 }
3340
3341 /* XXX: Broadcom Linux driver. */
3342 if (sc->bge_flags & BGE_FLAG_PCIE &&
3031 ifp->if_hwassist |= CSUM_TSO;
3032 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
3033 }
3034#ifdef IFCAP_VLAN_HWCSUM
3035 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
3036#endif
3037 ifp->if_capenable = ifp->if_capabilities;
3038#ifdef DEVICE_POLLING

--- 430 unchanged lines hidden (view full) ---

3469 sc->bge_flags & BGE_FLAG_TBI) {
3470 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3471 val = (val & ~0xFFF) | 0x880;
3472 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3473 }
3474
3475 /* XXX: Broadcom Linux driver. */
3476 if (sc->bge_flags & BGE_FLAG_PCIE &&
3477 sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
3343 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
3344 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
3345 /* Enable Data FIFO protection. */
3346 val = CSR_READ_4(sc, 0x7C00);
3347 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3348 }
3349 DELAY(10000);
3350

--- 124 unchanged lines hidden (view full) ---

3475 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3476 cur_rx->bge_len);
3477 m->m_data += ETHER_ALIGN;
3478 }
3479#endif
3480 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3481 m->m_pkthdr.rcvif = ifp;
3482
3478 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
3479 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
3480 /* Enable Data FIFO protection. */
3481 val = CSR_READ_4(sc, 0x7C00);
3482 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3483 }
3484 DELAY(10000);
3485

--- 124 unchanged lines hidden (view full) ---

3610 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3611 cur_rx->bge_len);
3612 m->m_data += ETHER_ALIGN;
3613 }
3614#endif
3615 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3616 m->m_pkthdr.rcvif = ifp;
3617
3483 if (ifp->if_capenable & IFCAP_RXCSUM) {
3484 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3485 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3486 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3487 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3488 }
3489 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3490 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3491 m->m_pkthdr.csum_data =
3492 cur_rx->bge_tcp_udp_csum;
3493 m->m_pkthdr.csum_flags |=
3494 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3495 }
3496 }
3618 if (ifp->if_capenable & IFCAP_RXCSUM)
3619 bge_rxcsum(sc, cur_rx, m);
3497
3498 /*
3499 * If we received a packet with a vlan tag,
3500 * attach that information to the packet.
3501 */
3502 if (have_tag) {
3503#if __FreeBSD_version > 700022
3504 m->m_pkthdr.ether_vtag = vlan_tag;

--- 42 unchanged lines hidden (view full) ---

3547 */
3548 if (BGE_IS_5705_PLUS(sc))
3549 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3550#endif
3551 return (rx_npkts);
3552}
3553
3554static void
3620
3621 /*
3622 * If we received a packet with a vlan tag,
3623 * attach that information to the packet.
3624 */
3625 if (have_tag) {
3626#if __FreeBSD_version > 700022
3627 m->m_pkthdr.ether_vtag = vlan_tag;

--- 42 unchanged lines hidden (view full) ---

3670 */
3671 if (BGE_IS_5705_PLUS(sc))
3672 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3673#endif
3674 return (rx_npkts);
3675}
3676
3677static void
3678bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
3679{
3680
3681 if (BGE_IS_5717_PLUS(sc)) {
3682 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
3683 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3684 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3685 if ((cur_rx->bge_error_flag &
3686 BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
3687 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3688 }
3689 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
3690 m->m_pkthdr.csum_data =
3691 cur_rx->bge_tcp_udp_csum;
3692 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3693 CSUM_PSEUDO_HDR;
3694 }
3695 }
3696 } else {
3697 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3698 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3699 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3700 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3701 }
3702 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3703 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3704 m->m_pkthdr.csum_data =
3705 cur_rx->bge_tcp_udp_csum;
3706 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3707 CSUM_PSEUDO_HDR;
3708 }
3709 }
3710}
3711
3712static void
3555bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3556{
3557 struct bge_tx_bd *cur_tx;
3558 struct ifnet *ifp;
3559
3560 BGE_LOCK_ASSERT(sc);
3561
3562 /* Nothing to do. */

--- 100 unchanged lines hidden (view full) ---

3663 return (FILTER_HANDLED);
3664}
3665
3666static void
3667bge_intr_task(void *arg, int pending)
3668{
3669 struct bge_softc *sc;
3670 struct ifnet *ifp;
3713bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3714{
3715 struct bge_tx_bd *cur_tx;
3716 struct ifnet *ifp;
3717
3718 BGE_LOCK_ASSERT(sc);
3719
3720 /* Nothing to do. */

--- 100 unchanged lines hidden (view full) ---

3821 return (FILTER_HANDLED);
3822}
3823
3824static void
3825bge_intr_task(void *arg, int pending)
3826{
3827 struct bge_softc *sc;
3828 struct ifnet *ifp;
3671 uint32_t status;
3829 uint32_t status, status_tag;
3672 uint16_t rx_prod, tx_cons;
3673
3674 sc = (struct bge_softc *)arg;
3675 ifp = sc->bge_ifp;
3676
3677 BGE_LOCK(sc);
3678 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3679 BGE_UNLOCK(sc);

--- 4 unchanged lines hidden (view full) ---

3684 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3685 sc->bge_cdata.bge_status_map,
3686 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3687
3688 /* Save producer/consumer indexess. */
3689 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3690 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3691 status = sc->bge_ldata.bge_status_block->bge_status;
3830 uint16_t rx_prod, tx_cons;
3831
3832 sc = (struct bge_softc *)arg;
3833 ifp = sc->bge_ifp;
3834
3835 BGE_LOCK(sc);
3836 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3837 BGE_UNLOCK(sc);

--- 4 unchanged lines hidden (view full) ---

3842 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3843 sc->bge_cdata.bge_status_map,
3844 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3845
3846 /* Save producer/consumer indexess. */
3847 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3848 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3849 status = sc->bge_ldata.bge_status_block->bge_status;
3850 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
3692 sc->bge_ldata.bge_status_block->bge_status = 0;
3693 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3694 sc->bge_cdata.bge_status_map,
3695 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3851 sc->bge_ldata.bge_status_block->bge_status = 0;
3852 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3853 sc->bge_cdata.bge_status_map,
3854 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3855 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
3856 status_tag = 0;
3696
3697 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
3698 bge_link_upd(sc);
3699
3700 /* Let controller work. */
3857
3858 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
3859 bge_link_upd(sc);
3860
3861 /* Let controller work. */
3701 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3862 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
3702
3703 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3704 sc->bge_rx_saved_considx != rx_prod) {
3705 /* Check RX return ring producer/consumer. */
3706 BGE_UNLOCK(sc);
3707 bge_rxeof(sc, rx_prod, 0);
3708 BGE_LOCK(sc);
3709 }

--- 389 unchanged lines hidden (view full) ---

4099 if (n == NULL)
4100 m_freem(m);
4101 } else
4102 n = m;
4103 return (n);
4104}
4105
4106static struct mbuf *
3863
3864 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3865 sc->bge_rx_saved_considx != rx_prod) {
3866 /* Check RX return ring producer/consumer. */
3867 BGE_UNLOCK(sc);
3868 bge_rxeof(sc, rx_prod, 0);
3869 BGE_LOCK(sc);
3870 }

--- 389 unchanged lines hidden (view full) ---

4260 if (n == NULL)
4261 m_freem(m);
4262 } else
4263 n = m;
4264 return (n);
4265}
4266
4267static struct mbuf *
4107bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss)
4268bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
4269 uint16_t *flags)
4108{
4109 struct ip *ip;
4110 struct tcphdr *tcp;
4111 struct mbuf *n;
4112 uint16_t hlen;
4113 uint32_t poff;
4114
4115 if (M_WRITABLE(m) == 0) {

--- 26 unchanged lines hidden (view full) ---

4142 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
4143 /* Clear pseudo checksum computed by TCP stack. */
4144 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
4145 tcp->th_sum = 0;
4146 /*
4147 * Broadcom controllers uses different descriptor format for
4148 * TSO depending on ASIC revision. Due to TSO-capable firmware
4149 * license issue and lower performance of firmware based TSO
4270{
4271 struct ip *ip;
4272 struct tcphdr *tcp;
4273 struct mbuf *n;
4274 uint16_t hlen;
4275 uint32_t poff;
4276
4277 if (M_WRITABLE(m) == 0) {

--- 26 unchanged lines hidden (view full) ---

4304 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
4305 /* Clear pseudo checksum computed by TCP stack. */
4306 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
4307 tcp->th_sum = 0;
4308 /*
4309 * Broadcom controllers uses different descriptor format for
4310 * TSO depending on ASIC revision. Due to TSO-capable firmware
4311 * license issue and lower performance of firmware based TSO
4150 * we only support hardware based TSO which is applicable for
4151 * BCM5755 or newer controllers. Hardware based TSO uses 11
4152 * bits to store MSS and upper 5 bits are used to store IP/TCP
4153 * header length(including IP/TCP options). The header length
4154 * is expressed as 32 bits unit.
4312 * we only support hardware based TSO.
4155 */
4313 */
4314 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
4156 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
4315 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
4157 *mss |= (hlen << 11);
4316 if (sc->bge_flags & BGE_FLAG_TSO3) {
4317 /*
4318 * For BCM5717 and newer controllers, hardware based TSO
4319 * uses the 14 lower bits of the bge_mss field to store the
4320 * MSS and the upper 2 bits to store the lowest 2 bits of
4321 * the IP/TCP header length. The upper 6 bits of the header
4322 * length are stored in the bge_flags[14:10,4] field. Jumbo
4323 * frames are supported.
4324 */
4325 *mss |= ((hlen & 0x3) << 14);
4326 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
4327 } else {
4328 /*
4329 * For BCM5755 and newer controllers, hardware based TSO uses
4330 * the lower 11 bits to store the MSS and the upper 5 bits to
4331 * store the IP/TCP header length. Jumbo frames are not
4332 * supported.
4333 */
4334 *mss |= (hlen << 11);
4335 }
4158 return (m);
4159}
4160
4161/*
4162 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
4163 * pointers to descriptors.
4164 */
4165static int

--- 13 unchanged lines hidden (view full) ---

4179 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
4180 m->m_next != NULL) {
4181 *m_head = bge_check_short_dma(m);
4182 if (*m_head == NULL)
4183 return (ENOBUFS);
4184 m = *m_head;
4185 }
4186 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
4336 return (m);
4337}
4338
4339/*
4340 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
4341 * pointers to descriptors.
4342 */
4343static int

--- 13 unchanged lines hidden (view full) ---

4357 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
4358 m->m_next != NULL) {
4359 *m_head = bge_check_short_dma(m);
4360 if (*m_head == NULL)
4361 return (ENOBUFS);
4362 m = *m_head;
4363 }
4364 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
4187 *m_head = m = bge_setup_tso(sc, m, &mss);
4365 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
4188 if (*m_head == NULL)
4189 return (ENOBUFS);
4190 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
4191 BGE_TXBDFLAG_CPU_POST_DMA;
4192 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
4193 if (m->m_pkthdr.csum_flags & CSUM_IP)
4194 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
4195 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {

--- 6 unchanged lines hidden (view full) ---

4202 }
4203 }
4204 if (m->m_flags & M_LASTFRAG)
4205 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
4206 else if (m->m_flags & M_FRAG)
4207 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
4208 }
4209
4366 if (*m_head == NULL)
4367 return (ENOBUFS);
4368 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
4369 BGE_TXBDFLAG_CPU_POST_DMA;
4370 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
4371 if (m->m_pkthdr.csum_flags & CSUM_IP)
4372 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
4373 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {

--- 6 unchanged lines hidden (view full) ---

4380 }
4381 }
4382 if (m->m_flags & M_LASTFRAG)
4383 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
4384 else if (m->m_flags & M_FRAG)
4385 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
4386 }
4387
4210 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
4211 sc->bge_forced_collapse > 0 &&
4212 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
4213 /*
4214 * Forcedly collapse mbuf chains to overcome hardware
4215 * limitation which only support a single outstanding
4216 * DMA read operation.
4217 */
4218 if (sc->bge_forced_collapse == 1)
4219 m = m_defrag(m, M_DONTWAIT);
4220 else
4221 m = m_collapse(m, M_DONTWAIT, sc->bge_forced_collapse);
4222 if (m == NULL)
4223 m = *m_head;
4224 *m_head = m;
4388 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
4389 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
4390 m->m_pkthdr.len > ETHER_MAX_LEN)
4391 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
4392 if (sc->bge_forced_collapse > 0 &&
4393 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
4394 /*
4395 * Forcedly collapse mbuf chains to overcome hardware
4396 * limitation which only support a single outstanding
4397 * DMA read operation.
4398 */
4399 if (sc->bge_forced_collapse == 1)
4400 m = m_defrag(m, M_DONTWAIT);
4401 else
4402 m = m_collapse(m, M_DONTWAIT,
4403 sc->bge_forced_collapse);
4404 if (m == NULL)
4405 m = *m_head;
4406 *m_head = m;
4407 }
4225 }
4226
4227 map = sc->bge_cdata.bge_tx_dmamap[idx];
4228 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
4229 &nsegs, BUS_DMA_NOWAIT);
4230 if (error == EFBIG) {
4231 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
4232 if (m == NULL) {

--- 1427 unchanged lines hidden --- 		4408 }
4409
4410 map = sc->bge_cdata.bge_tx_dmamap[idx];
4411 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
4412 &nsegs, BUS_DMA_NOWAIT);
4413 if (error == EFBIG) {
4414 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
4415 if (m == NULL) {

--- 1427 unchanged lines hidden ---