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if_bge.c (165101) if_bge.c (165114)
1/*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 18 unchanged lines hidden (view full) ---

27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 18 unchanged lines hidden (view full) ---

27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 165101 2006-12-11 18:00:34Z jkim $");
35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 165114 2006-12-12 05:11:12Z scottl $");
36
37/*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external

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251 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
252 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
253 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
254 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
255 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
256 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
257 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
258 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
36
37/*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external

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251 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
252 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
253 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
254 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
255 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
256 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
257 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
258 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
259 /* 5784 and 5787 share the same ASIC ID */
260 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
261 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
262 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
259
260 { 0, NULL }
261};
262
263/*
264 * Some defaults for major revisions, so that newer steppings
265 * that we don't know about have a shot at working.
266 */

--- 4 unchanged lines hidden (view full) ---

271 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
272 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
273 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
274 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
275 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
276 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
277 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
278 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
263
264 { 0, NULL }
265};
266
267/*
268 * Some defaults for major revisions, so that newer steppings
269 * that we don't know about have a shot at working.
270 */

--- 4 unchanged lines hidden (view full) ---

275 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
276 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
277 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
278 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
279 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
280 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
281 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
282 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
279 { BGE_ASICREV_BCM5787, "unknown BCM5787" },
283 /* 5784 and 5787 share the same ASIC ID */
284 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
280
281 { 0, NULL }
282};
283
284#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
285#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
286#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
287#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)

--- 52 unchanged lines hidden (view full) ---

340static int bge_blockinit(struct bge_softc *);
341
342static uint32_t bge_readmem_ind(struct bge_softc *, int);
343static void bge_writemem_ind(struct bge_softc *, int, int);
344#ifdef notdef
345static uint32_t bge_readreg_ind(struct bge_softc *, int);
346#endif
347static void bge_writereg_ind(struct bge_softc *, int, int);
285
286 { 0, NULL }
287};
288
289#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
290#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
291#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
292#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)

--- 52 unchanged lines hidden (view full) ---

345static int bge_blockinit(struct bge_softc *);
346
347static uint32_t bge_readmem_ind(struct bge_softc *, int);
348static void bge_writemem_ind(struct bge_softc *, int, int);
349#ifdef notdef
350static uint32_t bge_readreg_ind(struct bge_softc *, int);
351#endif
352static void bge_writereg_ind(struct bge_softc *, int, int);
353static void bge_writemem_direct(struct bge_softc *, int, int) __unused;
348
349static int bge_miibus_readreg(device_t, int, int);
350static int bge_miibus_writereg(device_t, int, int, int);
351static void bge_miibus_statchg(device_t);
352#ifdef DEVICE_POLLING
353static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
354#endif
355
356#define BGE_RESET_START 1
357#define BGE_RESET_STOP 2
358static void bge_sig_post_reset(struct bge_softc *, int);
359static void bge_sig_legacy(struct bge_softc *, int);
360static void bge_sig_pre_reset(struct bge_softc *, int);
361static int bge_reset(struct bge_softc *);
362static void bge_link_upd(struct bge_softc *);
363
354
355static int bge_miibus_readreg(device_t, int, int);
356static int bge_miibus_writereg(device_t, int, int, int);
357static void bge_miibus_statchg(device_t);
358#ifdef DEVICE_POLLING
359static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
360#endif
361
362#define BGE_RESET_START 1
363#define BGE_RESET_STOP 2
364static void bge_sig_post_reset(struct bge_softc *, int);
365static void bge_sig_legacy(struct bge_softc *, int);
366static void bge_sig_pre_reset(struct bge_softc *, int);
367static int bge_reset(struct bge_softc *);
368static void bge_link_upd(struct bge_softc *);
369
370/*
371 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
372 * leak information to untrusted users. It is also known to cause alignment
373 * traps on certain architectures.
374 */
375#ifdef BGE_REGISTER_DEBUG
376static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
377static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
378static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
379#endif
380static void bge_add_sysctls(struct bge_softc *);
381
364static device_method_t bge_methods[] = {
365 /* Device interface */
366 DEVMETHOD(device_probe, bge_probe),
367 DEVMETHOD(device_attach, bge_attach),
368 DEVMETHOD(device_detach, bge_detach),
369 DEVMETHOD(device_shutdown, bge_shutdown),
370 DEVMETHOD(device_suspend, bge_suspend),
371 DEVMETHOD(device_resume, bge_resume),

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404 "Enable fake autonegotiation for certain blade systems");
405SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
406 "Allow ASF mode if available");
407
408static uint32_t
409bge_readmem_ind(struct bge_softc *sc, int off)
410{
411 device_t dev;
382static device_method_t bge_methods[] = {
383 /* Device interface */
384 DEVMETHOD(device_probe, bge_probe),
385 DEVMETHOD(device_attach, bge_attach),
386 DEVMETHOD(device_detach, bge_detach),
387 DEVMETHOD(device_shutdown, bge_shutdown),
388 DEVMETHOD(device_suspend, bge_suspend),
389 DEVMETHOD(device_resume, bge_resume),

--- 32 unchanged lines hidden (view full) ---

422 "Enable fake autonegotiation for certain blade systems");
423SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
424 "Allow ASF mode if available");
425
426static uint32_t
427bge_readmem_ind(struct bge_softc *sc, int off)
428{
429 device_t dev;
430 uint32_t val;
412
413 dev = sc->bge_dev;
414
415 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
431
432 dev = sc->bge_dev;
433
434 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
416 return (pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
435 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
436 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
437 return (val);
417}
418
419static void
420bge_writemem_ind(struct bge_softc *sc, int off, int val)
421{
422 device_t dev;
423
424 dev = sc->bge_dev;
425
426 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
427 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
438}
439
440static void
441bge_writemem_ind(struct bge_softc *sc, int off, int val)
442{
443 device_t dev;
444
445 dev = sc->bge_dev;
446
447 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
448 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
449 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
428}
429
430#ifdef notdef
431static uint32_t
432bge_readreg_ind(struct bge_softc *sc, int off)
433{
434 device_t dev;
435

--- 10 unchanged lines hidden (view full) ---

446 device_t dev;
447
448 dev = sc->bge_dev;
449
450 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
451 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
452}
453
450}
451
452#ifdef notdef
453static uint32_t
454bge_readreg_ind(struct bge_softc *sc, int off)
455{
456 device_t dev;
457

--- 10 unchanged lines hidden (view full) ---

468 device_t dev;
469
470 dev = sc->bge_dev;
471
472 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
473 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
474}
475
476static void
477bge_writemem_direct(struct bge_softc *sc, int off, int val)
478{
479 CSR_WRITE_4(sc, off, val);
480}
481
454/*
455 * Map a single buffer address.
456 */
457
458static void
459bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
460{
461 struct bge_dmamap_arg *ctx;

--- 726 unchanged lines hidden (view full) ---

1188}
1189
1190static int
1191bge_blockinit(struct bge_softc *sc)
1192{
1193 struct bge_rcb *rcb;
1194 bus_size_t vrcb;
1195 bge_hostaddr taddr;
482/*
483 * Map a single buffer address.
484 */
485
486static void
487bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
488{
489 struct bge_dmamap_arg *ctx;

--- 726 unchanged lines hidden (view full) ---

1216}
1217
1218static int
1219bge_blockinit(struct bge_softc *sc)
1220{
1221 struct bge_rcb *rcb;
1222 bus_size_t vrcb;
1223 bge_hostaddr taddr;
1224 uint32_t val;
1196 int i;
1197
1198 /*
1199 * Initialize the memory window pointer register so that
1200 * we can access the first 32K of internal NIC RAM. This will
1201 * allow us to set up the TX send ring RCBs and the RX return
1202 * ring RCBs, plus other things which live in NIC memory.
1203 */

--- 121 unchanged lines hidden (view full) ---

1325 rcb->bge_maxlen_flags);
1326 }
1327
1328 /*
1329 * Set the BD ring replentish thresholds. The recommended
1330 * values are 1/8th the number of descriptors allocated to
1331 * each ring.
1332 */
1225 int i;
1226
1227 /*
1228 * Initialize the memory window pointer register so that
1229 * we can access the first 32K of internal NIC RAM. This will
1230 * allow us to set up the TX send ring RCBs and the RX return
1231 * ring RCBs, plus other things which live in NIC memory.
1232 */

--- 121 unchanged lines hidden (view full) ---

1354 rcb->bge_maxlen_flags);
1355 }
1356
1357 /*
1358 * Set the BD ring replentish thresholds. The recommended
1359 * values are 1/8th the number of descriptors allocated to
1360 * each ring.
1361 */
1333 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1362 if (sc->bge_flags & BGE_FLAG_5705_PLUS)
1363 val = 8;
1364 else
1365 val = BGE_STD_RX_RING_CNT / 8;
1366
1367 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1334 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1335
1336 /*
1337 * Disable all unused send rings by setting the 'ring disabled'
1338 * bit in the flags field of all the TX send ring control blocks.
1339 * These are located in NIC memory.
1340 */
1341 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;

--- 153 unchanged lines hidden (view full) ---

1495 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1496 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1497#endif
1498
1499 /* Turn on DMA completion state machine */
1500 if (!(BGE_IS_5705_PLUS(sc)))
1501 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1502
1368 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1369
1370 /*
1371 * Disable all unused send rings by setting the 'ring disabled'
1372 * bit in the flags field of all the TX send ring control blocks.
1373 * These are located in NIC memory.
1374 */
1375 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;

--- 153 unchanged lines hidden (view full) ---

1529 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1530 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1531#endif
1532
1533 /* Turn on DMA completion state machine */
1534 if (!(BGE_IS_5705_PLUS(sc)))
1535 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1536
1537
1538 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1539
1540 /* Enable host coalescing bug fix. */
1541 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1542 sc->bge_asicrev == BGE_ASICREV_BCM5787)
1543 val |= (1 << 29);
1544
1503 /* Turn on write DMA state machine */
1545 /* Turn on write DMA state machine */
1504 CSR_WRITE_4(sc, BGE_WDMA_MODE,
1505 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1546 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1506
1507 /* Turn on read DMA state machine */
1508 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1509 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1510
1511 /* Turn on RX data completion state machine */
1512 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1513

--- 552 unchanged lines hidden (view full) ---

2066bge_attach(device_t dev)
2067{
2068 struct ifnet *ifp;
2069 struct bge_softc *sc;
2070 uint32_t hwcfg = 0;
2071 uint32_t mac_tmp = 0;
2072 u_char eaddr[6];
2073 int error = 0, rid;
1547
1548 /* Turn on read DMA state machine */
1549 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1550 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1551
1552 /* Turn on RX data completion state machine */
1553 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1554

--- 552 unchanged lines hidden (view full) ---

2107bge_attach(device_t dev)
2108{
2109 struct ifnet *ifp;
2110 struct bge_softc *sc;
2111 uint32_t hwcfg = 0;
2112 uint32_t mac_tmp = 0;
2113 u_char eaddr[6];
2114 int error = 0, rid;
2074 int trys;
2115 int trys, reg;
2075
2076 sc = device_get_softc(dev);
2077 sc->bge_dev = dev;
2078
2079 /*
2080 * Map control/status registers.
2081 */
2082 pci_enable_busmaster(dev);

--- 55 unchanged lines hidden (view full) ---

2138 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2139 /* Fall through */
2140
2141 case BGE_ASICREV_BCM5705:
2142 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2143 break;
2144 }
2145
2116
2117 sc = device_get_softc(dev);
2118 sc->bge_dev = dev;
2119
2120 /*
2121 * Map control/status registers.
2122 */
2123 pci_enable_busmaster(dev);

--- 55 unchanged lines hidden (view full) ---

2179 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2180 /* Fall through */
2181
2182 case BGE_ASICREV_BCM5705:
2183 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2184 break;
2185 }
2186
2146 /*
2147 * XXX: Broadcom Linux driver. Not in specs or eratta.
2148 * PCI-Express?
2149 */
2150 if (BGE_IS_5705_PLUS(sc)) {
2151 uint32_t v;
2152
2153 v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4);
2154 if (((v >> 8) & 0xff) == BGE_PCIE_CAPID_REG) {
2155 v = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
2156 if ((v & 0xff) == BGE_PCIE_CAPID)
2157 sc->bge_flags |= BGE_FLAG_PCIE;
2158 }
2187 /*
2188 * Check if this is a PCI-X or PCI Express device.
2189 */
2190#if __FreeBSD_version > 700010
2191 if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
2192 /*
2193 * Found a PCI Express capabilities register, this
2194 * must be a PCI Express device.
2195 */
2196 if (reg != 0)
2197 sc->bge_flags |= BGE_FLAG_PCIE;
2198 } else if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0) {
2199 if (reg != 0)
2200 sc->bge_flags |= BGE_FLAG_PCIX;
2159 }
2201 }
2202
2203#else
2204 if (sc->bge_flags & BGE_FLAG_5705_PLUS) {
2205 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
2206 if ((reg & 0xff) == BGE_PCIE_CAPID)
2207 sc->bge_flags |= BGE_FLAG_PCIE;
2208 } else {
2209 /*
2210 * Check if the device is in PCI-X Mode.
2211 * (This bit is not valid on PCI Express controllers.)
2212 */
2213 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2214 BGE_PCISTATE_PCI_BUSMODE) == 0)
2215 sc->bge_flags |= BGE_FLAG_PCIX;
2216 }
2217#endif
2160
2218
2161 /*
2162 * PCI-X ?
2163 */
2164 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2165 BGE_PCISTATE_PCI_BUSMODE) == 0)
2166 sc->bge_flags |= BGE_FLAG_PCIX;
2167
2168 /* Try to reset the chip. */
2169 if (bge_reset(sc)) {
2170 device_printf(sc->bge_dev, "chip reset failed\n");
2171 bge_release_resources(sc);
2172 error = ENXIO;
2173 goto fail;
2174 }
2175

--- 63 unchanged lines hidden (view full) ---

2239 error = ENXIO;
2240 goto fail;
2241 }
2242
2243 /* Set default tuneable values. */
2244 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2245 sc->bge_rx_coal_ticks = 150;
2246 sc->bge_tx_coal_ticks = 150;
2219 /* Try to reset the chip. */
2220 if (bge_reset(sc)) {
2221 device_printf(sc->bge_dev, "chip reset failed\n");
2222 bge_release_resources(sc);
2223 error = ENXIO;
2224 goto fail;
2225 }
2226

--- 63 unchanged lines hidden (view full) ---

2290 error = ENXIO;
2291 goto fail;
2292 }
2293
2294 /* Set default tuneable values. */
2295 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2296 sc->bge_rx_coal_ticks = 150;
2297 sc->bge_tx_coal_ticks = 150;
2247 sc->bge_rx_max_coal_bds = 64;
2248 sc->bge_tx_max_coal_bds = 128;
2298 sc->bge_rx_max_coal_bds = 10;
2299 sc->bge_tx_max_coal_bds = 10;
2249
2250 /* Set up ifnet structure */
2251 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2252 if (ifp == NULL) {
2253 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2254 bge_release_resources(sc);
2255 error = ENXIO;
2256 goto fail;

--- 122 unchanged lines hidden (view full) ---

2379 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2380 bge_intr, sc, &sc->bge_intrhand);
2381
2382 if (error) {
2383 bge_detach(dev);
2384 device_printf(sc->bge_dev, "couldn't set up irq\n");
2385 }
2386
2300
2301 /* Set up ifnet structure */
2302 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2303 if (ifp == NULL) {
2304 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2305 bge_release_resources(sc);
2306 error = ENXIO;
2307 goto fail;

--- 122 unchanged lines hidden (view full) ---

2430 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2431 bge_intr, sc, &sc->bge_intrhand);
2432
2433 if (error) {
2434 bge_detach(dev);
2435 device_printf(sc->bge_dev, "couldn't set up irq\n");
2436 }
2437
2438 bge_add_sysctls(sc);
2439
2387fail:
2388 return (error);
2389}
2390
2391static int
2392bge_detach(device_t dev)
2393{
2394 struct bge_softc *sc;

--- 58 unchanged lines hidden (view full) ---

2453 BGE_LOCK_DESTROY(sc);
2454}
2455
2456static int
2457bge_reset(struct bge_softc *sc)
2458{
2459 device_t dev;
2460 uint32_t cachesize, command, pcistate, reset;
2440fail:
2441 return (error);
2442}
2443
2444static int
2445bge_detach(device_t dev)
2446{
2447 struct bge_softc *sc;

--- 58 unchanged lines hidden (view full) ---

2506 BGE_LOCK_DESTROY(sc);
2507}
2508
2509static int
2510bge_reset(struct bge_softc *sc)
2511{
2512 device_t dev;
2513 uint32_t cachesize, command, pcistate, reset;
2514 void (*write_op)(struct bge_softc *, int, int);
2461 int i, val = 0;
2462
2463 dev = sc->bge_dev;
2464
2515 int i, val = 0;
2516
2517 dev = sc->bge_dev;
2518
2519 if (BGE_IS_5705_PLUS(sc) && !BGE_IS_5714_FAMILY(sc))
2520 if (sc->bge_flags & BGE_FLAG_PCIE)
2521 write_op = bge_writemem_direct;
2522 else
2523 write_op = bge_writemem_ind;
2524 else
2525 write_op = bge_writereg_ind;
2526
2465 /* Save some important PCI state. */
2466 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2467 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2468 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2469
2470 pci_write_config(dev, BGE_PCI_MISC_CTL,
2471 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2472 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2473
2527 /* Save some important PCI state. */
2528 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2529 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2530 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2531
2532 pci_write_config(dev, BGE_PCI_MISC_CTL,
2533 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2534 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2535
2536 /* Disable fastboot on controllers that support it. */
2537 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2538 sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2539 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2540 if (bootverbose)
2541 device_printf(sc->bge_dev, "%s: Disabling fastboot\n",
2542 __FUNCTION__);
2543 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2544 }
2545
2546 /*
2547 * Write the magic number to SRAM at offset 0xB50.
2548 * When firmware finishes its initialization it will
2549 * write ~BGE_MAGIC_NUMBER to the same location.
2550 */
2551 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2552
2474 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2475
2476 /* XXX: Broadcom Linux driver. */
2477 if (sc->bge_flags & BGE_FLAG_PCIE) {
2478 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2479 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2480 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2481 /* Prevent PCIE link training during global reset */
2482 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2483 reset |= (1<<29);
2484 }
2485 }
2486
2487 /*
2488 * Write the magic number to the firmware mailbox at 0xb50
2489 * so that the driver can synchronize with the firmware.
2490 */
2491 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2492
2553 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2554
2555 /* XXX: Broadcom Linux driver. */
2556 if (sc->bge_flags & BGE_FLAG_PCIE) {
2557 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2558 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2559 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2560 /* Prevent PCIE link training during global reset */
2561 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2562 reset |= (1<<29);
2563 }
2564 }
2565
2566 /*
2567 * Write the magic number to the firmware mailbox at 0xb50
2568 * so that the driver can synchronize with the firmware.
2569 */
2570 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2571
2572 /*
2573 * Set GPHY Power Down Override to leave GPHY
2574 * powered up in D0 uninitialized.
2575 */
2576 if (sc->bge_flags & BGE_FLAG_5705_PLUS)
2577 reset |= 0x04000000;
2578
2493 /* Issue global reset */
2579 /* Issue global reset */
2494 bge_writereg_ind(sc, BGE_MISC_CFG, reset);
2580 write_op(sc, BGE_MISC_CFG, reset);
2495
2496 DELAY(1000);
2497
2498 /* XXX: Broadcom Linux driver. */
2499 if (sc->bge_flags & BGE_FLAG_PCIE) {
2500 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2501 uint32_t v;
2502
2503 DELAY(500000); /* wait for link training to complete */
2504 v = pci_read_config(dev, 0xc4, 4);
2505 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2506 }
2581
2582 DELAY(1000);
2583
2584 /* XXX: Broadcom Linux driver. */
2585 if (sc->bge_flags & BGE_FLAG_PCIE) {
2586 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2587 uint32_t v;
2588
2589 DELAY(500000); /* wait for link training to complete */
2590 v = pci_read_config(dev, 0xc4, 4);
2591 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2592 }
2507 /* Set PCIE max payload size and clear error status. */
2593 /* Set PCIE max payload size to 128 bytes and clear error status. */
2508 pci_write_config(dev, 0xd8, 0xf5000, 4);
2509 }
2510
2511 /* Reset some of the PCI state that got zapped by reset. */
2512 pci_write_config(dev, BGE_PCI_MISC_CTL,
2513 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2514 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2515 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2516 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2594 pci_write_config(dev, 0xd8, 0xf5000, 4);
2595 }
2596
2597 /* Reset some of the PCI state that got zapped by reset. */
2598 pci_write_config(dev, BGE_PCI_MISC_CTL,
2599 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2600 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2601 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2602 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2517 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
2603 write_op(sc, BGE_MISC_CFG, (65 << 1));
2518
2519 /* Enable memory arbiter. */
2520 if (BGE_IS_5714_FAMILY(sc)) {
2521 uint32_t val;
2522
2523 val = CSR_READ_4(sc, BGE_MARB_MODE);
2524 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2525 } else
2526 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2527
2528 /*
2604
2605 /* Enable memory arbiter. */
2606 if (BGE_IS_5714_FAMILY(sc)) {
2607 uint32_t val;
2608
2609 val = CSR_READ_4(sc, BGE_MARB_MODE);
2610 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2611 } else
2612 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2613
2614 /*
2529 * Poll the value location we just wrote until
2530 * we see the 1's complement of the magic number.
2615 * Poll until we see the 1's complement of the magic number.
2531 * This indicates that the firmware initialization
2532 * is complete.
2533 */
2534 for (i = 0; i < BGE_TIMEOUT; i++) {
2535 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2536 if (val == ~BGE_MAGIC_NUMBER)
2537 break;
2538 DELAY(10);
2539 }
2540
2541 if (i == BGE_TIMEOUT) {
2616 * This indicates that the firmware initialization
2617 * is complete.
2618 */
2619 for (i = 0; i < BGE_TIMEOUT; i++) {
2620 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2621 if (val == ~BGE_MAGIC_NUMBER)
2622 break;
2623 DELAY(10);
2624 }
2625
2626 if (i == BGE_TIMEOUT) {
2542 device_printf(sc->bge_dev, "firmware handshake timed out\n");
2543 return(0);
2627 device_printf(sc->bge_dev, "firmware handshake timed out! "
2628 "found 0x%08X\n", val);
2544 }
2545
2546 /*
2547 * XXX Wait for the value of the PCISTATE register to
2548 * return to its original pre-reset state. This is a
2549 * fairly good indicator of reset completion. If we don't
2550 * wait for the reset to fully complete, trying to read
2551 * from the device's non-PCI registers may yield garbage
2552 * results.
2553 */
2554 for (i = 0; i < BGE_TIMEOUT; i++) {
2555 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2556 break;
2557 DELAY(10);
2558 }
2559
2629 }
2630
2631 /*
2632 * XXX Wait for the value of the PCISTATE register to
2633 * return to its original pre-reset state. This is a
2634 * fairly good indicator of reset completion. If we don't
2635 * wait for the reset to fully complete, trying to read
2636 * from the device's non-PCI registers may yield garbage
2637 * results.
2638 */
2639 for (i = 0; i < BGE_TIMEOUT; i++) {
2640 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2641 break;
2642 DELAY(10);
2643 }
2644
2645 if (sc->bge_flags & BGE_FLAG_PCIE) {
2646 reset = bge_readmem_ind(sc, 0x7c00);
2647 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2648 }
2649
2560 /* Fix up byte swapping. */
2561 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
2562 BGE_MODECTL_BYTESWAP_DATA);
2563
2564 /* Tell the ASF firmware we are up */
2565 if (sc->bge_asf_mode & ASF_STACKUP)
2566 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2567

--- 1374 unchanged lines hidden (view full) ---

3942 }
3943 }
3944
3945 /* Clear the attention. */
3946 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
3947 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
3948 BGE_MACSTAT_LINK_CHANGED);
3949}
2650 /* Fix up byte swapping. */
2651 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
2652 BGE_MODECTL_BYTESWAP_DATA);
2653
2654 /* Tell the ASF firmware we are up */
2655 if (sc->bge_asf_mode & ASF_STACKUP)
2656 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2657

--- 1374 unchanged lines hidden (view full) ---

4032 }
4033 }
4034
4035 /* Clear the attention. */
4036 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
4037 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
4038 BGE_MACSTAT_LINK_CHANGED);
4039}
4040
4041static void
4042bge_add_sysctls(struct bge_softc *sc)
4043{
4044 struct sysctl_ctx_list *ctx;
4045 struct sysctl_oid_list *children;
4046
4047 ctx = device_get_sysctl_ctx(sc->bge_dev);
4048 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4049
4050#ifdef BGE_REGISTER_DEBUG
4051 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4052 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4053 "Debug Information");
4054
4055 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4056 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4057 "Register Read");
4058
4059 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4060 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4061 "Memory Read");
4062
4063 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "stat_IfHcInOctets",
4064 CTLFLAG_RD,
4065 &sc->bge_ldata.bge_stats->rxstats.ifHCInOctets.bge_addr_lo,
4066 "Bytes received");
4067
4068 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "stat_IfHcOutOctets",
4069 CTLFLAG_RD,
4070 &sc->bge_ldata.bge_stats->txstats.ifHCOutOctets.bge_addr_lo,
4071 "Bytes received");
4072#endif
4073}
4074
4075#ifdef BGE_REGISTER_DEBUG
4076static int
4077bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4078{
4079 struct bge_softc *sc;
4080 uint16_t *sbdata;
4081 int error;
4082 int result;
4083 int i, j;
4084
4085 result = -1;
4086 error = sysctl_handle_int(oidp, &result, 0, req);
4087 if (error || (req->newptr == NULL))
4088 return (error);
4089
4090 if (result == 1) {
4091 sc = (struct bge_softc *)arg1;
4092
4093 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
4094 printf("Status Block:\n");
4095 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
4096 printf("%06x:", i);
4097 for (j = 0; j < 8; j++) {
4098 printf(" %04x", sbdata[i]);
4099 i += 4;
4100 }
4101 printf("\n");
4102 }
4103
4104 printf("Registers:\n");
4105 for (i = 0x800; i < 0xa00; ) {
4106 printf("%06x:", i);
4107 for (j = 0; j < 8; j++) {
4108 printf(" %08x", CSR_READ_4(sc, i));
4109 i += 4;
4110 }
4111 printf("\n");
4112 }
4113
4114 printf("Hardware Flags:\n");
4115 if (sc->bge_flags & BGE_FLAG_575X_PLUS)
4116 printf(" - 575X Plus\n");
4117 if (sc->bge_flags & BGE_FLAG_5705_PLUS)
4118 printf(" - 5705 Plus\n");
4119 if (sc->bge_flags & BGE_FLAG_JUMBO)
4120 printf(" - Supports Jumbo Frames\n");
4121 if (sc->bge_flags & BGE_FLAG_PCIX)
4122 printf(" - PCI-X Bus\n");
4123 if (sc->bge_flags & BGE_FLAG_PCIE)
4124 printf(" - PCI Express Bus\n");
4125 if (sc->bge_flags & BGE_FLAG_NO3LED)
4126 printf(" - No 3 LEDs\n");
4127 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
4128 printf(" - RX Alignment Bug\n");
4129 }
4130
4131 return (error);
4132}
4133
4134static int
4135bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
4136{
4137 struct bge_softc *sc;
4138 int error;
4139 uint16_t result;
4140 uint32_t val;
4141
4142 result = -1;
4143 error = sysctl_handle_int(oidp, &result, 0, req);
4144 if (error || (req->newptr == NULL))
4145 return (error);
4146
4147 if (result < 0x8000) {
4148 sc = (struct bge_softc *)arg1;
4149 val = CSR_READ_4(sc, result);
4150 printf("reg 0x%06X = 0x%08X\n", result, val);
4151 }
4152
4153 return (error);
4154}
4155
4156static int
4157bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
4158{
4159 struct bge_softc *sc;
4160 int error;
4161 uint16_t result;
4162 uint32_t val;
4163
4164 result = -1;
4165 error = sysctl_handle_int(oidp, &result, 0, req);
4166 if (error || (req->newptr == NULL))
4167 return (error);
4168
4169 if (result < 0x8000) {
4170 sc = (struct bge_softc *)arg1;
4171 val = bge_readmem_ind(sc, result);
4172 printf("mem 0x%06X = 0x%08X\n", result, val);
4173 }
4174
4175 return (error);
4176}
4177#endif