148 { 0, 0, NULL }
149};
150
151static int bge_probe (device_t);
152static int bge_attach (device_t);
153static int bge_detach (device_t);
154static void bge_release_resources
155 (struct bge_softc *);
156static void bge_txeof (struct bge_softc *);
157static void bge_rxeof (struct bge_softc *);
158
159static void bge_tick (void *);
160static void bge_stats_update (struct bge_softc *);
161static int bge_encap (struct bge_softc *, struct mbuf *,
162 u_int32_t *);
163
164static void bge_intr (void *);
165static void bge_start (struct ifnet *);
166static int bge_ioctl (struct ifnet *, u_long, caddr_t);
167static void bge_init (void *);
168static void bge_stop (struct bge_softc *);
169static void bge_watchdog (struct ifnet *);
170static void bge_shutdown (device_t);
171static int bge_ifmedia_upd (struct ifnet *);
172static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *);
173
174static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *);
175static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int);
176
177static u_int32_t bge_crc (caddr_t);
178static void bge_setmulti (struct bge_softc *);
179
180static void bge_handle_events (struct bge_softc *);
181static int bge_alloc_jumbo_mem (struct bge_softc *);
182static void bge_free_jumbo_mem (struct bge_softc *);
183static void *bge_jalloc (struct bge_softc *);
184static void bge_jfree (void *, void *);
185static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *);
186static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *);
187static int bge_init_rx_ring_std (struct bge_softc *);
188static void bge_free_rx_ring_std (struct bge_softc *);
189static int bge_init_rx_ring_jumbo (struct bge_softc *);
190static void bge_free_rx_ring_jumbo (struct bge_softc *);
191static void bge_free_tx_ring (struct bge_softc *);
192static int bge_init_tx_ring (struct bge_softc *);
193
194static int bge_chipinit (struct bge_softc *);
195static int bge_blockinit (struct bge_softc *);
196
197#ifdef notdef
198static u_int8_t bge_vpd_readbyte(struct bge_softc *, int);
199static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int);
200static void bge_vpd_read (struct bge_softc *);
201#endif
202
203static u_int32_t bge_readmem_ind
204 (struct bge_softc *, int);
205static void bge_writemem_ind (struct bge_softc *, int, int);
206#ifdef notdef
207static u_int32_t bge_readreg_ind
208 (struct bge_softc *, int);
209#endif
210static void bge_writereg_ind (struct bge_softc *, int, int);
211
212static int bge_miibus_readreg (device_t, int, int);
213static int bge_miibus_writereg (device_t, int, int, int);
214static void bge_miibus_statchg (device_t);
215
216static void bge_reset (struct bge_softc *);
217static void bge_phy_hack (struct bge_softc *);
218
219static device_method_t bge_methods[] = {
220 /* Device interface */
221 DEVMETHOD(device_probe, bge_probe),
222 DEVMETHOD(device_attach, bge_attach),
223 DEVMETHOD(device_detach, bge_detach),
224 DEVMETHOD(device_shutdown, bge_shutdown),
225
226 /* bus interface */
227 DEVMETHOD(bus_print_child, bus_generic_print_child),
228 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
229
230 /* MII interface */
231 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
232 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
233 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
234
235 { 0, 0 }
236};
237
238static driver_t bge_driver = {
239 "bge",
240 bge_methods,
241 sizeof(struct bge_softc)
242};
243
244static devclass_t bge_devclass;
245
246DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
247DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
248
249static u_int32_t
250bge_readmem_ind(sc, off)
251 struct bge_softc *sc;
252 int off;
253{
254 device_t dev;
255
256 dev = sc->bge_dev;
257
258 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
259 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
260}
261
262static void
263bge_writemem_ind(sc, off, val)
264 struct bge_softc *sc;
265 int off, val;
266{
267 device_t dev;
268
269 dev = sc->bge_dev;
270
271 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
272 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
273
274 return;
275}
276
277#ifdef notdef
278static u_int32_t
279bge_readreg_ind(sc, off)
280 struct bge_softc *sc;
281 int off;
282{
283 device_t dev;
284
285 dev = sc->bge_dev;
286
287 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
288 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
289}
290#endif
291
292static void
293bge_writereg_ind(sc, off, val)
294 struct bge_softc *sc;
295 int off, val;
296{
297 device_t dev;
298
299 dev = sc->bge_dev;
300
301 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
302 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
303
304 return;
305}
306
307#ifdef notdef
308static u_int8_t
309bge_vpd_readbyte(sc, addr)
310 struct bge_softc *sc;
311 int addr;
312{
313 int i;
314 device_t dev;
315 u_int32_t val;
316
317 dev = sc->bge_dev;
318 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
319 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
320 DELAY(10);
321 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
322 break;
323 }
324
325 if (i == BGE_TIMEOUT) {
326 printf("bge%d: VPD read timed out\n", sc->bge_unit);
327 return(0);
328 }
329
330 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
331
332 return((val >> ((addr % 4) * 8)) & 0xFF);
333}
334
335static void
336bge_vpd_read_res(sc, res, addr)
337 struct bge_softc *sc;
338 struct vpd_res *res;
339 int addr;
340{
341 int i;
342 u_int8_t *ptr;
343
344 ptr = (u_int8_t *)res;
345 for (i = 0; i < sizeof(struct vpd_res); i++)
346 ptr[i] = bge_vpd_readbyte(sc, i + addr);
347
348 return;
349}
350
351static void
352bge_vpd_read(sc)
353 struct bge_softc *sc;
354{
355 int pos = 0, i;
356 struct vpd_res res;
357
358 if (sc->bge_vpd_prodname != NULL)
359 free(sc->bge_vpd_prodname, M_DEVBUF);
360 if (sc->bge_vpd_readonly != NULL)
361 free(sc->bge_vpd_readonly, M_DEVBUF);
362 sc->bge_vpd_prodname = NULL;
363 sc->bge_vpd_readonly = NULL;
364
365 bge_vpd_read_res(sc, &res, pos);
366
367 if (res.vr_id != VPD_RES_ID) {
368 printf("bge%d: bad VPD resource id: expected %x got %x\n",
369 sc->bge_unit, VPD_RES_ID, res.vr_id);
370 return;
371 }
372
373 pos += sizeof(res);
374 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
375 for (i = 0; i < res.vr_len; i++)
376 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
377 sc->bge_vpd_prodname[i] = '\0';
378 pos += i;
379
380 bge_vpd_read_res(sc, &res, pos);
381
382 if (res.vr_id != VPD_RES_READ) {
383 printf("bge%d: bad VPD resource id: expected %x got %x\n",
384 sc->bge_unit, VPD_RES_READ, res.vr_id);
385 return;
386 }
387
388 pos += sizeof(res);
389 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
390 for (i = 0; i < res.vr_len + 1; i++)
391 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
392
393 return;
394}
395#endif
396
397/*
398 * Read a byte of data stored in the EEPROM at address 'addr.' The
399 * BCM570x supports both the traditional bitbang interface and an
400 * auto access interface for reading the EEPROM. We use the auto
401 * access method.
402 */
403static u_int8_t
404bge_eeprom_getbyte(sc, addr, dest)
405 struct bge_softc *sc;
406 int addr;
407 u_int8_t *dest;
408{
409 int i;
410 u_int32_t byte = 0;
411
412 /*
413 * Enable use of auto EEPROM access so we can avoid
414 * having to use the bitbang method.
415 */
416 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
417
418 /* Reset the EEPROM, load the clock period. */
419 CSR_WRITE_4(sc, BGE_EE_ADDR,
420 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
421 DELAY(20);
422
423 /* Issue the read EEPROM command. */
424 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
425
426 /* Wait for completion */
427 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
428 DELAY(10);
429 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
430 break;
431 }
432
433 if (i == BGE_TIMEOUT) {
434 printf("bge%d: eeprom read timed out\n", sc->bge_unit);
435 return(0);
436 }
437
438 /* Get result. */
439 byte = CSR_READ_4(sc, BGE_EE_DATA);
440
441 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
442
443 return(0);
444}
445
446/*
447 * Read a sequence of bytes from the EEPROM.
448 */
449static int
450bge_read_eeprom(sc, dest, off, cnt)
451 struct bge_softc *sc;
452 caddr_t dest;
453 int off;
454 int cnt;
455{
456 int err = 0, i;
457 u_int8_t byte = 0;
458
459 for (i = 0; i < cnt; i++) {
460 err = bge_eeprom_getbyte(sc, off + i, &byte);
461 if (err)
462 break;
463 *(dest + i) = byte;
464 }
465
466 return(err ? 1 : 0);
467}
468
469static int
470bge_miibus_readreg(dev, phy, reg)
471 device_t dev;
472 int phy, reg;
473{
474 struct bge_softc *sc;
475 struct ifnet *ifp;
476 u_int32_t val;
477 int i;
478
479 sc = device_get_softc(dev);
480 ifp = &sc->arpcom.ac_if;
481
482 if (sc->bge_asicrev == BGE_ASICREV_BCM5701_B5 && phy != 1)
483 return(0);
484
485 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
486 BGE_MIPHY(phy)|BGE_MIREG(reg));
487
488 for (i = 0; i < BGE_TIMEOUT; i++) {
489 val = CSR_READ_4(sc, BGE_MI_COMM);
490 if (!(val & BGE_MICOMM_BUSY))
491 break;
492 }
493
494 if (i == BGE_TIMEOUT) {
495 printf("bge%d: PHY read timed out\n", sc->bge_unit);
496 return(0);
497 }
498
499 val = CSR_READ_4(sc, BGE_MI_COMM);
500
501 if (val & BGE_MICOMM_READFAIL)
502 return(0);
503
504 return(val & 0xFFFF);
505}
506
507static int
508bge_miibus_writereg(dev, phy, reg, val)
509 device_t dev;
510 int phy, reg, val;
511{
512 struct bge_softc *sc;
513 int i;
514
515 sc = device_get_softc(dev);
516
517 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
518 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
519
520 for (i = 0; i < BGE_TIMEOUT; i++) {
521 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
522 break;
523 }
524
525 if (i == BGE_TIMEOUT) {
526 printf("bge%d: PHY read timed out\n", sc->bge_unit);
527 return(0);
528 }
529
530 return(0);
531}
532
533static void
534bge_miibus_statchg(dev)
535 device_t dev;
536{
537 struct bge_softc *sc;
538 struct mii_data *mii;
539
540 sc = device_get_softc(dev);
541 mii = device_get_softc(sc->bge_miibus);
542
543 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
544 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
545 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
546 } else {
547 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
548 }
549
550 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
551 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
552 } else {
553 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
554 }
555
556 bge_phy_hack(sc);
557
558 return;
559}
560
561/*
562 * Handle events that have triggered interrupts.
563 */
564static void
565bge_handle_events(sc)
566 struct bge_softc *sc;
567{
568
569 return;
570}
571
572/*
573 * Memory management for jumbo frames.
574 */
575
576static int
577bge_alloc_jumbo_mem(sc)
578 struct bge_softc *sc;
579{
580 caddr_t ptr;
581 register int i;
582 struct bge_jpool_entry *entry;
583
584 /* Grab a big chunk o' storage. */
585 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
586 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
587
588 if (sc->bge_cdata.bge_jumbo_buf == NULL) {
589 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit);
590 return(ENOBUFS);
591 }
592
593 SLIST_INIT(&sc->bge_jfree_listhead);
594 SLIST_INIT(&sc->bge_jinuse_listhead);
595
596 /*
597 * Now divide it up into 9K pieces and save the addresses
598 * in an array.
599 */
600 ptr = sc->bge_cdata.bge_jumbo_buf;
601 for (i = 0; i < BGE_JSLOTS; i++) {
602 sc->bge_cdata.bge_jslots[i] = ptr;
603 ptr += BGE_JLEN;
604 entry = malloc(sizeof(struct bge_jpool_entry),
605 M_DEVBUF, M_NOWAIT);
606 if (entry == NULL) {
607 contigfree(sc->bge_cdata.bge_jumbo_buf,
608 BGE_JMEM, M_DEVBUF);
609 sc->bge_cdata.bge_jumbo_buf = NULL;
610 printf("bge%d: no memory for jumbo "
611 "buffer queue!\n", sc->bge_unit);
612 return(ENOBUFS);
613 }
614 entry->slot = i;
615 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
616 entry, jpool_entries);
617 }
618
619 return(0);
620}
621
622static void
623bge_free_jumbo_mem(sc)
624 struct bge_softc *sc;
625{
626 int i;
627 struct bge_jpool_entry *entry;
628
629 for (i = 0; i < BGE_JSLOTS; i++) {
630 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
631 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
632 free(entry, M_DEVBUF);
633 }
634
635 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
636
637 return;
638}
639
640/*
641 * Allocate a jumbo buffer.
642 */
643static void *
644bge_jalloc(sc)
645 struct bge_softc *sc;
646{
647 struct bge_jpool_entry *entry;
648
649 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
650
651 if (entry == NULL) {
652 printf("bge%d: no free jumbo buffers\n", sc->bge_unit);
653 return(NULL);
654 }
655
656 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
657 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
658 return(sc->bge_cdata.bge_jslots[entry->slot]);
659}
660
661/*
662 * Release a jumbo buffer.
663 */
664static void
665bge_jfree(buf, args)
666 void *buf;
667 void *args;
668{
669 struct bge_jpool_entry *entry;
670 struct bge_softc *sc;
671 int i;
672
673 /* Extract the softc struct pointer. */
674 sc = (struct bge_softc *)args;
675
676 if (sc == NULL)
677 panic("bge_jfree: can't find softc pointer!");
678
679 /* calculate the slot this buffer belongs to */
680
681 i = ((vm_offset_t)buf
682 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
683
684 if ((i < 0) || (i >= BGE_JSLOTS))
685 panic("bge_jfree: asked to free buffer that we don't manage!");
686
687 entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
688 if (entry == NULL)
689 panic("bge_jfree: buffer not in use!");
690 entry->slot = i;
691 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries);
692 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries);
693
694 return;
695}
696
697
698/*
699 * Intialize a standard receive ring descriptor.
700 */
701static int
702bge_newbuf_std(sc, i, m)
703 struct bge_softc *sc;
704 int i;
705 struct mbuf *m;
706{
707 struct mbuf *m_new = NULL;
708 struct bge_rx_bd *r;
709
710 if (m == NULL) {
711 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
712 if (m_new == NULL) {
713 return(ENOBUFS);
714 }
715
716 MCLGET(m_new, M_DONTWAIT);
717 if (!(m_new->m_flags & M_EXT)) {
718 m_freem(m_new);
719 return(ENOBUFS);
720 }
721 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
722 } else {
723 m_new = m;
724 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
725 m_new->m_data = m_new->m_ext.ext_buf;
726 }
727
728 if (!sc->bge_rx_alignment_bug)
729 m_adj(m_new, ETHER_ALIGN);
730 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
731 r = &sc->bge_rdata->bge_rx_std_ring[i];
732 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t));
733 r->bge_flags = BGE_RXBDFLAG_END;
734 r->bge_len = m_new->m_len;
735 r->bge_idx = i;
736
737 return(0);
738}
739
740/*
741 * Initialize a jumbo receive ring descriptor. This allocates
742 * a jumbo buffer from the pool managed internally by the driver.
743 */
744static int
745bge_newbuf_jumbo(sc, i, m)
746 struct bge_softc *sc;
747 int i;
748 struct mbuf *m;
749{
750 struct mbuf *m_new = NULL;
751 struct bge_rx_bd *r;
752
753 if (m == NULL) {
754 caddr_t *buf = NULL;
755
756 /* Allocate the mbuf. */
757 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
758 if (m_new == NULL) {
759 return(ENOBUFS);
760 }
761
762 /* Allocate the jumbo buffer */
763 buf = bge_jalloc(sc);
764 if (buf == NULL) {
765 m_freem(m_new);
766 printf("bge%d: jumbo allocation failed "
767 "-- packet dropped!\n", sc->bge_unit);
768 return(ENOBUFS);
769 }
770
771 /* Attach the buffer to the mbuf. */
772 m_new->m_data = (void *) buf;
773 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN;
774 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree,
775 (struct bge_softc *)sc, 0, EXT_NET_DRV);
776 } else {
777 m_new = m;
778 m_new->m_data = m_new->m_ext.ext_buf;
779 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
780 }
781
782 if (!sc->bge_rx_alignment_bug)
783 m_adj(m_new, ETHER_ALIGN);
784 /* Set up the descriptor. */
785 r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
786 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
787 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t));
788 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
789 r->bge_len = m_new->m_len;
790 r->bge_idx = i;
791
792 return(0);
793}
794
795/*
796 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
797 * that's 1MB or memory, which is a lot. For now, we fill only the first
798 * 256 ring entries and hope that our CPU is fast enough to keep up with
799 * the NIC.
800 */
801static int
802bge_init_rx_ring_std(sc)
803 struct bge_softc *sc;
804{
805 int i;
806
807 for (i = 0; i < BGE_SSLOTS; i++) {
808 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
809 return(ENOBUFS);
810 };
811
812 sc->bge_std = i - 1;
813 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
814
815 return(0);
816}
817
818static void
819bge_free_rx_ring_std(sc)
820 struct bge_softc *sc;
821{
822 int i;
823
824 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
825 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
826 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
827 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
828 }
829 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i],
830 sizeof(struct bge_rx_bd));
831 }
832
833 return;
834}
835
836static int
837bge_init_rx_ring_jumbo(sc)
838 struct bge_softc *sc;
839{
840 int i;
841 struct bge_rcb *rcb;
842 struct bge_rcb_opaque *rcbo;
843
844 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
845 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
846 return(ENOBUFS);
847 };
848
849 sc->bge_jumbo = i - 1;
850
851 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
852 rcbo = (struct bge_rcb_opaque *)rcb;
853 rcb->bge_flags = 0;
854 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
855
856 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
857
858 return(0);
859}
860
861static void
862bge_free_rx_ring_jumbo(sc)
863 struct bge_softc *sc;
864{
865 int i;
866
867 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
868 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
869 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
870 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
871 }
872 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i],
873 sizeof(struct bge_rx_bd));
874 }
875
876 return;
877}
878
879static void
880bge_free_tx_ring(sc)
881 struct bge_softc *sc;
882{
883 int i;
884
885 if (sc->bge_rdata->bge_tx_ring == NULL)
886 return;
887
888 for (i = 0; i < BGE_TX_RING_CNT; i++) {
889 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
890 m_freem(sc->bge_cdata.bge_tx_chain[i]);
891 sc->bge_cdata.bge_tx_chain[i] = NULL;
892 }
893 bzero((char *)&sc->bge_rdata->bge_tx_ring[i],
894 sizeof(struct bge_tx_bd));
895 }
896
897 return;
898}
899
900static int
901bge_init_tx_ring(sc)
902 struct bge_softc *sc;
903{
904 sc->bge_txcnt = 0;
905 sc->bge_tx_saved_considx = 0;
906 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
907 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
908
909 return(0);
910}
911
912#define BGE_POLY 0xEDB88320
913
914static u_int32_t
915bge_crc(addr)
916 caddr_t addr;
917{
918 u_int32_t idx, bit, data, crc;
919
920 /* Compute CRC for the address value. */
921 crc = 0xFFFFFFFF; /* initial value */
922
923 for (idx = 0; idx < 6; idx++) {
924 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
925 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0);
926 }
927
928 return(crc & 0x7F);
929}
930
931static void
932bge_setmulti(sc)
933 struct bge_softc *sc;
934{
935 struct ifnet *ifp;
936 struct ifmultiaddr *ifma;
937 u_int32_t hashes[4] = { 0, 0, 0, 0 };
938 int h, i;
939
940 ifp = &sc->arpcom.ac_if;
941
942 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
943 for (i = 0; i < 4; i++)
944 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
945 return;
946 }
947
948 /* First, zot all the existing filters. */
949 for (i = 0; i < 4; i++)
950 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
951
952 /* Now program new ones. */
953 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
954 if (ifma->ifma_addr->sa_family != AF_LINK)
955 continue;
956 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
957 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
958 }
959
960 for (i = 0; i < 4; i++)
961 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
962
963 return;
964}
965
966/*
967 * Do endian, PCI and DMA initialization. Also check the on-board ROM
968 * self-test results.
969 */
970static int
971bge_chipinit(sc)
972 struct bge_softc *sc;
973{
974 u_int32_t cachesize;
975 int i;
976
977 /* Set endianness before we access any non-PCI registers. */
978#if BYTE_ORDER == BIG_ENDIAN
979 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
980 BGE_BIGENDIAN_INIT, 4);
981#else
982 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
983 BGE_LITTLEENDIAN_INIT, 4);
984#endif
985
986 /*
987 * Check the 'ROM failed' bit on the RX CPU to see if
988 * self-tests passed.
989 */
990 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
991 printf("bge%d: RX CPU self-diagnostics failed!\n",
992 sc->bge_unit);
993 return(ENODEV);
994 }
995
996 /* Clear the MAC control register */
997 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
998
999 /*
1000 * Clear the MAC statistics block in the NIC's
1001 * internal memory.
1002 */
1003 for (i = BGE_STATS_BLOCK;
1004 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
1005 BGE_MEMWIN_WRITE(sc, i, 0);
1006
1007 for (i = BGE_STATUS_BLOCK;
1008 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
1009 BGE_MEMWIN_WRITE(sc, i, 0);
1010
1011 /* Set up the PCI DMA control register. */
1012 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1013 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F, 4);
1014
1015 /*
1016 * Set up general mode register.
1017 */
1018 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1019 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1020 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1021 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM|
1022 BGE_MODECTL_RX_NO_PHDR_CSUM);
1023
1024 /* Get cache line size. */
1025 cachesize = pci_read_config(sc->bge_dev, BGE_PCI_CACHESZ, 1);
1026
1027 /*
1028 * Avoid violating PCI spec on certain chip revs.
1029 */
1030 if (pci_read_config(sc->bge_dev, BGE_PCI_CMD, 4) & PCIM_CMD_MWIEN) {
1031 switch(cachesize) {
1032 case 1:
1033 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1034 BGE_PCI_WRITE_BNDRY_16BYTES, 4);
1035 break;
1036 case 2:
1037 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1038 BGE_PCI_WRITE_BNDRY_32BYTES, 4);
1039 break;
1040 case 4:
1041 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1042 BGE_PCI_WRITE_BNDRY_64BYTES, 4);
1043 break;
1044 case 8:
1045 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1046 BGE_PCI_WRITE_BNDRY_128BYTES, 4);
1047 break;
1048 case 16:
1049 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1050 BGE_PCI_WRITE_BNDRY_256BYTES, 4);
1051 break;
1052 case 32:
1053 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1054 BGE_PCI_WRITE_BNDRY_512BYTES, 4);
1055 break;
1056 case 64:
1057 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1058 BGE_PCI_WRITE_BNDRY_1024BYTES, 4);
1059 break;
1060 default:
1061 /* Disable PCI memory write and invalidate. */
1062 if (bootverbose)
1063 printf("bge%d: cache line size %d not "
1064 "supported; disabling PCI MWI\n",
1065 sc->bge_unit, cachesize);
1066 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1067 PCIM_CMD_MWIEN, 4);
1068 break;
1069 }
1070 }
1071
1072#ifdef __brokenalpha__
1073 /*
1074 * Must insure that we do not cross an 8K (bytes) boundary
1075 * for DMA reads. Our highest limit is 1K bytes. This is a
1076 * restriction on some ALPHA platforms with early revision
1077 * 21174 PCI chipsets, such as the AlphaPC 164lx
1078 */
1079 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4);
1080#endif
1081
1082 /* Set the timer prescaler (always 66Mhz) */
1083 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1084
1085 return(0);
1086}
1087
1088static int
1089bge_blockinit(sc)
1090 struct bge_softc *sc;
1091{
1092 struct bge_rcb *rcb;
1093 struct bge_rcb_opaque *rcbo;
1094 int i;
1095
1096 /*
1097 * Initialize the memory window pointer register so that
1098 * we can access the first 32K of internal NIC RAM. This will
1099 * allow us to set up the TX send ring RCBs and the RX return
1100 * ring RCBs, plus other things which live in NIC memory.
1101 */
1102 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1103
1104 /* Configure mbuf memory pool */
1105 if (sc->bge_extram) {
1106 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM);
1107 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1108 } else {
1109 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1110 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1111 }
1112
1113 /* Configure DMA resource pool */
1114 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS);
1115 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1116
1117 /* Configure mbuf pool watermarks */
1118 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24);
1119 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24);
1120 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48);
1121
1122 /* Configure DMA resource watermarks */
1123 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1124 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1125
1126 /* Enable buffer manager */
1127 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1128 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1129
1130 /* Poll for buffer manager start indication */
1131 for (i = 0; i < BGE_TIMEOUT; i++) {
1132 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1133 break;
1134 DELAY(10);
1135 }
1136
1137 if (i == BGE_TIMEOUT) {
1138 printf("bge%d: buffer manager failed to start\n",
1139 sc->bge_unit);
1140 return(ENXIO);
1141 }
1142
1143 /* Enable flow-through queues */
1144 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1145 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1146
1147 /* Wait until queue initialization is complete */
1148 for (i = 0; i < BGE_TIMEOUT; i++) {
1149 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1150 break;
1151 DELAY(10);
1152 }
1153
1154 if (i == BGE_TIMEOUT) {
1155 printf("bge%d: flow-through queue init failed\n",
1156 sc->bge_unit);
1157 return(ENXIO);
1158 }
1159
1160 /* Initialize the standard RX ring control block */
1161 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1162 BGE_HOSTADDR(rcb->bge_hostaddr) =
1163 vtophys(&sc->bge_rdata->bge_rx_std_ring);
1164 rcb->bge_max_len = BGE_MAX_FRAMELEN;
1165 if (sc->bge_extram)
1166 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1167 else
1168 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1169 rcb->bge_flags = 0;
1170 rcbo = (struct bge_rcb_opaque *)rcb;
1171 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0);
1172 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1);
1173 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
1174 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3);
1175
1176 /*
1177 * Initialize the jumbo RX ring control block
1178 * We set the 'ring disabled' bit in the flags
1179 * field until we're actually ready to start
1180 * using this ring (i.e. once we set the MTU
1181 * high enough to require it).
1182 */
1183 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1184 BGE_HOSTADDR(rcb->bge_hostaddr) =
1185 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring);
1186 rcb->bge_max_len = BGE_MAX_FRAMELEN;
1187 if (sc->bge_extram)
1188 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1189 else
1190 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1191 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
1192
1193 rcbo = (struct bge_rcb_opaque *)rcb;
1194 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0);
1195 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1);
1196 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
1197 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3);
1198
1199 /* Set up dummy disabled mini ring RCB */
1200 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1201 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
1202 rcbo = (struct bge_rcb_opaque *)rcb;
1203 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
1204
1205 /*
1206 * Set the BD ring replentish thresholds. The recommended
1207 * values are 1/8th the number of descriptors allocated to
1208 * each ring.
1209 */
1210 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1211 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1212
1213 /*
1214 * Disable all unused send rings by setting the 'ring disabled'
1215 * bit in the flags field of all the TX send ring control blocks.
1216 * These are located in NIC memory.
1217 */
1218 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1219 BGE_SEND_RING_RCB);
1220 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1221 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
1222 rcb->bge_max_len = 0;
1223 rcb->bge_nicaddr = 0;
1224 rcb++;
1225 }
1226
1227 /* Configure TX RCB 0 (we use only the first ring) */
1228 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1229 BGE_SEND_RING_RCB);
1230 rcb->bge_hostaddr.bge_addr_hi = 0;
1231 BGE_HOSTADDR(rcb->bge_hostaddr) =
1232 vtophys(&sc->bge_rdata->bge_tx_ring);
1233 rcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1234 rcb->bge_max_len = BGE_TX_RING_CNT;
1235 rcb->bge_flags = 0;
1236
1237 /* Disable all unused RX return rings */
1238 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1239 BGE_RX_RETURN_RING_RCB);
1240 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1241 rcb->bge_hostaddr.bge_addr_hi = 0;
1242 rcb->bge_hostaddr.bge_addr_lo = 0;
1243 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
1244 rcb->bge_max_len = BGE_RETURN_RING_CNT;
1245 rcb->bge_nicaddr = 0;
1246 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1247 (i * (sizeof(u_int64_t))), 0);
1248 rcb++;
1249 }
1250
1251 /* Initialize RX ring indexes */
1252 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1253 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1254 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1255
1256 /*
1257 * Set up RX return ring 0
1258 * Note that the NIC address for RX return rings is 0x00000000.
1259 * The return rings live entirely within the host, so the
1260 * nicaddr field in the RCB isn't used.
1261 */
1262 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1263 BGE_RX_RETURN_RING_RCB);
1264 rcb->bge_hostaddr.bge_addr_hi = 0;
1265 BGE_HOSTADDR(rcb->bge_hostaddr) =
1266 vtophys(&sc->bge_rdata->bge_rx_return_ring);
1267 rcb->bge_nicaddr = 0x00000000;
1268 rcb->bge_max_len = BGE_RETURN_RING_CNT;
1269 rcb->bge_flags = 0;
1270
1271 /* Set random backoff seed for TX */
1272 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1273 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1274 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1275 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1276 BGE_TX_BACKOFF_SEED_MASK);
1277
1278 /* Set inter-packet gap */
1279 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1280
1281 /*
1282 * Specify which ring to use for packets that don't match
1283 * any RX rules.
1284 */
1285 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1286
1287 /*
1288 * Configure number of RX lists. One interrupt distribution
1289 * list, sixteen active lists, one bad frames class.
1290 */
1291 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1292
1293 /* Inialize RX list placement stats mask. */
1294 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1295 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1296
1297 /* Disable host coalescing until we get it set up */
1298 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1299
1300 /* Poll to make sure it's shut down. */
1301 for (i = 0; i < BGE_TIMEOUT; i++) {
1302 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1303 break;
1304 DELAY(10);
1305 }
1306
1307 if (i == BGE_TIMEOUT) {
1308 printf("bge%d: host coalescing engine failed to idle\n",
1309 sc->bge_unit);
1310 return(ENXIO);
1311 }
1312
1313 /* Set up host coalescing defaults */
1314 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1315 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1316 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1317 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1318 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1319 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1320 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1321 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1322 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1323
1324 /* Set up address of statistics block */
1325 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1326 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1327 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1328 vtophys(&sc->bge_rdata->bge_info.bge_stats));
1329
1330 /* Set up address of status block */
1331 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1332 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1333 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1334 vtophys(&sc->bge_rdata->bge_status_block));
1335 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1336 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1337
1338 /* Turn on host coalescing state machine */
1339 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1340
1341 /* Turn on RX BD completion state machine and enable attentions */
1342 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1343 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1344
1345 /* Turn on RX list placement state machine */
1346 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1347
1348 /* Turn on RX list selector state machine. */
1349 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1350
1351 /* Turn on DMA, clear stats */
1352 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1353 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1354 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1355 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1356 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1357
1358 /* Set misc. local control, enable interrupts on attentions */
1359 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1360
1361#ifdef notdef
1362 /* Assert GPIO pins for PHY reset */
1363 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1364 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1365 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1366 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1367#endif
1368
1369 /* Turn on DMA completion state machine */
1370 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1371
1372 /* Turn on write DMA state machine */
1373 CSR_WRITE_4(sc, BGE_WDMA_MODE,
1374 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1375
1376 /* Turn on read DMA state machine */
1377 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1378 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1379
1380 /* Turn on RX data completion state machine */
1381 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1382
1383 /* Turn on RX BD initiator state machine */
1384 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1385
1386 /* Turn on RX data and RX BD initiator state machine */
1387 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1388
1389 /* Turn on Mbuf cluster free state machine */
1390 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1391
1392 /* Turn on send BD completion state machine */
1393 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1394
1395 /* Turn on send data completion state machine */
1396 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1397
1398 /* Turn on send data initiator state machine */
1399 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1400
1401 /* Turn on send BD initiator state machine */
1402 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1403
1404 /* Turn on send BD selector state machine */
1405 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1406
1407 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1408 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1409 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1410
1411 /* init LED register */
1412 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000);
1413
1414 /* ack/clear link change events */
1415 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1416 BGE_MACSTAT_CFG_CHANGED);
1417 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1418
1419 /* Enable PHY auto polling (for MII/GMII only) */
1420 if (sc->bge_tbi) {
1421 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1422 } else {
1423 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1424 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1425 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1426 BGE_EVTENB_MI_INTERRUPT);
1427 }
1428
1429 /* Enable link state change attentions. */
1430 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1431
1432 return(0);
1433}
1434
1435/*
1436 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1437 * against our list and return its name if we find a match. Note
1438 * that since the Broadcom controller contains VPD support, we
1439 * can get the device name string from the controller itself instead
1440 * of the compiled-in string. This is a little slow, but it guarantees
1441 * we'll always announce the right product name.
1442 */
1443static int
1444bge_probe(dev)
1445 device_t dev;
1446{
1447 struct bge_type *t;
1448 struct bge_softc *sc;
1449
1450 t = bge_devs;
1451
1452 sc = device_get_softc(dev);
1453 bzero(sc, sizeof(struct bge_softc));
1454 sc->bge_unit = device_get_unit(dev);
1455 sc->bge_dev = dev;
1456
1457 while(t->bge_name != NULL) {
1458 if ((pci_get_vendor(dev) == t->bge_vid) &&
1459 (pci_get_device(dev) == t->bge_did)) {
1460#ifdef notdef
1461 bge_vpd_read(sc);
1462 device_set_desc(dev, sc->bge_vpd_prodname);
1463#endif
1464 device_set_desc(dev, t->bge_name);
1465 return(0);
1466 }
1467 t++;
1468 }
1469
1470 return(ENXIO);
1471}
1472
1473static int
1474bge_attach(dev)
1475 device_t dev;
1476{
1477 int s;
1478 u_int32_t command;
1479 struct ifnet *ifp;
1480 struct bge_softc *sc;
1481 u_int32_t hwcfg = 0;
1482 int unit, error = 0, rid;
1483
1484 s = splimp();
1485
1486 sc = device_get_softc(dev);
1487 unit = device_get_unit(dev);
1488 sc->bge_dev = dev;
1489 sc->bge_unit = unit;
1490
1491 /*
1492 * Map control/status registers.
1493 */
1494 pci_enable_busmaster(dev);
1495 pci_enable_io(dev, SYS_RES_MEMORY);
1496 command = pci_read_config(dev, PCIR_COMMAND, 4);
1497
1498 if (!(command & PCIM_CMD_MEMEN)) {
1499 printf("bge%d: failed to enable memory mapping!\n", unit);
1500 error = ENXIO;
1501 goto fail;
1502 }
1503
1504 rid = BGE_PCI_BAR0;
1505 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1506 0, ~0, 1, RF_ACTIVE);
1507
1508 if (sc->bge_res == NULL) {
1509 printf ("bge%d: couldn't map memory\n", unit);
1510 error = ENXIO;
1511 goto fail;
1512 }
1513
1514 sc->bge_btag = rman_get_bustag(sc->bge_res);
1515 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1516 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1517
1518 /*
1519 * XXX FIXME: rman_get_virtual() on the alpha is currently
1520 * broken and returns a physical address instead of a kernel
1521 * virtual address. Consequently, we need to do a little
1522 * extra mangling of the vhandle on the alpha. This should
1523 * eventually be fixed! The whole idea here is to get rid
1524 * of platform dependencies.
1525 */
1526#ifdef __alpha__
1527 if (pci_cvt_to_bwx(sc->bge_vhandle))
1528 sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle);
1529 else
1530 sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle);
1531 sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle);
1532#endif
1533
1534 /* Allocate interrupt */
1535 rid = 0;
1536
1537 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1538 RF_SHAREABLE | RF_ACTIVE);
1539
1540 if (sc->bge_irq == NULL) {
1541 printf("bge%d: couldn't map interrupt\n", unit);
1542 error = ENXIO;
1543 goto fail;
1544 }
1545
1546 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET,
1547 bge_intr, sc, &sc->bge_intrhand);
1548
1549 if (error) {
1550 bge_release_resources(sc);
1551 printf("bge%d: couldn't set up irq\n", unit);
1552 goto fail;
1553 }
1554
1555 sc->bge_unit = unit;
1556
1557 /* Try to reset the chip. */
1558 bge_reset(sc);
1559
1560 if (bge_chipinit(sc)) {
1561 printf("bge%d: chip initialization failed\n", sc->bge_unit);
1562 bge_release_resources(sc);
1563 error = ENXIO;
1564 goto fail;
1565 }
1566
1567 /*
1568 * Get station address from the EEPROM.
1569 */
1570 if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1571 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1572 printf("bge%d: failed to read station address\n", unit);
1573 bge_release_resources(sc);
1574 error = ENXIO;
1575 goto fail;
1576 }
1577
1578 /*
1579 * A Broadcom chip was detected. Inform the world.
1580 */
1581 printf("bge%d: Ethernet address: %6D\n", unit,
1582 sc->arpcom.ac_enaddr, ":");
1583
1584 /* Allocate the general information block and ring buffers. */
1585 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1586 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1587
1588 if (sc->bge_rdata == NULL) {
1589 bge_release_resources(sc);
1590 error = ENXIO;
1591 printf("bge%d: no memory for list buffers!\n", sc->bge_unit);
1592 goto fail;
1593 }
1594
1595 bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1596
1597 /* Try to allocate memory for jumbo buffers. */
1598 if (bge_alloc_jumbo_mem(sc)) {
1599 printf("bge%d: jumbo buffer allocation "
1600 "failed\n", sc->bge_unit);
1601 bge_release_resources(sc);
1602 error = ENXIO;
1603 goto fail;
1604 }
1605
1606 /* Set default tuneable values. */
1607 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1608 sc->bge_rx_coal_ticks = 150;
1609 sc->bge_tx_coal_ticks = 150;
1610 sc->bge_rx_max_coal_bds = 64;
1611 sc->bge_tx_max_coal_bds = 128;
1612
1613 /* Set up ifnet structure */
1614 ifp = &sc->arpcom.ac_if;
1615 ifp->if_softc = sc;
1616 ifp->if_unit = sc->bge_unit;
1617 ifp->if_name = "bge";
1618 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1619 ifp->if_ioctl = bge_ioctl;
1620 ifp->if_output = ether_output;
1621 ifp->if_start = bge_start;
1622 ifp->if_watchdog = bge_watchdog;
1623 ifp->if_init = bge_init;
1624 ifp->if_mtu = ETHERMTU;
1625 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1;
1626 ifp->if_hwassist = BGE_CSUM_FEATURES;
1627 ifp->if_capabilities = IFCAP_HWCSUM;
1628 ifp->if_capenable = ifp->if_capabilities;
1629
1630 /* Save ASIC rev. */
1631
1632 sc->bge_asicrev =
1633 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1634 BGE_PCIMISCCTL_ASICREV;
1635
1636 /* Pretend all 5700s are the same */
1637 if ((sc->bge_asicrev & 0xFF000000) == BGE_ASICREV_BCM5700)
1638 sc->bge_asicrev = BGE_ASICREV_BCM5700;
1639
1640 /*
1641 * Figure out what sort of media we have by checking the
1642 * hardware config word in the EEPROM. Note: on some BCM5700
1643 * cards, this value appears to be unset. If that's the
1644 * case, we have to rely on identifying the NIC by its PCI
1645 * subsystem ID, as we do below for the SysKonnect SK-9D41.
1646 */
1647 bge_read_eeprom(sc, (caddr_t)&hwcfg,
1648 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
1649 if ((ntohl(hwcfg) & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1650 sc->bge_tbi = 1;
1651
1652 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1653 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
1654 sc->bge_tbi = 1;
1655
1656 if (sc->bge_tbi) {
1657 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1658 bge_ifmedia_upd, bge_ifmedia_sts);
1659 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1660 ifmedia_add(&sc->bge_ifmedia,
1661 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1662 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1663 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1664 } else {
1665 /*
1666 * Do transceiver setup.
1667 */
1668 if (mii_phy_probe(dev, &sc->bge_miibus,
1669 bge_ifmedia_upd, bge_ifmedia_sts)) {
1670 printf("bge%d: MII without any PHY!\n", sc->bge_unit);
1671 bge_release_resources(sc);
1672 bge_free_jumbo_mem(sc);
1673 error = ENXIO;
1674 goto fail;
1675 }
1676 }
1677
1678 /*
1679 * When using the BCM5701 in PCI-X mode, data corruption has
1680 * been observed in the first few bytes of some received packets.
1681 * Aligning the packet buffer in memory eliminates the corruption.
1682 * Unfortunately, this misaligns the packet payloads. On platforms
1683 * which do not support unaligned accesses, we will realign the
1684 * payloads by copying the received packets.
1685 */
1686 switch (sc->bge_asicrev) {
1687 case BGE_ASICREV_BCM5701_A0:
1688 case BGE_ASICREV_BCM5701_B0:
1689 case BGE_ASICREV_BCM5701_B2:
1690 case BGE_ASICREV_BCM5701_B5:
1691 /* If in PCI-X mode, work around the alignment bug. */
1692 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
1693 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
1694 BGE_PCISTATE_PCI_BUSSPEED)
1695 sc->bge_rx_alignment_bug = 1;
1696 break;
1697 }
1698
1699 /*
1700 * Call MI attach routine.
1701 */
1702 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1703 callout_handle_init(&sc->bge_stat_ch);
1704
1705fail:
1706 splx(s);
1707
1708 return(error);
1709}
1710
1711static int
1712bge_detach(dev)
1713 device_t dev;
1714{
1715 struct bge_softc *sc;
1716 struct ifnet *ifp;
1717 int s;
1718
1719 s = splimp();
1720
1721 sc = device_get_softc(dev);
1722 ifp = &sc->arpcom.ac_if;
1723
1724 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1725 bge_stop(sc);
1726 bge_reset(sc);
1727
1728 if (sc->bge_tbi) {
1729 ifmedia_removeall(&sc->bge_ifmedia);
1730 } else {
1731 bus_generic_detach(dev);
1732 device_delete_child(dev, sc->bge_miibus);
1733 }
1734
1735 bge_release_resources(sc);
1736 bge_free_jumbo_mem(sc);
1737
1738 splx(s);
1739
1740 return(0);
1741}
1742
1743static void
1744bge_release_resources(sc)
1745 struct bge_softc *sc;
1746{
1747 device_t dev;
1748
1749 dev = sc->bge_dev;
1750
1751 if (sc->bge_vpd_prodname != NULL)
1752 free(sc->bge_vpd_prodname, M_DEVBUF);
1753
1754 if (sc->bge_vpd_readonly != NULL)
1755 free(sc->bge_vpd_readonly, M_DEVBUF);
1756
1757 if (sc->bge_intrhand != NULL)
1758 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1759
1760 if (sc->bge_irq != NULL)
1761 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1762
1763 if (sc->bge_res != NULL)
1764 bus_release_resource(dev, SYS_RES_MEMORY,
1765 BGE_PCI_BAR0, sc->bge_res);
1766
1767 if (sc->bge_rdata != NULL)
1768 contigfree(sc->bge_rdata,
1769 sizeof(struct bge_ring_data), M_DEVBUF);
1770
1771 return;
1772}
1773
1774static void
1775bge_reset(sc)
1776 struct bge_softc *sc;
1777{
1778 device_t dev;
1779 u_int32_t cachesize, command, pcistate;
1780 int i, val = 0;
1781
1782 dev = sc->bge_dev;
1783
1784 /* Save some important PCI state. */
1785 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1786 command = pci_read_config(dev, BGE_PCI_CMD, 4);
1787 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1788
1789 pci_write_config(dev, BGE_PCI_MISC_CTL,
1790 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1791 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1792
1793 /* Issue global reset */
1794 bge_writereg_ind(sc, BGE_MISC_CFG,
1795 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1));
1796
1797 DELAY(1000);
1798
1799 /* Reset some of the PCI state that got zapped by reset */
1800 pci_write_config(dev, BGE_PCI_MISC_CTL,
1801 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1802 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1803 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
1804 pci_write_config(dev, BGE_PCI_CMD, command, 4);
1805 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
1806
1807 /*
1808 * Prevent PXE restart: write a magic number to the
1809 * general communications memory at 0xB50.
1810 */
1811 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1812 /*
1813 * Poll the value location we just wrote until
1814 * we see the 1's complement of the magic number.
1815 * This indicates that the firmware initialization
1816 * is complete.
1817 */
1818 for (i = 0; i < BGE_TIMEOUT; i++) {
1819 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
1820 if (val == ~BGE_MAGIC_NUMBER)
1821 break;
1822 DELAY(10);
1823 }
1824
1825 if (i == BGE_TIMEOUT) {
1826 printf("bge%d: firmware handshake timed out\n", sc->bge_unit);
1827 return;
1828 }
1829
1830 /*
1831 * XXX Wait for the value of the PCISTATE register to
1832 * return to its original pre-reset state. This is a
1833 * fairly good indicator of reset completion. If we don't
1834 * wait for the reset to fully complete, trying to read
1835 * from the device's non-PCI registers may yield garbage
1836 * results.
1837 */
1838 for (i = 0; i < BGE_TIMEOUT; i++) {
1839 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
1840 break;
1841 DELAY(10);
1842 }
1843
1844 /* Enable memory arbiter. */
1845 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
1846
1847 /* Fix up byte swapping */
1848 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
1849 BGE_MODECTL_BYTESWAP_DATA);
1850
1851 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1852
1853 DELAY(10000);
1854
1855 return;
1856}
1857
1858/*
1859 * Frame reception handling. This is called if there's a frame
1860 * on the receive return list.
1861 *
1862 * Note: we have to be able to handle two possibilities here:
1863 * 1) the frame is from the jumbo recieve ring
1864 * 2) the frame is from the standard receive ring
1865 */
1866
1867static void
1868bge_rxeof(sc)
1869 struct bge_softc *sc;
1870{
1871 struct ifnet *ifp;
1872 int stdcnt = 0, jumbocnt = 0;
1873
1874 ifp = &sc->arpcom.ac_if;
1875
1876 while(sc->bge_rx_saved_considx !=
1877 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
1878 struct bge_rx_bd *cur_rx;
1879 u_int32_t rxidx;
1880 struct ether_header *eh;
1881 struct mbuf *m = NULL;
1882 u_int16_t vlan_tag = 0;
1883 int have_tag = 0;
1884
1885 cur_rx =
1886 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
1887
1888 rxidx = cur_rx->bge_idx;
1889 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT);
1890
1891 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
1892 have_tag = 1;
1893 vlan_tag = cur_rx->bge_vlan_tag;
1894 }
1895
1896 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
1897 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1898 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
1899 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
1900 jumbocnt++;
1901 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1902 ifp->if_ierrors++;
1903 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1904 continue;
1905 }
1906 if (bge_newbuf_jumbo(sc,
1907 sc->bge_jumbo, NULL) == ENOBUFS) {
1908 ifp->if_ierrors++;
1909 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1910 continue;
1911 }
1912 } else {
1913 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1914 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
1915 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
1916 stdcnt++;
1917 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1918 ifp->if_ierrors++;
1919 bge_newbuf_std(sc, sc->bge_std, m);
1920 continue;
1921 }
1922 if (bge_newbuf_std(sc, sc->bge_std,
1923 NULL) == ENOBUFS) {
1924 ifp->if_ierrors++;
1925 bge_newbuf_std(sc, sc->bge_std, m);
1926 continue;
1927 }
1928 }
1929
1930 ifp->if_ipackets++;
1931#ifndef __i386__
1932 /*
1933 * The i386 allows unaligned accesses, but for other
1934 * platforms we must make sure the payload is aligned.
1935 */
1936 if (sc->bge_rx_alignment_bug) {
1937 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
1938 cur_rx->bge_len);
1939 m->m_data += ETHER_ALIGN;
1940 }
1941#endif
1942 eh = mtod(m, struct ether_header *);
1943 m->m_pkthdr.len = m->m_len = cur_rx->bge_len;
1944 m->m_pkthdr.rcvif = ifp;
1945
1946 /* Remove header from mbuf and pass it on. */
1947 m_adj(m, sizeof(struct ether_header));
1948
1949#if 0 /* currently broken for some packets, possibly related to TCP options */
1950 if (ifp->if_hwassist) {
1951 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1952 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
1953 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1954 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
1955 m->m_pkthdr.csum_data =
1956 cur_rx->bge_tcp_udp_csum;
1957 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1958 }
1959 }
1960#endif
1961
1962 /*
1963 * If we received a packet with a vlan tag, pass it
1964 * to vlan_input() instead of ether_input().
1965 */
1966 if (have_tag) {
1967 VLAN_INPUT_TAG(eh, m, vlan_tag);
1968 have_tag = vlan_tag = 0;
1969 continue;
1970 }
1971
1972 ether_input(ifp, eh, m);
1973 }
1974
1975 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
1976 if (stdcnt)
1977 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1978 if (jumbocnt)
1979 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1980
1981 return;
1982}
1983
1984static void
1985bge_txeof(sc)
1986 struct bge_softc *sc;
1987{
1988 struct bge_tx_bd *cur_tx = NULL;
1989 struct ifnet *ifp;
1990
1991 ifp = &sc->arpcom.ac_if;
1992
1993 /*
1994 * Go through our tx ring and free mbufs for those
1995 * frames that have been sent.
1996 */
1997 while (sc->bge_tx_saved_considx !=
1998 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
1999 u_int32_t idx = 0;
2000
2001 idx = sc->bge_tx_saved_considx;
2002 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
2003 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2004 ifp->if_opackets++;
2005 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2006 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2007 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2008 }
2009 sc->bge_txcnt--;
2010 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2011 ifp->if_timer = 0;
2012 }
2013
2014 if (cur_tx != NULL)
2015 ifp->if_flags &= ~IFF_OACTIVE;
2016
2017 return;
2018}
2019
2020static void
2021bge_intr(xsc)
2022 void *xsc;
2023{
2024 struct bge_softc *sc;
2025 struct ifnet *ifp;
2026
2027 sc = xsc;
2028 ifp = &sc->arpcom.ac_if;
2029
2030#ifdef notdef
2031 /* Avoid this for now -- checking this register is expensive. */
2032 /* Make sure this is really our interrupt. */
2033 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
2034 return;
2035#endif
2036 /* Ack interrupt and stop others from occuring. */
2037 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2038
2039 /*
2040 * Process link state changes.
2041 * Grrr. The link status word in the status block does
2042 * not work correctly on the BCM5700 rev AX and BX chips,
2043 * according to all avaibable information. Hence, we have
2044 * to enable MII interrupts in order to properly obtain
2045 * async link changes. Unfortunately, this also means that
2046 * we have to read the MAC status register to detect link
2047 * changes, thereby adding an additional register access to
2048 * the interrupt handler.
2049 */
2050
2051 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2052 u_int32_t status;
2053
2054 status = CSR_READ_4(sc, BGE_MAC_STS);
2055 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2056 sc->bge_link = 0;
2057 untimeout(bge_tick, sc, sc->bge_stat_ch);
2058 bge_tick(sc);
2059 /* Clear the interrupt */
2060 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2061 BGE_EVTENB_MI_INTERRUPT);
2062 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2063 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2064 BRGPHY_INTRS);
2065 }
2066 } else {
2067 if (sc->bge_rdata->bge_status_block.bge_status &
2068 BGE_STATFLAG_LINKSTATE_CHANGED) {
2069 sc->bge_link = 0;
2070 untimeout(bge_tick, sc, sc->bge_stat_ch);
2071 bge_tick(sc);
2072 /* Clear the interrupt */
2073 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2074 BGE_MACSTAT_CFG_CHANGED);
2075 }
2076 }
2077
2078 if (ifp->if_flags & IFF_RUNNING) {
2079 /* Check RX return ring producer/consumer */
2080 bge_rxeof(sc);
2081
2082 /* Check TX ring producer/consumer */
2083 bge_txeof(sc);
2084 }
2085
2086 bge_handle_events(sc);
2087
2088 /* Re-enable interrupts. */
2089 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2090
2091 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
2092 bge_start(ifp);
2093
2094 return;
2095}
2096
2097static void
2098bge_tick(xsc)
2099 void *xsc;
2100{
2101 struct bge_softc *sc;
2102 struct mii_data *mii = NULL;
2103 struct ifmedia *ifm = NULL;
2104 struct ifnet *ifp;
2105 int s;
2106
2107 sc = xsc;
2108 ifp = &sc->arpcom.ac_if;
2109
2110 s = splimp();
2111
2112 bge_stats_update(sc);
2113 sc->bge_stat_ch = timeout(bge_tick, sc, hz);
2114 if (sc->bge_link) {
2115 splx(s);
2116 return;
2117 }
2118
2119 if (sc->bge_tbi) {
2120 ifm = &sc->bge_ifmedia;
2121 if (CSR_READ_4(sc, BGE_MAC_STS) &
2122 BGE_MACSTAT_TBI_PCS_SYNCHED) {
2123 sc->bge_link++;
2124 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2125 printf("bge%d: gigabit link up\n", sc->bge_unit);
2126 if (ifp->if_snd.ifq_head != NULL)
2127 bge_start(ifp);
2128 }
2129 splx(s);
2130 return;
2131 }
2132
2133 mii = device_get_softc(sc->bge_miibus);
2134 mii_tick(mii);
2135
2136 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE &&
2137 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2138 sc->bge_link++;
2139 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
2140 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2141 printf("bge%d: gigabit link up\n",
2142 sc->bge_unit);
2143 if (ifp->if_snd.ifq_head != NULL)
2144 bge_start(ifp);
2145 }
2146
2147 splx(s);
2148
2149 return;
2150}
2151
2152static void
2153bge_stats_update(sc)
2154 struct bge_softc *sc;
2155{
2156 struct ifnet *ifp;
2157 struct bge_stats *stats;
2158
2159 ifp = &sc->arpcom.ac_if;
2160
2161 stats = (struct bge_stats *)(sc->bge_vhandle +
2162 BGE_MEMWIN_START + BGE_STATS_BLOCK);
2163
2164 ifp->if_collisions +=
2165 (stats->dot3StatsSingleCollisionFrames.bge_addr_lo +
2166 stats->dot3StatsMultipleCollisionFrames.bge_addr_lo +
2167 stats->dot3StatsExcessiveCollisions.bge_addr_lo +
2168 stats->dot3StatsLateCollisions.bge_addr_lo) -
2169 ifp->if_collisions;
2170
2171#ifdef notdef
2172 ifp->if_collisions +=
2173 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2174 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2175 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2176 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2177 ifp->if_collisions;
2178#endif
2179
2180 return;
2181}
2182
2183/*
2184 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2185 * pointers to descriptors.
2186 */
2187static int
2188bge_encap(sc, m_head, txidx)
2189 struct bge_softc *sc;
2190 struct mbuf *m_head;
2191 u_int32_t *txidx;
2192{
2193 struct bge_tx_bd *f = NULL;
2194 struct mbuf *m;
2195 u_int32_t frag, cur, cnt = 0;
2196 u_int16_t csum_flags = 0;
2197 struct ifvlan *ifv = NULL;
2198
2199 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2200 m_head->m_pkthdr.rcvif != NULL &&
2201 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2202 ifv = m_head->m_pkthdr.rcvif->if_softc;
2203
2204 m = m_head;
2205 cur = frag = *txidx;
2206
2207 if (m_head->m_pkthdr.csum_flags) {
2208 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2209 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2210 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2211 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2212 if (m_head->m_flags & M_LASTFRAG)
2213 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2214 else if (m_head->m_flags & M_FRAG)
2215 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2216 }
2217
2218 /*
2219 * Start packing the mbufs in this chain into
2220 * the fragment pointers. Stop when we run out
2221 * of fragments or hit the end of the mbuf chain.
2222 */
2223 for (m = m_head; m != NULL; m = m->m_next) {
2224 if (m->m_len != 0) {
2225 f = &sc->bge_rdata->bge_tx_ring[frag];
2226 if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2227 break;
2228 BGE_HOSTADDR(f->bge_addr) =
2229 vtophys(mtod(m, vm_offset_t));
2230 f->bge_len = m->m_len;
2231 f->bge_flags = csum_flags;
2232 if (ifv != NULL) {
2233 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2234 f->bge_vlan_tag = ifv->ifv_tag;
2235 } else {
2236 f->bge_vlan_tag = 0;
2237 }
2238 /*
2239 * Sanity check: avoid coming within 16 descriptors
2240 * of the end of the ring.
2241 */
2242 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2243 return(ENOBUFS);
2244 cur = frag;
2245 BGE_INC(frag, BGE_TX_RING_CNT);
2246 cnt++;
2247 }
2248 }
2249
2250 if (m != NULL)
2251 return(ENOBUFS);
2252
2253 if (frag == sc->bge_tx_saved_considx)
2254 return(ENOBUFS);
2255
2256 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2257 sc->bge_cdata.bge_tx_chain[cur] = m_head;
2258 sc->bge_txcnt += cnt;
2259
2260 *txidx = frag;
2261
2262 return(0);
2263}
2264
2265/*
2266 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2267 * to the mbuf data regions directly in the transmit descriptors.
2268 */
2269static void
2270bge_start(ifp)
2271 struct ifnet *ifp;
2272{
2273 struct bge_softc *sc;
2274 struct mbuf *m_head = NULL;
2275 u_int32_t prodidx = 0;
2276
2277 sc = ifp->if_softc;
2278
2279 if (!sc->bge_link && ifp->if_snd.ifq_len < 10)
2280 return;
2281
2282 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2283
2284 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2285 IF_DEQUEUE(&ifp->if_snd, m_head);
2286 if (m_head == NULL)
2287 break;
2288
2289 /*
2290 * XXX
2291 * safety overkill. If this is a fragmented packet chain
2292 * with delayed TCP/UDP checksums, then only encapsulate
2293 * it if we have enough descriptors to handle the entire
2294 * chain at once.
2295 * (paranoia -- may not actually be needed)
2296 */
2297 if (m_head->m_flags & M_FIRSTFRAG &&
2298 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2299 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2300 m_head->m_pkthdr.csum_data + 16) {
2301 IF_PREPEND(&ifp->if_snd, m_head);
2302 ifp->if_flags |= IFF_OACTIVE;
2303 break;
2304 }
2305 }
2306
2307 /*
2308 * Pack the data into the transmit ring. If we
2309 * don't have room, set the OACTIVE flag and wait
2310 * for the NIC to drain the ring.
2311 */
2312 if (bge_encap(sc, m_head, &prodidx)) {
2313 IF_PREPEND(&ifp->if_snd, m_head);
2314 ifp->if_flags |= IFF_OACTIVE;
2315 break;
2316 }
2317
2318 /*
2319 * If there's a BPF listener, bounce a copy of this frame
2320 * to him.
2321 */
2322 if (ifp->if_bpf)
2323 bpf_mtap(ifp, m_head);
2324 }
2325
2326 /* Transmit */
2327 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2328
2329 /*
2330 * Set a timeout in case the chip goes out to lunch.
2331 */
2332 ifp->if_timer = 5;
2333
2334 return;
2335}
2336
2337/*
2338 * If we have a BCM5400 or BCM5401 PHY, we need to properly
2339 * program its internal DSP. Failing to do this can result in
2340 * massive packet loss at 1Gb speeds.
2341 */
2342static void
2343bge_phy_hack(sc)
2344 struct bge_softc *sc;
2345{
2346 struct bge_bcom_hack bhack[] = {
2347 { BRGPHY_MII_AUXCTL, 0x4C20 },
2348 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
2349 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
2350 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
2351 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
2352 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
2353 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
2354 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
2355 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
2356 { BRGPHY_MII_DSP_ADDR_REG, 0x201F },
2357 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 },
2358 { 0, 0 } };
2359 u_int16_t vid, did;
2360 int i;
2361
2362 vid = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR1);
2363 did = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR2);
2364
2365 if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM &&
2366 (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 ||
2367 MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) {
2368 i = 0;
2369 while(bhack[i].reg) {
2370 bge_miibus_writereg(sc->bge_dev, 1, bhack[i].reg,
2371 bhack[i].val);
2372 i++;
2373 }
2374 }
2375
2376 return;
2377}
2378
2379static void
2380bge_init(xsc)
2381 void *xsc;
2382{
2383 struct bge_softc *sc = xsc;
2384 struct ifnet *ifp;
2385 u_int16_t *m;
2386 int s;
2387
2388 s = splimp();
2389
2390 ifp = &sc->arpcom.ac_if;
2391
2392 if (ifp->if_flags & IFF_RUNNING) {
2393 splx(s);
2394 return;
2395 }
2396
2397 /* Cancel pending I/O and flush buffers. */
2398 bge_stop(sc);
2399 bge_reset(sc);
2400 bge_chipinit(sc);
2401
2402 /*
2403 * Init the various state machines, ring
2404 * control blocks and firmware.
2405 */
2406 if (bge_blockinit(sc)) {
2407 printf("bge%d: initialization failure\n", sc->bge_unit);
2408 splx(s);
2409 return;
2410 }
2411
2412 ifp = &sc->arpcom.ac_if;
2413
2414 /* Specify MTU. */
2415 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2416 ETHER_HDR_LEN + ETHER_CRC_LEN);
2417
2418 /* Load our MAC address. */
2419 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2420 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2421 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2422
2423 /* Enable or disable promiscuous mode as needed. */
2424 if (ifp->if_flags & IFF_PROMISC) {
2425 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2426 } else {
2427 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2428 }
2429
2430 /* Program multicast filter. */
2431 bge_setmulti(sc);
2432
2433 /* Init RX ring. */
2434 bge_init_rx_ring_std(sc);
2435
2436 /* Init jumbo RX ring. */
2437 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2438 bge_init_rx_ring_jumbo(sc);
2439
2440 /* Init our RX return ring index */
2441 sc->bge_rx_saved_considx = 0;
2442
2443 /* Init TX ring. */
2444 bge_init_tx_ring(sc);
2445
2446 /* Turn on transmitter */
2447 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2448
2449 /* Turn on receiver */
2450 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2451
2452 /* Tell firmware we're alive. */
2453 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2454
2455 /* Enable host interrupts. */
2456 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2457 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2458 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2459
2460 bge_ifmedia_upd(ifp);
2461
2462 ifp->if_flags |= IFF_RUNNING;
2463 ifp->if_flags &= ~IFF_OACTIVE;
2464
2465 splx(s);
2466
2467 sc->bge_stat_ch = timeout(bge_tick, sc, hz);
2468
2469 return;
2470}
2471
2472/*
2473 * Set media options.
2474 */
2475static int
2476bge_ifmedia_upd(ifp)
2477 struct ifnet *ifp;
2478{
2479 struct bge_softc *sc;
2480 struct mii_data *mii;
2481 struct ifmedia *ifm;
2482
2483 sc = ifp->if_softc;
2484 ifm = &sc->bge_ifmedia;
2485
2486 /* If this is a 1000baseX NIC, enable the TBI port. */
2487 if (sc->bge_tbi) {
2488 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2489 return(EINVAL);
2490 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2491 case IFM_AUTO:
2492 break;
2493 case IFM_1000_SX:
2494 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2495 BGE_CLRBIT(sc, BGE_MAC_MODE,
2496 BGE_MACMODE_HALF_DUPLEX);
2497 } else {
2498 BGE_SETBIT(sc, BGE_MAC_MODE,
2499 BGE_MACMODE_HALF_DUPLEX);
2500 }
2501 break;
2502 default:
2503 return(EINVAL);
2504 }
2505 return(0);
2506 }
2507
2508 mii = device_get_softc(sc->bge_miibus);
2509 sc->bge_link = 0;
2510 if (mii->mii_instance) {
2511 struct mii_softc *miisc;
2512 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
2513 miisc = LIST_NEXT(miisc, mii_list))
2514 mii_phy_reset(miisc);
2515 }
2516 bge_phy_hack(sc);
2517 mii_mediachg(mii);
2518
2519 return(0);
2520}
2521
2522/*
2523 * Report current media status.
2524 */
2525static void
2526bge_ifmedia_sts(ifp, ifmr)
2527 struct ifnet *ifp;
2528 struct ifmediareq *ifmr;
2529{
2530 struct bge_softc *sc;
2531 struct mii_data *mii;
2532
2533 sc = ifp->if_softc;
2534
2535 if (sc->bge_tbi) {
2536 ifmr->ifm_status = IFM_AVALID;
2537 ifmr->ifm_active = IFM_ETHER;
2538 if (CSR_READ_4(sc, BGE_MAC_STS) &
2539 BGE_MACSTAT_TBI_PCS_SYNCHED)
2540 ifmr->ifm_status |= IFM_ACTIVE;
2541 ifmr->ifm_active |= IFM_1000_SX;
2542 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2543 ifmr->ifm_active |= IFM_HDX;
2544 else
2545 ifmr->ifm_active |= IFM_FDX;
2546 return;
2547 }
2548
2549 mii = device_get_softc(sc->bge_miibus);
2550 mii_pollstat(mii);
2551 ifmr->ifm_active = mii->mii_media_active;
2552 ifmr->ifm_status = mii->mii_media_status;
2553
2554 return;
2555}
2556
2557static int
2558bge_ioctl(ifp, command, data)
2559 struct ifnet *ifp;
2560 u_long command;
2561 caddr_t data;
2562{
2563 struct bge_softc *sc = ifp->if_softc;
2564 struct ifreq *ifr = (struct ifreq *) data;
2565 int s, mask, error = 0;
2566 struct mii_data *mii;
2567
2568 s = splimp();
2569
2570 switch(command) {
2571 case SIOCSIFADDR:
2572 case SIOCGIFADDR:
2573 error = ether_ioctl(ifp, command, data);
2574 break;
2575 case SIOCSIFMTU:
2576 if (ifr->ifr_mtu > BGE_JUMBO_MTU)
2577 error = EINVAL;
2578 else {
2579 ifp->if_mtu = ifr->ifr_mtu;
2580 ifp->if_flags &= ~IFF_RUNNING;
2581 bge_init(sc);
2582 }
2583 break;
2584 case SIOCSIFFLAGS:
2585 if (ifp->if_flags & IFF_UP) {
2586 /*
2587 * If only the state of the PROMISC flag changed,
2588 * then just use the 'set promisc mode' command
2589 * instead of reinitializing the entire NIC. Doing
2590 * a full re-init means reloading the firmware and
2591 * waiting for it to start up, which may take a
2592 * second or two.
2593 */
2594 if (ifp->if_flags & IFF_RUNNING &&
2595 ifp->if_flags & IFF_PROMISC &&
2596 !(sc->bge_if_flags & IFF_PROMISC)) {
2597 BGE_SETBIT(sc, BGE_RX_MODE,
2598 BGE_RXMODE_RX_PROMISC);
2599 } else if (ifp->if_flags & IFF_RUNNING &&
2600 !(ifp->if_flags & IFF_PROMISC) &&
2601 sc->bge_if_flags & IFF_PROMISC) {
2602 BGE_CLRBIT(sc, BGE_RX_MODE,
2603 BGE_RXMODE_RX_PROMISC);
2604 } else
2605 bge_init(sc);
2606 } else {
2607 if (ifp->if_flags & IFF_RUNNING) {
2608 bge_stop(sc);
2609 }
2610 }
2611 sc->bge_if_flags = ifp->if_flags;
2612 error = 0;
2613 break;
2614 case SIOCADDMULTI:
2615 case SIOCDELMULTI:
2616 if (ifp->if_flags & IFF_RUNNING) {
2617 bge_setmulti(sc);
2618 error = 0;
2619 }
2620 break;
2621 case SIOCSIFMEDIA:
2622 case SIOCGIFMEDIA:
2623 if (sc->bge_tbi) {
2624 error = ifmedia_ioctl(ifp, ifr,
2625 &sc->bge_ifmedia, command);
2626 } else {
2627 mii = device_get_softc(sc->bge_miibus);
2628 error = ifmedia_ioctl(ifp, ifr,
2629 &mii->mii_media, command);
2630 }
2631 break;
2632 case SIOCSIFCAP:
2633 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2634 if (mask & IFCAP_HWCSUM) {
2635 if (IFCAP_HWCSUM & ifp->if_capenable)
2636 ifp->if_capenable &= ~IFCAP_HWCSUM;
2637 else
2638 ifp->if_capenable |= IFCAP_HWCSUM;
2639 }
2640 error = 0;
2641 break;
2642 default:
2643 error = EINVAL;
2644 break;
2645 }
2646
2647 (void)splx(s);
2648
2649 return(error);
2650}
2651
2652static void
2653bge_watchdog(ifp)
2654 struct ifnet *ifp;
2655{
2656 struct bge_softc *sc;
2657
2658 sc = ifp->if_softc;
2659
2660 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit);
2661
2662 ifp->if_flags &= ~IFF_RUNNING;
2663 bge_init(sc);
2664
2665 ifp->if_oerrors++;
2666
2667 return;
2668}
2669
2670/*
2671 * Stop the adapter and free any mbufs allocated to the
2672 * RX and TX lists.
2673 */
2674static void
2675bge_stop(sc)
2676 struct bge_softc *sc;
2677{
2678 struct ifnet *ifp;
2679 struct ifmedia_entry *ifm;
2680 struct mii_data *mii = NULL;
2681 int mtmp, itmp;
2682
2683 ifp = &sc->arpcom.ac_if;
2684
2685 if (!sc->bge_tbi)
2686 mii = device_get_softc(sc->bge_miibus);
2687
2688 untimeout(bge_tick, sc, sc->bge_stat_ch);
2689
2690 /*
2691 * Disable all of the receiver blocks
2692 */
2693 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2694 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2695 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2696 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2697 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
2698 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2699 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
2700
2701 /*
2702 * Disable all of the transmit blocks
2703 */
2704 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2705 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2706 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2707 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
2708 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
2709 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2710 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2711
2712 /*
2713 * Shut down all of the memory managers and related
2714 * state machines.
2715 */
2716 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
2717 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
2718 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2719 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2720 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2721 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
2722 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2723
2724 /* Disable host interrupts. */
2725 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2726 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2727
2728 /*
2729 * Tell firmware we're shutting down.
2730 */
2731 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2732
2733 /* Free the RX lists. */
2734 bge_free_rx_ring_std(sc);
2735
2736 /* Free jumbo RX list. */
2737 bge_free_rx_ring_jumbo(sc);
2738
2739 /* Free TX buffers. */
2740 bge_free_tx_ring(sc);
2741
2742 /*
2743 * Isolate/power down the PHY, but leave the media selection
2744 * unchanged so that things will be put back to normal when
2745 * we bring the interface back up.
2746 */
2747 if (!sc->bge_tbi) {
2748 itmp = ifp->if_flags;
2749 ifp->if_flags |= IFF_UP;
2750 ifm = mii->mii_media.ifm_cur;
2751 mtmp = ifm->ifm_media;
2752 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2753 mii_mediachg(mii);
2754 ifm->ifm_media = mtmp;
2755 ifp->if_flags = itmp;
2756 }
2757
2758 sc->bge_link = 0;
2759
2760 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
2761
2762 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2763
2764 return;
2765}
2766
2767/*
2768 * Stop all chip I/O so that the kernel's probe routines don't
2769 * get confused by errant DMAs when rebooting.
2770 */
2771static void
2772bge_shutdown(dev)
2773 device_t dev;
2774{
2775 struct bge_softc *sc;
2776
2777 sc = device_get_softc(dev);
2778
2779 bge_stop(sc);
2780 bge_reset(sc);
2781
2782 return;
2783}
| 150 { 0, 0, NULL }
151};
152
153static int bge_probe (device_t);
154static int bge_attach (device_t);
155static int bge_detach (device_t);
156static void bge_release_resources
157 (struct bge_softc *);
158static void bge_txeof (struct bge_softc *);
159static void bge_rxeof (struct bge_softc *);
160
161static void bge_tick (void *);
162static void bge_stats_update (struct bge_softc *);
163static int bge_encap (struct bge_softc *, struct mbuf *,
164 u_int32_t *);
165
166static void bge_intr (void *);
167static void bge_start (struct ifnet *);
168static int bge_ioctl (struct ifnet *, u_long, caddr_t);
169static void bge_init (void *);
170static void bge_stop (struct bge_softc *);
171static void bge_watchdog (struct ifnet *);
172static void bge_shutdown (device_t);
173static int bge_ifmedia_upd (struct ifnet *);
174static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *);
175
176static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *);
177static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int);
178
179static u_int32_t bge_crc (caddr_t);
180static void bge_setmulti (struct bge_softc *);
181
182static void bge_handle_events (struct bge_softc *);
183static int bge_alloc_jumbo_mem (struct bge_softc *);
184static void bge_free_jumbo_mem (struct bge_softc *);
185static void *bge_jalloc (struct bge_softc *);
186static void bge_jfree (void *, void *);
187static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *);
188static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *);
189static int bge_init_rx_ring_std (struct bge_softc *);
190static void bge_free_rx_ring_std (struct bge_softc *);
191static int bge_init_rx_ring_jumbo (struct bge_softc *);
192static void bge_free_rx_ring_jumbo (struct bge_softc *);
193static void bge_free_tx_ring (struct bge_softc *);
194static int bge_init_tx_ring (struct bge_softc *);
195
196static int bge_chipinit (struct bge_softc *);
197static int bge_blockinit (struct bge_softc *);
198
199#ifdef notdef
200static u_int8_t bge_vpd_readbyte(struct bge_softc *, int);
201static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int);
202static void bge_vpd_read (struct bge_softc *);
203#endif
204
205static u_int32_t bge_readmem_ind
206 (struct bge_softc *, int);
207static void bge_writemem_ind (struct bge_softc *, int, int);
208#ifdef notdef
209static u_int32_t bge_readreg_ind
210 (struct bge_softc *, int);
211#endif
212static void bge_writereg_ind (struct bge_softc *, int, int);
213
214static int bge_miibus_readreg (device_t, int, int);
215static int bge_miibus_writereg (device_t, int, int, int);
216static void bge_miibus_statchg (device_t);
217
218static void bge_reset (struct bge_softc *);
219static void bge_phy_hack (struct bge_softc *);
220
221static device_method_t bge_methods[] = {
222 /* Device interface */
223 DEVMETHOD(device_probe, bge_probe),
224 DEVMETHOD(device_attach, bge_attach),
225 DEVMETHOD(device_detach, bge_detach),
226 DEVMETHOD(device_shutdown, bge_shutdown),
227
228 /* bus interface */
229 DEVMETHOD(bus_print_child, bus_generic_print_child),
230 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
231
232 /* MII interface */
233 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
234 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
235 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
236
237 { 0, 0 }
238};
239
240static driver_t bge_driver = {
241 "bge",
242 bge_methods,
243 sizeof(struct bge_softc)
244};
245
246static devclass_t bge_devclass;
247
248DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
249DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
250
251static u_int32_t
252bge_readmem_ind(sc, off)
253 struct bge_softc *sc;
254 int off;
255{
256 device_t dev;
257
258 dev = sc->bge_dev;
259
260 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
261 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
262}
263
264static void
265bge_writemem_ind(sc, off, val)
266 struct bge_softc *sc;
267 int off, val;
268{
269 device_t dev;
270
271 dev = sc->bge_dev;
272
273 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
274 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
275
276 return;
277}
278
279#ifdef notdef
280static u_int32_t
281bge_readreg_ind(sc, off)
282 struct bge_softc *sc;
283 int off;
284{
285 device_t dev;
286
287 dev = sc->bge_dev;
288
289 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
290 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
291}
292#endif
293
294static void
295bge_writereg_ind(sc, off, val)
296 struct bge_softc *sc;
297 int off, val;
298{
299 device_t dev;
300
301 dev = sc->bge_dev;
302
303 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
304 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
305
306 return;
307}
308
309#ifdef notdef
310static u_int8_t
311bge_vpd_readbyte(sc, addr)
312 struct bge_softc *sc;
313 int addr;
314{
315 int i;
316 device_t dev;
317 u_int32_t val;
318
319 dev = sc->bge_dev;
320 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
321 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
322 DELAY(10);
323 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
324 break;
325 }
326
327 if (i == BGE_TIMEOUT) {
328 printf("bge%d: VPD read timed out\n", sc->bge_unit);
329 return(0);
330 }
331
332 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
333
334 return((val >> ((addr % 4) * 8)) & 0xFF);
335}
336
337static void
338bge_vpd_read_res(sc, res, addr)
339 struct bge_softc *sc;
340 struct vpd_res *res;
341 int addr;
342{
343 int i;
344 u_int8_t *ptr;
345
346 ptr = (u_int8_t *)res;
347 for (i = 0; i < sizeof(struct vpd_res); i++)
348 ptr[i] = bge_vpd_readbyte(sc, i + addr);
349
350 return;
351}
352
353static void
354bge_vpd_read(sc)
355 struct bge_softc *sc;
356{
357 int pos = 0, i;
358 struct vpd_res res;
359
360 if (sc->bge_vpd_prodname != NULL)
361 free(sc->bge_vpd_prodname, M_DEVBUF);
362 if (sc->bge_vpd_readonly != NULL)
363 free(sc->bge_vpd_readonly, M_DEVBUF);
364 sc->bge_vpd_prodname = NULL;
365 sc->bge_vpd_readonly = NULL;
366
367 bge_vpd_read_res(sc, &res, pos);
368
369 if (res.vr_id != VPD_RES_ID) {
370 printf("bge%d: bad VPD resource id: expected %x got %x\n",
371 sc->bge_unit, VPD_RES_ID, res.vr_id);
372 return;
373 }
374
375 pos += sizeof(res);
376 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
377 for (i = 0; i < res.vr_len; i++)
378 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
379 sc->bge_vpd_prodname[i] = '\0';
380 pos += i;
381
382 bge_vpd_read_res(sc, &res, pos);
383
384 if (res.vr_id != VPD_RES_READ) {
385 printf("bge%d: bad VPD resource id: expected %x got %x\n",
386 sc->bge_unit, VPD_RES_READ, res.vr_id);
387 return;
388 }
389
390 pos += sizeof(res);
391 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
392 for (i = 0; i < res.vr_len + 1; i++)
393 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
394
395 return;
396}
397#endif
398
399/*
400 * Read a byte of data stored in the EEPROM at address 'addr.' The
401 * BCM570x supports both the traditional bitbang interface and an
402 * auto access interface for reading the EEPROM. We use the auto
403 * access method.
404 */
405static u_int8_t
406bge_eeprom_getbyte(sc, addr, dest)
407 struct bge_softc *sc;
408 int addr;
409 u_int8_t *dest;
410{
411 int i;
412 u_int32_t byte = 0;
413
414 /*
415 * Enable use of auto EEPROM access so we can avoid
416 * having to use the bitbang method.
417 */
418 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
419
420 /* Reset the EEPROM, load the clock period. */
421 CSR_WRITE_4(sc, BGE_EE_ADDR,
422 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
423 DELAY(20);
424
425 /* Issue the read EEPROM command. */
426 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
427
428 /* Wait for completion */
429 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
430 DELAY(10);
431 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
432 break;
433 }
434
435 if (i == BGE_TIMEOUT) {
436 printf("bge%d: eeprom read timed out\n", sc->bge_unit);
437 return(0);
438 }
439
440 /* Get result. */
441 byte = CSR_READ_4(sc, BGE_EE_DATA);
442
443 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
444
445 return(0);
446}
447
448/*
449 * Read a sequence of bytes from the EEPROM.
450 */
451static int
452bge_read_eeprom(sc, dest, off, cnt)
453 struct bge_softc *sc;
454 caddr_t dest;
455 int off;
456 int cnt;
457{
458 int err = 0, i;
459 u_int8_t byte = 0;
460
461 for (i = 0; i < cnt; i++) {
462 err = bge_eeprom_getbyte(sc, off + i, &byte);
463 if (err)
464 break;
465 *(dest + i) = byte;
466 }
467
468 return(err ? 1 : 0);
469}
470
471static int
472bge_miibus_readreg(dev, phy, reg)
473 device_t dev;
474 int phy, reg;
475{
476 struct bge_softc *sc;
477 struct ifnet *ifp;
478 u_int32_t val;
479 int i;
480
481 sc = device_get_softc(dev);
482 ifp = &sc->arpcom.ac_if;
483
484 if (sc->bge_asicrev == BGE_ASICREV_BCM5701_B5 && phy != 1)
485 return(0);
486
487 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
488 BGE_MIPHY(phy)|BGE_MIREG(reg));
489
490 for (i = 0; i < BGE_TIMEOUT; i++) {
491 val = CSR_READ_4(sc, BGE_MI_COMM);
492 if (!(val & BGE_MICOMM_BUSY))
493 break;
494 }
495
496 if (i == BGE_TIMEOUT) {
497 printf("bge%d: PHY read timed out\n", sc->bge_unit);
498 return(0);
499 }
500
501 val = CSR_READ_4(sc, BGE_MI_COMM);
502
503 if (val & BGE_MICOMM_READFAIL)
504 return(0);
505
506 return(val & 0xFFFF);
507}
508
509static int
510bge_miibus_writereg(dev, phy, reg, val)
511 device_t dev;
512 int phy, reg, val;
513{
514 struct bge_softc *sc;
515 int i;
516
517 sc = device_get_softc(dev);
518
519 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
520 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
521
522 for (i = 0; i < BGE_TIMEOUT; i++) {
523 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
524 break;
525 }
526
527 if (i == BGE_TIMEOUT) {
528 printf("bge%d: PHY read timed out\n", sc->bge_unit);
529 return(0);
530 }
531
532 return(0);
533}
534
535static void
536bge_miibus_statchg(dev)
537 device_t dev;
538{
539 struct bge_softc *sc;
540 struct mii_data *mii;
541
542 sc = device_get_softc(dev);
543 mii = device_get_softc(sc->bge_miibus);
544
545 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
546 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
547 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
548 } else {
549 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
550 }
551
552 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
553 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
554 } else {
555 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
556 }
557
558 bge_phy_hack(sc);
559
560 return;
561}
562
563/*
564 * Handle events that have triggered interrupts.
565 */
566static void
567bge_handle_events(sc)
568 struct bge_softc *sc;
569{
570
571 return;
572}
573
574/*
575 * Memory management for jumbo frames.
576 */
577
578static int
579bge_alloc_jumbo_mem(sc)
580 struct bge_softc *sc;
581{
582 caddr_t ptr;
583 register int i;
584 struct bge_jpool_entry *entry;
585
586 /* Grab a big chunk o' storage. */
587 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
588 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
589
590 if (sc->bge_cdata.bge_jumbo_buf == NULL) {
591 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit);
592 return(ENOBUFS);
593 }
594
595 SLIST_INIT(&sc->bge_jfree_listhead);
596 SLIST_INIT(&sc->bge_jinuse_listhead);
597
598 /*
599 * Now divide it up into 9K pieces and save the addresses
600 * in an array.
601 */
602 ptr = sc->bge_cdata.bge_jumbo_buf;
603 for (i = 0; i < BGE_JSLOTS; i++) {
604 sc->bge_cdata.bge_jslots[i] = ptr;
605 ptr += BGE_JLEN;
606 entry = malloc(sizeof(struct bge_jpool_entry),
607 M_DEVBUF, M_NOWAIT);
608 if (entry == NULL) {
609 contigfree(sc->bge_cdata.bge_jumbo_buf,
610 BGE_JMEM, M_DEVBUF);
611 sc->bge_cdata.bge_jumbo_buf = NULL;
612 printf("bge%d: no memory for jumbo "
613 "buffer queue!\n", sc->bge_unit);
614 return(ENOBUFS);
615 }
616 entry->slot = i;
617 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
618 entry, jpool_entries);
619 }
620
621 return(0);
622}
623
624static void
625bge_free_jumbo_mem(sc)
626 struct bge_softc *sc;
627{
628 int i;
629 struct bge_jpool_entry *entry;
630
631 for (i = 0; i < BGE_JSLOTS; i++) {
632 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
633 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
634 free(entry, M_DEVBUF);
635 }
636
637 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
638
639 return;
640}
641
642/*
643 * Allocate a jumbo buffer.
644 */
645static void *
646bge_jalloc(sc)
647 struct bge_softc *sc;
648{
649 struct bge_jpool_entry *entry;
650
651 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
652
653 if (entry == NULL) {
654 printf("bge%d: no free jumbo buffers\n", sc->bge_unit);
655 return(NULL);
656 }
657
658 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
659 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
660 return(sc->bge_cdata.bge_jslots[entry->slot]);
661}
662
663/*
664 * Release a jumbo buffer.
665 */
666static void
667bge_jfree(buf, args)
668 void *buf;
669 void *args;
670{
671 struct bge_jpool_entry *entry;
672 struct bge_softc *sc;
673 int i;
674
675 /* Extract the softc struct pointer. */
676 sc = (struct bge_softc *)args;
677
678 if (sc == NULL)
679 panic("bge_jfree: can't find softc pointer!");
680
681 /* calculate the slot this buffer belongs to */
682
683 i = ((vm_offset_t)buf
684 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
685
686 if ((i < 0) || (i >= BGE_JSLOTS))
687 panic("bge_jfree: asked to free buffer that we don't manage!");
688
689 entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
690 if (entry == NULL)
691 panic("bge_jfree: buffer not in use!");
692 entry->slot = i;
693 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries);
694 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries);
695
696 return;
697}
698
699
700/*
701 * Intialize a standard receive ring descriptor.
702 */
703static int
704bge_newbuf_std(sc, i, m)
705 struct bge_softc *sc;
706 int i;
707 struct mbuf *m;
708{
709 struct mbuf *m_new = NULL;
710 struct bge_rx_bd *r;
711
712 if (m == NULL) {
713 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
714 if (m_new == NULL) {
715 return(ENOBUFS);
716 }
717
718 MCLGET(m_new, M_DONTWAIT);
719 if (!(m_new->m_flags & M_EXT)) {
720 m_freem(m_new);
721 return(ENOBUFS);
722 }
723 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
724 } else {
725 m_new = m;
726 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
727 m_new->m_data = m_new->m_ext.ext_buf;
728 }
729
730 if (!sc->bge_rx_alignment_bug)
731 m_adj(m_new, ETHER_ALIGN);
732 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
733 r = &sc->bge_rdata->bge_rx_std_ring[i];
734 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t));
735 r->bge_flags = BGE_RXBDFLAG_END;
736 r->bge_len = m_new->m_len;
737 r->bge_idx = i;
738
739 return(0);
740}
741
742/*
743 * Initialize a jumbo receive ring descriptor. This allocates
744 * a jumbo buffer from the pool managed internally by the driver.
745 */
746static int
747bge_newbuf_jumbo(sc, i, m)
748 struct bge_softc *sc;
749 int i;
750 struct mbuf *m;
751{
752 struct mbuf *m_new = NULL;
753 struct bge_rx_bd *r;
754
755 if (m == NULL) {
756 caddr_t *buf = NULL;
757
758 /* Allocate the mbuf. */
759 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
760 if (m_new == NULL) {
761 return(ENOBUFS);
762 }
763
764 /* Allocate the jumbo buffer */
765 buf = bge_jalloc(sc);
766 if (buf == NULL) {
767 m_freem(m_new);
768 printf("bge%d: jumbo allocation failed "
769 "-- packet dropped!\n", sc->bge_unit);
770 return(ENOBUFS);
771 }
772
773 /* Attach the buffer to the mbuf. */
774 m_new->m_data = (void *) buf;
775 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN;
776 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree,
777 (struct bge_softc *)sc, 0, EXT_NET_DRV);
778 } else {
779 m_new = m;
780 m_new->m_data = m_new->m_ext.ext_buf;
781 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
782 }
783
784 if (!sc->bge_rx_alignment_bug)
785 m_adj(m_new, ETHER_ALIGN);
786 /* Set up the descriptor. */
787 r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
788 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
789 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t));
790 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
791 r->bge_len = m_new->m_len;
792 r->bge_idx = i;
793
794 return(0);
795}
796
797/*
798 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
799 * that's 1MB or memory, which is a lot. For now, we fill only the first
800 * 256 ring entries and hope that our CPU is fast enough to keep up with
801 * the NIC.
802 */
803static int
804bge_init_rx_ring_std(sc)
805 struct bge_softc *sc;
806{
807 int i;
808
809 for (i = 0; i < BGE_SSLOTS; i++) {
810 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
811 return(ENOBUFS);
812 };
813
814 sc->bge_std = i - 1;
815 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
816
817 return(0);
818}
819
820static void
821bge_free_rx_ring_std(sc)
822 struct bge_softc *sc;
823{
824 int i;
825
826 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
827 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
828 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
829 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
830 }
831 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i],
832 sizeof(struct bge_rx_bd));
833 }
834
835 return;
836}
837
838static int
839bge_init_rx_ring_jumbo(sc)
840 struct bge_softc *sc;
841{
842 int i;
843 struct bge_rcb *rcb;
844 struct bge_rcb_opaque *rcbo;
845
846 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
847 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
848 return(ENOBUFS);
849 };
850
851 sc->bge_jumbo = i - 1;
852
853 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
854 rcbo = (struct bge_rcb_opaque *)rcb;
855 rcb->bge_flags = 0;
856 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
857
858 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
859
860 return(0);
861}
862
863static void
864bge_free_rx_ring_jumbo(sc)
865 struct bge_softc *sc;
866{
867 int i;
868
869 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
870 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
871 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
872 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
873 }
874 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i],
875 sizeof(struct bge_rx_bd));
876 }
877
878 return;
879}
880
881static void
882bge_free_tx_ring(sc)
883 struct bge_softc *sc;
884{
885 int i;
886
887 if (sc->bge_rdata->bge_tx_ring == NULL)
888 return;
889
890 for (i = 0; i < BGE_TX_RING_CNT; i++) {
891 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
892 m_freem(sc->bge_cdata.bge_tx_chain[i]);
893 sc->bge_cdata.bge_tx_chain[i] = NULL;
894 }
895 bzero((char *)&sc->bge_rdata->bge_tx_ring[i],
896 sizeof(struct bge_tx_bd));
897 }
898
899 return;
900}
901
902static int
903bge_init_tx_ring(sc)
904 struct bge_softc *sc;
905{
906 sc->bge_txcnt = 0;
907 sc->bge_tx_saved_considx = 0;
908 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
909 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
910
911 return(0);
912}
913
914#define BGE_POLY 0xEDB88320
915
916static u_int32_t
917bge_crc(addr)
918 caddr_t addr;
919{
920 u_int32_t idx, bit, data, crc;
921
922 /* Compute CRC for the address value. */
923 crc = 0xFFFFFFFF; /* initial value */
924
925 for (idx = 0; idx < 6; idx++) {
926 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
927 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0);
928 }
929
930 return(crc & 0x7F);
931}
932
933static void
934bge_setmulti(sc)
935 struct bge_softc *sc;
936{
937 struct ifnet *ifp;
938 struct ifmultiaddr *ifma;
939 u_int32_t hashes[4] = { 0, 0, 0, 0 };
940 int h, i;
941
942 ifp = &sc->arpcom.ac_if;
943
944 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
945 for (i = 0; i < 4; i++)
946 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
947 return;
948 }
949
950 /* First, zot all the existing filters. */
951 for (i = 0; i < 4; i++)
952 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
953
954 /* Now program new ones. */
955 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
956 if (ifma->ifma_addr->sa_family != AF_LINK)
957 continue;
958 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
959 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
960 }
961
962 for (i = 0; i < 4; i++)
963 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
964
965 return;
966}
967
968/*
969 * Do endian, PCI and DMA initialization. Also check the on-board ROM
970 * self-test results.
971 */
972static int
973bge_chipinit(sc)
974 struct bge_softc *sc;
975{
976 u_int32_t cachesize;
977 int i;
978
979 /* Set endianness before we access any non-PCI registers. */
980#if BYTE_ORDER == BIG_ENDIAN
981 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
982 BGE_BIGENDIAN_INIT, 4);
983#else
984 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
985 BGE_LITTLEENDIAN_INIT, 4);
986#endif
987
988 /*
989 * Check the 'ROM failed' bit on the RX CPU to see if
990 * self-tests passed.
991 */
992 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
993 printf("bge%d: RX CPU self-diagnostics failed!\n",
994 sc->bge_unit);
995 return(ENODEV);
996 }
997
998 /* Clear the MAC control register */
999 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1000
1001 /*
1002 * Clear the MAC statistics block in the NIC's
1003 * internal memory.
1004 */
1005 for (i = BGE_STATS_BLOCK;
1006 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
1007 BGE_MEMWIN_WRITE(sc, i, 0);
1008
1009 for (i = BGE_STATUS_BLOCK;
1010 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
1011 BGE_MEMWIN_WRITE(sc, i, 0);
1012
1013 /* Set up the PCI DMA control register. */
1014 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1015 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F, 4);
1016
1017 /*
1018 * Set up general mode register.
1019 */
1020 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1021 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1022 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1023 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM|
1024 BGE_MODECTL_RX_NO_PHDR_CSUM);
1025
1026 /* Get cache line size. */
1027 cachesize = pci_read_config(sc->bge_dev, BGE_PCI_CACHESZ, 1);
1028
1029 /*
1030 * Avoid violating PCI spec on certain chip revs.
1031 */
1032 if (pci_read_config(sc->bge_dev, BGE_PCI_CMD, 4) & PCIM_CMD_MWIEN) {
1033 switch(cachesize) {
1034 case 1:
1035 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1036 BGE_PCI_WRITE_BNDRY_16BYTES, 4);
1037 break;
1038 case 2:
1039 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1040 BGE_PCI_WRITE_BNDRY_32BYTES, 4);
1041 break;
1042 case 4:
1043 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1044 BGE_PCI_WRITE_BNDRY_64BYTES, 4);
1045 break;
1046 case 8:
1047 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1048 BGE_PCI_WRITE_BNDRY_128BYTES, 4);
1049 break;
1050 case 16:
1051 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1052 BGE_PCI_WRITE_BNDRY_256BYTES, 4);
1053 break;
1054 case 32:
1055 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1056 BGE_PCI_WRITE_BNDRY_512BYTES, 4);
1057 break;
1058 case 64:
1059 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1060 BGE_PCI_WRITE_BNDRY_1024BYTES, 4);
1061 break;
1062 default:
1063 /* Disable PCI memory write and invalidate. */
1064 if (bootverbose)
1065 printf("bge%d: cache line size %d not "
1066 "supported; disabling PCI MWI\n",
1067 sc->bge_unit, cachesize);
1068 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1069 PCIM_CMD_MWIEN, 4);
1070 break;
1071 }
1072 }
1073
1074#ifdef __brokenalpha__
1075 /*
1076 * Must insure that we do not cross an 8K (bytes) boundary
1077 * for DMA reads. Our highest limit is 1K bytes. This is a
1078 * restriction on some ALPHA platforms with early revision
1079 * 21174 PCI chipsets, such as the AlphaPC 164lx
1080 */
1081 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4);
1082#endif
1083
1084 /* Set the timer prescaler (always 66Mhz) */
1085 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1086
1087 return(0);
1088}
1089
1090static int
1091bge_blockinit(sc)
1092 struct bge_softc *sc;
1093{
1094 struct bge_rcb *rcb;
1095 struct bge_rcb_opaque *rcbo;
1096 int i;
1097
1098 /*
1099 * Initialize the memory window pointer register so that
1100 * we can access the first 32K of internal NIC RAM. This will
1101 * allow us to set up the TX send ring RCBs and the RX return
1102 * ring RCBs, plus other things which live in NIC memory.
1103 */
1104 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1105
1106 /* Configure mbuf memory pool */
1107 if (sc->bge_extram) {
1108 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM);
1109 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1110 } else {
1111 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1112 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1113 }
1114
1115 /* Configure DMA resource pool */
1116 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS);
1117 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1118
1119 /* Configure mbuf pool watermarks */
1120 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24);
1121 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24);
1122 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48);
1123
1124 /* Configure DMA resource watermarks */
1125 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1126 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1127
1128 /* Enable buffer manager */
1129 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1130 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1131
1132 /* Poll for buffer manager start indication */
1133 for (i = 0; i < BGE_TIMEOUT; i++) {
1134 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1135 break;
1136 DELAY(10);
1137 }
1138
1139 if (i == BGE_TIMEOUT) {
1140 printf("bge%d: buffer manager failed to start\n",
1141 sc->bge_unit);
1142 return(ENXIO);
1143 }
1144
1145 /* Enable flow-through queues */
1146 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1147 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1148
1149 /* Wait until queue initialization is complete */
1150 for (i = 0; i < BGE_TIMEOUT; i++) {
1151 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1152 break;
1153 DELAY(10);
1154 }
1155
1156 if (i == BGE_TIMEOUT) {
1157 printf("bge%d: flow-through queue init failed\n",
1158 sc->bge_unit);
1159 return(ENXIO);
1160 }
1161
1162 /* Initialize the standard RX ring control block */
1163 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1164 BGE_HOSTADDR(rcb->bge_hostaddr) =
1165 vtophys(&sc->bge_rdata->bge_rx_std_ring);
1166 rcb->bge_max_len = BGE_MAX_FRAMELEN;
1167 if (sc->bge_extram)
1168 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1169 else
1170 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1171 rcb->bge_flags = 0;
1172 rcbo = (struct bge_rcb_opaque *)rcb;
1173 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0);
1174 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1);
1175 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
1176 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3);
1177
1178 /*
1179 * Initialize the jumbo RX ring control block
1180 * We set the 'ring disabled' bit in the flags
1181 * field until we're actually ready to start
1182 * using this ring (i.e. once we set the MTU
1183 * high enough to require it).
1184 */
1185 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1186 BGE_HOSTADDR(rcb->bge_hostaddr) =
1187 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring);
1188 rcb->bge_max_len = BGE_MAX_FRAMELEN;
1189 if (sc->bge_extram)
1190 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1191 else
1192 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1193 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
1194
1195 rcbo = (struct bge_rcb_opaque *)rcb;
1196 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0);
1197 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1);
1198 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
1199 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3);
1200
1201 /* Set up dummy disabled mini ring RCB */
1202 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1203 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
1204 rcbo = (struct bge_rcb_opaque *)rcb;
1205 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2);
1206
1207 /*
1208 * Set the BD ring replentish thresholds. The recommended
1209 * values are 1/8th the number of descriptors allocated to
1210 * each ring.
1211 */
1212 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1213 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1214
1215 /*
1216 * Disable all unused send rings by setting the 'ring disabled'
1217 * bit in the flags field of all the TX send ring control blocks.
1218 * These are located in NIC memory.
1219 */
1220 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1221 BGE_SEND_RING_RCB);
1222 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1223 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
1224 rcb->bge_max_len = 0;
1225 rcb->bge_nicaddr = 0;
1226 rcb++;
1227 }
1228
1229 /* Configure TX RCB 0 (we use only the first ring) */
1230 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1231 BGE_SEND_RING_RCB);
1232 rcb->bge_hostaddr.bge_addr_hi = 0;
1233 BGE_HOSTADDR(rcb->bge_hostaddr) =
1234 vtophys(&sc->bge_rdata->bge_tx_ring);
1235 rcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1236 rcb->bge_max_len = BGE_TX_RING_CNT;
1237 rcb->bge_flags = 0;
1238
1239 /* Disable all unused RX return rings */
1240 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1241 BGE_RX_RETURN_RING_RCB);
1242 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1243 rcb->bge_hostaddr.bge_addr_hi = 0;
1244 rcb->bge_hostaddr.bge_addr_lo = 0;
1245 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED;
1246 rcb->bge_max_len = BGE_RETURN_RING_CNT;
1247 rcb->bge_nicaddr = 0;
1248 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1249 (i * (sizeof(u_int64_t))), 0);
1250 rcb++;
1251 }
1252
1253 /* Initialize RX ring indexes */
1254 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1255 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1256 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1257
1258 /*
1259 * Set up RX return ring 0
1260 * Note that the NIC address for RX return rings is 0x00000000.
1261 * The return rings live entirely within the host, so the
1262 * nicaddr field in the RCB isn't used.
1263 */
1264 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1265 BGE_RX_RETURN_RING_RCB);
1266 rcb->bge_hostaddr.bge_addr_hi = 0;
1267 BGE_HOSTADDR(rcb->bge_hostaddr) =
1268 vtophys(&sc->bge_rdata->bge_rx_return_ring);
1269 rcb->bge_nicaddr = 0x00000000;
1270 rcb->bge_max_len = BGE_RETURN_RING_CNT;
1271 rcb->bge_flags = 0;
1272
1273 /* Set random backoff seed for TX */
1274 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1275 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1276 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1277 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1278 BGE_TX_BACKOFF_SEED_MASK);
1279
1280 /* Set inter-packet gap */
1281 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1282
1283 /*
1284 * Specify which ring to use for packets that don't match
1285 * any RX rules.
1286 */
1287 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1288
1289 /*
1290 * Configure number of RX lists. One interrupt distribution
1291 * list, sixteen active lists, one bad frames class.
1292 */
1293 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1294
1295 /* Inialize RX list placement stats mask. */
1296 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1297 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1298
1299 /* Disable host coalescing until we get it set up */
1300 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1301
1302 /* Poll to make sure it's shut down. */
1303 for (i = 0; i < BGE_TIMEOUT; i++) {
1304 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1305 break;
1306 DELAY(10);
1307 }
1308
1309 if (i == BGE_TIMEOUT) {
1310 printf("bge%d: host coalescing engine failed to idle\n",
1311 sc->bge_unit);
1312 return(ENXIO);
1313 }
1314
1315 /* Set up host coalescing defaults */
1316 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1317 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1318 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1319 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1320 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1321 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1322 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1323 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1324 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1325
1326 /* Set up address of statistics block */
1327 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1328 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1329 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1330 vtophys(&sc->bge_rdata->bge_info.bge_stats));
1331
1332 /* Set up address of status block */
1333 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1334 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1335 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1336 vtophys(&sc->bge_rdata->bge_status_block));
1337 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1338 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1339
1340 /* Turn on host coalescing state machine */
1341 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1342
1343 /* Turn on RX BD completion state machine and enable attentions */
1344 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1345 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1346
1347 /* Turn on RX list placement state machine */
1348 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1349
1350 /* Turn on RX list selector state machine. */
1351 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1352
1353 /* Turn on DMA, clear stats */
1354 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1355 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1356 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1357 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1358 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1359
1360 /* Set misc. local control, enable interrupts on attentions */
1361 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1362
1363#ifdef notdef
1364 /* Assert GPIO pins for PHY reset */
1365 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1366 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1367 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1368 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1369#endif
1370
1371 /* Turn on DMA completion state machine */
1372 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1373
1374 /* Turn on write DMA state machine */
1375 CSR_WRITE_4(sc, BGE_WDMA_MODE,
1376 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1377
1378 /* Turn on read DMA state machine */
1379 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1380 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1381
1382 /* Turn on RX data completion state machine */
1383 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1384
1385 /* Turn on RX BD initiator state machine */
1386 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1387
1388 /* Turn on RX data and RX BD initiator state machine */
1389 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1390
1391 /* Turn on Mbuf cluster free state machine */
1392 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1393
1394 /* Turn on send BD completion state machine */
1395 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1396
1397 /* Turn on send data completion state machine */
1398 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1399
1400 /* Turn on send data initiator state machine */
1401 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1402
1403 /* Turn on send BD initiator state machine */
1404 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1405
1406 /* Turn on send BD selector state machine */
1407 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1408
1409 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1410 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1411 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1412
1413 /* init LED register */
1414 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000);
1415
1416 /* ack/clear link change events */
1417 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1418 BGE_MACSTAT_CFG_CHANGED);
1419 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1420
1421 /* Enable PHY auto polling (for MII/GMII only) */
1422 if (sc->bge_tbi) {
1423 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1424 } else {
1425 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1426 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1427 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1428 BGE_EVTENB_MI_INTERRUPT);
1429 }
1430
1431 /* Enable link state change attentions. */
1432 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1433
1434 return(0);
1435}
1436
1437/*
1438 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1439 * against our list and return its name if we find a match. Note
1440 * that since the Broadcom controller contains VPD support, we
1441 * can get the device name string from the controller itself instead
1442 * of the compiled-in string. This is a little slow, but it guarantees
1443 * we'll always announce the right product name.
1444 */
1445static int
1446bge_probe(dev)
1447 device_t dev;
1448{
1449 struct bge_type *t;
1450 struct bge_softc *sc;
1451
1452 t = bge_devs;
1453
1454 sc = device_get_softc(dev);
1455 bzero(sc, sizeof(struct bge_softc));
1456 sc->bge_unit = device_get_unit(dev);
1457 sc->bge_dev = dev;
1458
1459 while(t->bge_name != NULL) {
1460 if ((pci_get_vendor(dev) == t->bge_vid) &&
1461 (pci_get_device(dev) == t->bge_did)) {
1462#ifdef notdef
1463 bge_vpd_read(sc);
1464 device_set_desc(dev, sc->bge_vpd_prodname);
1465#endif
1466 device_set_desc(dev, t->bge_name);
1467 return(0);
1468 }
1469 t++;
1470 }
1471
1472 return(ENXIO);
1473}
1474
1475static int
1476bge_attach(dev)
1477 device_t dev;
1478{
1479 int s;
1480 u_int32_t command;
1481 struct ifnet *ifp;
1482 struct bge_softc *sc;
1483 u_int32_t hwcfg = 0;
1484 int unit, error = 0, rid;
1485
1486 s = splimp();
1487
1488 sc = device_get_softc(dev);
1489 unit = device_get_unit(dev);
1490 sc->bge_dev = dev;
1491 sc->bge_unit = unit;
1492
1493 /*
1494 * Map control/status registers.
1495 */
1496 pci_enable_busmaster(dev);
1497 pci_enable_io(dev, SYS_RES_MEMORY);
1498 command = pci_read_config(dev, PCIR_COMMAND, 4);
1499
1500 if (!(command & PCIM_CMD_MEMEN)) {
1501 printf("bge%d: failed to enable memory mapping!\n", unit);
1502 error = ENXIO;
1503 goto fail;
1504 }
1505
1506 rid = BGE_PCI_BAR0;
1507 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1508 0, ~0, 1, RF_ACTIVE);
1509
1510 if (sc->bge_res == NULL) {
1511 printf ("bge%d: couldn't map memory\n", unit);
1512 error = ENXIO;
1513 goto fail;
1514 }
1515
1516 sc->bge_btag = rman_get_bustag(sc->bge_res);
1517 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1518 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1519
1520 /*
1521 * XXX FIXME: rman_get_virtual() on the alpha is currently
1522 * broken and returns a physical address instead of a kernel
1523 * virtual address. Consequently, we need to do a little
1524 * extra mangling of the vhandle on the alpha. This should
1525 * eventually be fixed! The whole idea here is to get rid
1526 * of platform dependencies.
1527 */
1528#ifdef __alpha__
1529 if (pci_cvt_to_bwx(sc->bge_vhandle))
1530 sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle);
1531 else
1532 sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle);
1533 sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle);
1534#endif
1535
1536 /* Allocate interrupt */
1537 rid = 0;
1538
1539 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1540 RF_SHAREABLE | RF_ACTIVE);
1541
1542 if (sc->bge_irq == NULL) {
1543 printf("bge%d: couldn't map interrupt\n", unit);
1544 error = ENXIO;
1545 goto fail;
1546 }
1547
1548 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET,
1549 bge_intr, sc, &sc->bge_intrhand);
1550
1551 if (error) {
1552 bge_release_resources(sc);
1553 printf("bge%d: couldn't set up irq\n", unit);
1554 goto fail;
1555 }
1556
1557 sc->bge_unit = unit;
1558
1559 /* Try to reset the chip. */
1560 bge_reset(sc);
1561
1562 if (bge_chipinit(sc)) {
1563 printf("bge%d: chip initialization failed\n", sc->bge_unit);
1564 bge_release_resources(sc);
1565 error = ENXIO;
1566 goto fail;
1567 }
1568
1569 /*
1570 * Get station address from the EEPROM.
1571 */
1572 if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1573 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1574 printf("bge%d: failed to read station address\n", unit);
1575 bge_release_resources(sc);
1576 error = ENXIO;
1577 goto fail;
1578 }
1579
1580 /*
1581 * A Broadcom chip was detected. Inform the world.
1582 */
1583 printf("bge%d: Ethernet address: %6D\n", unit,
1584 sc->arpcom.ac_enaddr, ":");
1585
1586 /* Allocate the general information block and ring buffers. */
1587 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1588 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1589
1590 if (sc->bge_rdata == NULL) {
1591 bge_release_resources(sc);
1592 error = ENXIO;
1593 printf("bge%d: no memory for list buffers!\n", sc->bge_unit);
1594 goto fail;
1595 }
1596
1597 bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1598
1599 /* Try to allocate memory for jumbo buffers. */
1600 if (bge_alloc_jumbo_mem(sc)) {
1601 printf("bge%d: jumbo buffer allocation "
1602 "failed\n", sc->bge_unit);
1603 bge_release_resources(sc);
1604 error = ENXIO;
1605 goto fail;
1606 }
1607
1608 /* Set default tuneable values. */
1609 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1610 sc->bge_rx_coal_ticks = 150;
1611 sc->bge_tx_coal_ticks = 150;
1612 sc->bge_rx_max_coal_bds = 64;
1613 sc->bge_tx_max_coal_bds = 128;
1614
1615 /* Set up ifnet structure */
1616 ifp = &sc->arpcom.ac_if;
1617 ifp->if_softc = sc;
1618 ifp->if_unit = sc->bge_unit;
1619 ifp->if_name = "bge";
1620 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1621 ifp->if_ioctl = bge_ioctl;
1622 ifp->if_output = ether_output;
1623 ifp->if_start = bge_start;
1624 ifp->if_watchdog = bge_watchdog;
1625 ifp->if_init = bge_init;
1626 ifp->if_mtu = ETHERMTU;
1627 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1;
1628 ifp->if_hwassist = BGE_CSUM_FEATURES;
1629 ifp->if_capabilities = IFCAP_HWCSUM;
1630 ifp->if_capenable = ifp->if_capabilities;
1631
1632 /* Save ASIC rev. */
1633
1634 sc->bge_asicrev =
1635 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1636 BGE_PCIMISCCTL_ASICREV;
1637
1638 /* Pretend all 5700s are the same */
1639 if ((sc->bge_asicrev & 0xFF000000) == BGE_ASICREV_BCM5700)
1640 sc->bge_asicrev = BGE_ASICREV_BCM5700;
1641
1642 /*
1643 * Figure out what sort of media we have by checking the
1644 * hardware config word in the EEPROM. Note: on some BCM5700
1645 * cards, this value appears to be unset. If that's the
1646 * case, we have to rely on identifying the NIC by its PCI
1647 * subsystem ID, as we do below for the SysKonnect SK-9D41.
1648 */
1649 bge_read_eeprom(sc, (caddr_t)&hwcfg,
1650 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
1651 if ((ntohl(hwcfg) & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1652 sc->bge_tbi = 1;
1653
1654 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1655 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
1656 sc->bge_tbi = 1;
1657
1658 if (sc->bge_tbi) {
1659 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1660 bge_ifmedia_upd, bge_ifmedia_sts);
1661 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1662 ifmedia_add(&sc->bge_ifmedia,
1663 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1664 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1665 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1666 } else {
1667 /*
1668 * Do transceiver setup.
1669 */
1670 if (mii_phy_probe(dev, &sc->bge_miibus,
1671 bge_ifmedia_upd, bge_ifmedia_sts)) {
1672 printf("bge%d: MII without any PHY!\n", sc->bge_unit);
1673 bge_release_resources(sc);
1674 bge_free_jumbo_mem(sc);
1675 error = ENXIO;
1676 goto fail;
1677 }
1678 }
1679
1680 /*
1681 * When using the BCM5701 in PCI-X mode, data corruption has
1682 * been observed in the first few bytes of some received packets.
1683 * Aligning the packet buffer in memory eliminates the corruption.
1684 * Unfortunately, this misaligns the packet payloads. On platforms
1685 * which do not support unaligned accesses, we will realign the
1686 * payloads by copying the received packets.
1687 */
1688 switch (sc->bge_asicrev) {
1689 case BGE_ASICREV_BCM5701_A0:
1690 case BGE_ASICREV_BCM5701_B0:
1691 case BGE_ASICREV_BCM5701_B2:
1692 case BGE_ASICREV_BCM5701_B5:
1693 /* If in PCI-X mode, work around the alignment bug. */
1694 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
1695 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
1696 BGE_PCISTATE_PCI_BUSSPEED)
1697 sc->bge_rx_alignment_bug = 1;
1698 break;
1699 }
1700
1701 /*
1702 * Call MI attach routine.
1703 */
1704 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1705 callout_handle_init(&sc->bge_stat_ch);
1706
1707fail:
1708 splx(s);
1709
1710 return(error);
1711}
1712
1713static int
1714bge_detach(dev)
1715 device_t dev;
1716{
1717 struct bge_softc *sc;
1718 struct ifnet *ifp;
1719 int s;
1720
1721 s = splimp();
1722
1723 sc = device_get_softc(dev);
1724 ifp = &sc->arpcom.ac_if;
1725
1726 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1727 bge_stop(sc);
1728 bge_reset(sc);
1729
1730 if (sc->bge_tbi) {
1731 ifmedia_removeall(&sc->bge_ifmedia);
1732 } else {
1733 bus_generic_detach(dev);
1734 device_delete_child(dev, sc->bge_miibus);
1735 }
1736
1737 bge_release_resources(sc);
1738 bge_free_jumbo_mem(sc);
1739
1740 splx(s);
1741
1742 return(0);
1743}
1744
1745static void
1746bge_release_resources(sc)
1747 struct bge_softc *sc;
1748{
1749 device_t dev;
1750
1751 dev = sc->bge_dev;
1752
1753 if (sc->bge_vpd_prodname != NULL)
1754 free(sc->bge_vpd_prodname, M_DEVBUF);
1755
1756 if (sc->bge_vpd_readonly != NULL)
1757 free(sc->bge_vpd_readonly, M_DEVBUF);
1758
1759 if (sc->bge_intrhand != NULL)
1760 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1761
1762 if (sc->bge_irq != NULL)
1763 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1764
1765 if (sc->bge_res != NULL)
1766 bus_release_resource(dev, SYS_RES_MEMORY,
1767 BGE_PCI_BAR0, sc->bge_res);
1768
1769 if (sc->bge_rdata != NULL)
1770 contigfree(sc->bge_rdata,
1771 sizeof(struct bge_ring_data), M_DEVBUF);
1772
1773 return;
1774}
1775
1776static void
1777bge_reset(sc)
1778 struct bge_softc *sc;
1779{
1780 device_t dev;
1781 u_int32_t cachesize, command, pcistate;
1782 int i, val = 0;
1783
1784 dev = sc->bge_dev;
1785
1786 /* Save some important PCI state. */
1787 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1788 command = pci_read_config(dev, BGE_PCI_CMD, 4);
1789 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1790
1791 pci_write_config(dev, BGE_PCI_MISC_CTL,
1792 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1793 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1794
1795 /* Issue global reset */
1796 bge_writereg_ind(sc, BGE_MISC_CFG,
1797 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1));
1798
1799 DELAY(1000);
1800
1801 /* Reset some of the PCI state that got zapped by reset */
1802 pci_write_config(dev, BGE_PCI_MISC_CTL,
1803 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1804 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1805 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
1806 pci_write_config(dev, BGE_PCI_CMD, command, 4);
1807 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
1808
1809 /*
1810 * Prevent PXE restart: write a magic number to the
1811 * general communications memory at 0xB50.
1812 */
1813 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1814 /*
1815 * Poll the value location we just wrote until
1816 * we see the 1's complement of the magic number.
1817 * This indicates that the firmware initialization
1818 * is complete.
1819 */
1820 for (i = 0; i < BGE_TIMEOUT; i++) {
1821 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
1822 if (val == ~BGE_MAGIC_NUMBER)
1823 break;
1824 DELAY(10);
1825 }
1826
1827 if (i == BGE_TIMEOUT) {
1828 printf("bge%d: firmware handshake timed out\n", sc->bge_unit);
1829 return;
1830 }
1831
1832 /*
1833 * XXX Wait for the value of the PCISTATE register to
1834 * return to its original pre-reset state. This is a
1835 * fairly good indicator of reset completion. If we don't
1836 * wait for the reset to fully complete, trying to read
1837 * from the device's non-PCI registers may yield garbage
1838 * results.
1839 */
1840 for (i = 0; i < BGE_TIMEOUT; i++) {
1841 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
1842 break;
1843 DELAY(10);
1844 }
1845
1846 /* Enable memory arbiter. */
1847 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
1848
1849 /* Fix up byte swapping */
1850 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
1851 BGE_MODECTL_BYTESWAP_DATA);
1852
1853 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1854
1855 DELAY(10000);
1856
1857 return;
1858}
1859
1860/*
1861 * Frame reception handling. This is called if there's a frame
1862 * on the receive return list.
1863 *
1864 * Note: we have to be able to handle two possibilities here:
1865 * 1) the frame is from the jumbo recieve ring
1866 * 2) the frame is from the standard receive ring
1867 */
1868
1869static void
1870bge_rxeof(sc)
1871 struct bge_softc *sc;
1872{
1873 struct ifnet *ifp;
1874 int stdcnt = 0, jumbocnt = 0;
1875
1876 ifp = &sc->arpcom.ac_if;
1877
1878 while(sc->bge_rx_saved_considx !=
1879 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
1880 struct bge_rx_bd *cur_rx;
1881 u_int32_t rxidx;
1882 struct ether_header *eh;
1883 struct mbuf *m = NULL;
1884 u_int16_t vlan_tag = 0;
1885 int have_tag = 0;
1886
1887 cur_rx =
1888 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
1889
1890 rxidx = cur_rx->bge_idx;
1891 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT);
1892
1893 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
1894 have_tag = 1;
1895 vlan_tag = cur_rx->bge_vlan_tag;
1896 }
1897
1898 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
1899 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1900 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
1901 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
1902 jumbocnt++;
1903 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1904 ifp->if_ierrors++;
1905 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1906 continue;
1907 }
1908 if (bge_newbuf_jumbo(sc,
1909 sc->bge_jumbo, NULL) == ENOBUFS) {
1910 ifp->if_ierrors++;
1911 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1912 continue;
1913 }
1914 } else {
1915 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1916 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
1917 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
1918 stdcnt++;
1919 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1920 ifp->if_ierrors++;
1921 bge_newbuf_std(sc, sc->bge_std, m);
1922 continue;
1923 }
1924 if (bge_newbuf_std(sc, sc->bge_std,
1925 NULL) == ENOBUFS) {
1926 ifp->if_ierrors++;
1927 bge_newbuf_std(sc, sc->bge_std, m);
1928 continue;
1929 }
1930 }
1931
1932 ifp->if_ipackets++;
1933#ifndef __i386__
1934 /*
1935 * The i386 allows unaligned accesses, but for other
1936 * platforms we must make sure the payload is aligned.
1937 */
1938 if (sc->bge_rx_alignment_bug) {
1939 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
1940 cur_rx->bge_len);
1941 m->m_data += ETHER_ALIGN;
1942 }
1943#endif
1944 eh = mtod(m, struct ether_header *);
1945 m->m_pkthdr.len = m->m_len = cur_rx->bge_len;
1946 m->m_pkthdr.rcvif = ifp;
1947
1948 /* Remove header from mbuf and pass it on. */
1949 m_adj(m, sizeof(struct ether_header));
1950
1951#if 0 /* currently broken for some packets, possibly related to TCP options */
1952 if (ifp->if_hwassist) {
1953 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1954 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
1955 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1956 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
1957 m->m_pkthdr.csum_data =
1958 cur_rx->bge_tcp_udp_csum;
1959 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1960 }
1961 }
1962#endif
1963
1964 /*
1965 * If we received a packet with a vlan tag, pass it
1966 * to vlan_input() instead of ether_input().
1967 */
1968 if (have_tag) {
1969 VLAN_INPUT_TAG(eh, m, vlan_tag);
1970 have_tag = vlan_tag = 0;
1971 continue;
1972 }
1973
1974 ether_input(ifp, eh, m);
1975 }
1976
1977 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
1978 if (stdcnt)
1979 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1980 if (jumbocnt)
1981 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1982
1983 return;
1984}
1985
1986static void
1987bge_txeof(sc)
1988 struct bge_softc *sc;
1989{
1990 struct bge_tx_bd *cur_tx = NULL;
1991 struct ifnet *ifp;
1992
1993 ifp = &sc->arpcom.ac_if;
1994
1995 /*
1996 * Go through our tx ring and free mbufs for those
1997 * frames that have been sent.
1998 */
1999 while (sc->bge_tx_saved_considx !=
2000 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
2001 u_int32_t idx = 0;
2002
2003 idx = sc->bge_tx_saved_considx;
2004 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
2005 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2006 ifp->if_opackets++;
2007 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2008 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2009 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2010 }
2011 sc->bge_txcnt--;
2012 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2013 ifp->if_timer = 0;
2014 }
2015
2016 if (cur_tx != NULL)
2017 ifp->if_flags &= ~IFF_OACTIVE;
2018
2019 return;
2020}
2021
2022static void
2023bge_intr(xsc)
2024 void *xsc;
2025{
2026 struct bge_softc *sc;
2027 struct ifnet *ifp;
2028
2029 sc = xsc;
2030 ifp = &sc->arpcom.ac_if;
2031
2032#ifdef notdef
2033 /* Avoid this for now -- checking this register is expensive. */
2034 /* Make sure this is really our interrupt. */
2035 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
2036 return;
2037#endif
2038 /* Ack interrupt and stop others from occuring. */
2039 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2040
2041 /*
2042 * Process link state changes.
2043 * Grrr. The link status word in the status block does
2044 * not work correctly on the BCM5700 rev AX and BX chips,
2045 * according to all avaibable information. Hence, we have
2046 * to enable MII interrupts in order to properly obtain
2047 * async link changes. Unfortunately, this also means that
2048 * we have to read the MAC status register to detect link
2049 * changes, thereby adding an additional register access to
2050 * the interrupt handler.
2051 */
2052
2053 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2054 u_int32_t status;
2055
2056 status = CSR_READ_4(sc, BGE_MAC_STS);
2057 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2058 sc->bge_link = 0;
2059 untimeout(bge_tick, sc, sc->bge_stat_ch);
2060 bge_tick(sc);
2061 /* Clear the interrupt */
2062 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2063 BGE_EVTENB_MI_INTERRUPT);
2064 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2065 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2066 BRGPHY_INTRS);
2067 }
2068 } else {
2069 if (sc->bge_rdata->bge_status_block.bge_status &
2070 BGE_STATFLAG_LINKSTATE_CHANGED) {
2071 sc->bge_link = 0;
2072 untimeout(bge_tick, sc, sc->bge_stat_ch);
2073 bge_tick(sc);
2074 /* Clear the interrupt */
2075 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2076 BGE_MACSTAT_CFG_CHANGED);
2077 }
2078 }
2079
2080 if (ifp->if_flags & IFF_RUNNING) {
2081 /* Check RX return ring producer/consumer */
2082 bge_rxeof(sc);
2083
2084 /* Check TX ring producer/consumer */
2085 bge_txeof(sc);
2086 }
2087
2088 bge_handle_events(sc);
2089
2090 /* Re-enable interrupts. */
2091 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2092
2093 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
2094 bge_start(ifp);
2095
2096 return;
2097}
2098
2099static void
2100bge_tick(xsc)
2101 void *xsc;
2102{
2103 struct bge_softc *sc;
2104 struct mii_data *mii = NULL;
2105 struct ifmedia *ifm = NULL;
2106 struct ifnet *ifp;
2107 int s;
2108
2109 sc = xsc;
2110 ifp = &sc->arpcom.ac_if;
2111
2112 s = splimp();
2113
2114 bge_stats_update(sc);
2115 sc->bge_stat_ch = timeout(bge_tick, sc, hz);
2116 if (sc->bge_link) {
2117 splx(s);
2118 return;
2119 }
2120
2121 if (sc->bge_tbi) {
2122 ifm = &sc->bge_ifmedia;
2123 if (CSR_READ_4(sc, BGE_MAC_STS) &
2124 BGE_MACSTAT_TBI_PCS_SYNCHED) {
2125 sc->bge_link++;
2126 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2127 printf("bge%d: gigabit link up\n", sc->bge_unit);
2128 if (ifp->if_snd.ifq_head != NULL)
2129 bge_start(ifp);
2130 }
2131 splx(s);
2132 return;
2133 }
2134
2135 mii = device_get_softc(sc->bge_miibus);
2136 mii_tick(mii);
2137
2138 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE &&
2139 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2140 sc->bge_link++;
2141 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
2142 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2143 printf("bge%d: gigabit link up\n",
2144 sc->bge_unit);
2145 if (ifp->if_snd.ifq_head != NULL)
2146 bge_start(ifp);
2147 }
2148
2149 splx(s);
2150
2151 return;
2152}
2153
2154static void
2155bge_stats_update(sc)
2156 struct bge_softc *sc;
2157{
2158 struct ifnet *ifp;
2159 struct bge_stats *stats;
2160
2161 ifp = &sc->arpcom.ac_if;
2162
2163 stats = (struct bge_stats *)(sc->bge_vhandle +
2164 BGE_MEMWIN_START + BGE_STATS_BLOCK);
2165
2166 ifp->if_collisions +=
2167 (stats->dot3StatsSingleCollisionFrames.bge_addr_lo +
2168 stats->dot3StatsMultipleCollisionFrames.bge_addr_lo +
2169 stats->dot3StatsExcessiveCollisions.bge_addr_lo +
2170 stats->dot3StatsLateCollisions.bge_addr_lo) -
2171 ifp->if_collisions;
2172
2173#ifdef notdef
2174 ifp->if_collisions +=
2175 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2176 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2177 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2178 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2179 ifp->if_collisions;
2180#endif
2181
2182 return;
2183}
2184
2185/*
2186 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2187 * pointers to descriptors.
2188 */
2189static int
2190bge_encap(sc, m_head, txidx)
2191 struct bge_softc *sc;
2192 struct mbuf *m_head;
2193 u_int32_t *txidx;
2194{
2195 struct bge_tx_bd *f = NULL;
2196 struct mbuf *m;
2197 u_int32_t frag, cur, cnt = 0;
2198 u_int16_t csum_flags = 0;
2199 struct ifvlan *ifv = NULL;
2200
2201 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2202 m_head->m_pkthdr.rcvif != NULL &&
2203 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2204 ifv = m_head->m_pkthdr.rcvif->if_softc;
2205
2206 m = m_head;
2207 cur = frag = *txidx;
2208
2209 if (m_head->m_pkthdr.csum_flags) {
2210 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2211 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2212 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2213 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2214 if (m_head->m_flags & M_LASTFRAG)
2215 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2216 else if (m_head->m_flags & M_FRAG)
2217 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2218 }
2219
2220 /*
2221 * Start packing the mbufs in this chain into
2222 * the fragment pointers. Stop when we run out
2223 * of fragments or hit the end of the mbuf chain.
2224 */
2225 for (m = m_head; m != NULL; m = m->m_next) {
2226 if (m->m_len != 0) {
2227 f = &sc->bge_rdata->bge_tx_ring[frag];
2228 if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2229 break;
2230 BGE_HOSTADDR(f->bge_addr) =
2231 vtophys(mtod(m, vm_offset_t));
2232 f->bge_len = m->m_len;
2233 f->bge_flags = csum_flags;
2234 if (ifv != NULL) {
2235 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2236 f->bge_vlan_tag = ifv->ifv_tag;
2237 } else {
2238 f->bge_vlan_tag = 0;
2239 }
2240 /*
2241 * Sanity check: avoid coming within 16 descriptors
2242 * of the end of the ring.
2243 */
2244 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2245 return(ENOBUFS);
2246 cur = frag;
2247 BGE_INC(frag, BGE_TX_RING_CNT);
2248 cnt++;
2249 }
2250 }
2251
2252 if (m != NULL)
2253 return(ENOBUFS);
2254
2255 if (frag == sc->bge_tx_saved_considx)
2256 return(ENOBUFS);
2257
2258 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2259 sc->bge_cdata.bge_tx_chain[cur] = m_head;
2260 sc->bge_txcnt += cnt;
2261
2262 *txidx = frag;
2263
2264 return(0);
2265}
2266
2267/*
2268 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2269 * to the mbuf data regions directly in the transmit descriptors.
2270 */
2271static void
2272bge_start(ifp)
2273 struct ifnet *ifp;
2274{
2275 struct bge_softc *sc;
2276 struct mbuf *m_head = NULL;
2277 u_int32_t prodidx = 0;
2278
2279 sc = ifp->if_softc;
2280
2281 if (!sc->bge_link && ifp->if_snd.ifq_len < 10)
2282 return;
2283
2284 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2285
2286 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2287 IF_DEQUEUE(&ifp->if_snd, m_head);
2288 if (m_head == NULL)
2289 break;
2290
2291 /*
2292 * XXX
2293 * safety overkill. If this is a fragmented packet chain
2294 * with delayed TCP/UDP checksums, then only encapsulate
2295 * it if we have enough descriptors to handle the entire
2296 * chain at once.
2297 * (paranoia -- may not actually be needed)
2298 */
2299 if (m_head->m_flags & M_FIRSTFRAG &&
2300 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2301 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2302 m_head->m_pkthdr.csum_data + 16) {
2303 IF_PREPEND(&ifp->if_snd, m_head);
2304 ifp->if_flags |= IFF_OACTIVE;
2305 break;
2306 }
2307 }
2308
2309 /*
2310 * Pack the data into the transmit ring. If we
2311 * don't have room, set the OACTIVE flag and wait
2312 * for the NIC to drain the ring.
2313 */
2314 if (bge_encap(sc, m_head, &prodidx)) {
2315 IF_PREPEND(&ifp->if_snd, m_head);
2316 ifp->if_flags |= IFF_OACTIVE;
2317 break;
2318 }
2319
2320 /*
2321 * If there's a BPF listener, bounce a copy of this frame
2322 * to him.
2323 */
2324 if (ifp->if_bpf)
2325 bpf_mtap(ifp, m_head);
2326 }
2327
2328 /* Transmit */
2329 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2330
2331 /*
2332 * Set a timeout in case the chip goes out to lunch.
2333 */
2334 ifp->if_timer = 5;
2335
2336 return;
2337}
2338
2339/*
2340 * If we have a BCM5400 or BCM5401 PHY, we need to properly
2341 * program its internal DSP. Failing to do this can result in
2342 * massive packet loss at 1Gb speeds.
2343 */
2344static void
2345bge_phy_hack(sc)
2346 struct bge_softc *sc;
2347{
2348 struct bge_bcom_hack bhack[] = {
2349 { BRGPHY_MII_AUXCTL, 0x4C20 },
2350 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
2351 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
2352 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
2353 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
2354 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
2355 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
2356 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
2357 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
2358 { BRGPHY_MII_DSP_ADDR_REG, 0x201F },
2359 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 },
2360 { 0, 0 } };
2361 u_int16_t vid, did;
2362 int i;
2363
2364 vid = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR1);
2365 did = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR2);
2366
2367 if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM &&
2368 (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 ||
2369 MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) {
2370 i = 0;
2371 while(bhack[i].reg) {
2372 bge_miibus_writereg(sc->bge_dev, 1, bhack[i].reg,
2373 bhack[i].val);
2374 i++;
2375 }
2376 }
2377
2378 return;
2379}
2380
2381static void
2382bge_init(xsc)
2383 void *xsc;
2384{
2385 struct bge_softc *sc = xsc;
2386 struct ifnet *ifp;
2387 u_int16_t *m;
2388 int s;
2389
2390 s = splimp();
2391
2392 ifp = &sc->arpcom.ac_if;
2393
2394 if (ifp->if_flags & IFF_RUNNING) {
2395 splx(s);
2396 return;
2397 }
2398
2399 /* Cancel pending I/O and flush buffers. */
2400 bge_stop(sc);
2401 bge_reset(sc);
2402 bge_chipinit(sc);
2403
2404 /*
2405 * Init the various state machines, ring
2406 * control blocks and firmware.
2407 */
2408 if (bge_blockinit(sc)) {
2409 printf("bge%d: initialization failure\n", sc->bge_unit);
2410 splx(s);
2411 return;
2412 }
2413
2414 ifp = &sc->arpcom.ac_if;
2415
2416 /* Specify MTU. */
2417 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2418 ETHER_HDR_LEN + ETHER_CRC_LEN);
2419
2420 /* Load our MAC address. */
2421 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2422 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2423 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2424
2425 /* Enable or disable promiscuous mode as needed. */
2426 if (ifp->if_flags & IFF_PROMISC) {
2427 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2428 } else {
2429 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2430 }
2431
2432 /* Program multicast filter. */
2433 bge_setmulti(sc);
2434
2435 /* Init RX ring. */
2436 bge_init_rx_ring_std(sc);
2437
2438 /* Init jumbo RX ring. */
2439 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2440 bge_init_rx_ring_jumbo(sc);
2441
2442 /* Init our RX return ring index */
2443 sc->bge_rx_saved_considx = 0;
2444
2445 /* Init TX ring. */
2446 bge_init_tx_ring(sc);
2447
2448 /* Turn on transmitter */
2449 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2450
2451 /* Turn on receiver */
2452 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2453
2454 /* Tell firmware we're alive. */
2455 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2456
2457 /* Enable host interrupts. */
2458 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2459 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2460 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2461
2462 bge_ifmedia_upd(ifp);
2463
2464 ifp->if_flags |= IFF_RUNNING;
2465 ifp->if_flags &= ~IFF_OACTIVE;
2466
2467 splx(s);
2468
2469 sc->bge_stat_ch = timeout(bge_tick, sc, hz);
2470
2471 return;
2472}
2473
2474/*
2475 * Set media options.
2476 */
2477static int
2478bge_ifmedia_upd(ifp)
2479 struct ifnet *ifp;
2480{
2481 struct bge_softc *sc;
2482 struct mii_data *mii;
2483 struct ifmedia *ifm;
2484
2485 sc = ifp->if_softc;
2486 ifm = &sc->bge_ifmedia;
2487
2488 /* If this is a 1000baseX NIC, enable the TBI port. */
2489 if (sc->bge_tbi) {
2490 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2491 return(EINVAL);
2492 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2493 case IFM_AUTO:
2494 break;
2495 case IFM_1000_SX:
2496 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2497 BGE_CLRBIT(sc, BGE_MAC_MODE,
2498 BGE_MACMODE_HALF_DUPLEX);
2499 } else {
2500 BGE_SETBIT(sc, BGE_MAC_MODE,
2501 BGE_MACMODE_HALF_DUPLEX);
2502 }
2503 break;
2504 default:
2505 return(EINVAL);
2506 }
2507 return(0);
2508 }
2509
2510 mii = device_get_softc(sc->bge_miibus);
2511 sc->bge_link = 0;
2512 if (mii->mii_instance) {
2513 struct mii_softc *miisc;
2514 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
2515 miisc = LIST_NEXT(miisc, mii_list))
2516 mii_phy_reset(miisc);
2517 }
2518 bge_phy_hack(sc);
2519 mii_mediachg(mii);
2520
2521 return(0);
2522}
2523
2524/*
2525 * Report current media status.
2526 */
2527static void
2528bge_ifmedia_sts(ifp, ifmr)
2529 struct ifnet *ifp;
2530 struct ifmediareq *ifmr;
2531{
2532 struct bge_softc *sc;
2533 struct mii_data *mii;
2534
2535 sc = ifp->if_softc;
2536
2537 if (sc->bge_tbi) {
2538 ifmr->ifm_status = IFM_AVALID;
2539 ifmr->ifm_active = IFM_ETHER;
2540 if (CSR_READ_4(sc, BGE_MAC_STS) &
2541 BGE_MACSTAT_TBI_PCS_SYNCHED)
2542 ifmr->ifm_status |= IFM_ACTIVE;
2543 ifmr->ifm_active |= IFM_1000_SX;
2544 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2545 ifmr->ifm_active |= IFM_HDX;
2546 else
2547 ifmr->ifm_active |= IFM_FDX;
2548 return;
2549 }
2550
2551 mii = device_get_softc(sc->bge_miibus);
2552 mii_pollstat(mii);
2553 ifmr->ifm_active = mii->mii_media_active;
2554 ifmr->ifm_status = mii->mii_media_status;
2555
2556 return;
2557}
2558
2559static int
2560bge_ioctl(ifp, command, data)
2561 struct ifnet *ifp;
2562 u_long command;
2563 caddr_t data;
2564{
2565 struct bge_softc *sc = ifp->if_softc;
2566 struct ifreq *ifr = (struct ifreq *) data;
2567 int s, mask, error = 0;
2568 struct mii_data *mii;
2569
2570 s = splimp();
2571
2572 switch(command) {
2573 case SIOCSIFADDR:
2574 case SIOCGIFADDR:
2575 error = ether_ioctl(ifp, command, data);
2576 break;
2577 case SIOCSIFMTU:
2578 if (ifr->ifr_mtu > BGE_JUMBO_MTU)
2579 error = EINVAL;
2580 else {
2581 ifp->if_mtu = ifr->ifr_mtu;
2582 ifp->if_flags &= ~IFF_RUNNING;
2583 bge_init(sc);
2584 }
2585 break;
2586 case SIOCSIFFLAGS:
2587 if (ifp->if_flags & IFF_UP) {
2588 /*
2589 * If only the state of the PROMISC flag changed,
2590 * then just use the 'set promisc mode' command
2591 * instead of reinitializing the entire NIC. Doing
2592 * a full re-init means reloading the firmware and
2593 * waiting for it to start up, which may take a
2594 * second or two.
2595 */
2596 if (ifp->if_flags & IFF_RUNNING &&
2597 ifp->if_flags & IFF_PROMISC &&
2598 !(sc->bge_if_flags & IFF_PROMISC)) {
2599 BGE_SETBIT(sc, BGE_RX_MODE,
2600 BGE_RXMODE_RX_PROMISC);
2601 } else if (ifp->if_flags & IFF_RUNNING &&
2602 !(ifp->if_flags & IFF_PROMISC) &&
2603 sc->bge_if_flags & IFF_PROMISC) {
2604 BGE_CLRBIT(sc, BGE_RX_MODE,
2605 BGE_RXMODE_RX_PROMISC);
2606 } else
2607 bge_init(sc);
2608 } else {
2609 if (ifp->if_flags & IFF_RUNNING) {
2610 bge_stop(sc);
2611 }
2612 }
2613 sc->bge_if_flags = ifp->if_flags;
2614 error = 0;
2615 break;
2616 case SIOCADDMULTI:
2617 case SIOCDELMULTI:
2618 if (ifp->if_flags & IFF_RUNNING) {
2619 bge_setmulti(sc);
2620 error = 0;
2621 }
2622 break;
2623 case SIOCSIFMEDIA:
2624 case SIOCGIFMEDIA:
2625 if (sc->bge_tbi) {
2626 error = ifmedia_ioctl(ifp, ifr,
2627 &sc->bge_ifmedia, command);
2628 } else {
2629 mii = device_get_softc(sc->bge_miibus);
2630 error = ifmedia_ioctl(ifp, ifr,
2631 &mii->mii_media, command);
2632 }
2633 break;
2634 case SIOCSIFCAP:
2635 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2636 if (mask & IFCAP_HWCSUM) {
2637 if (IFCAP_HWCSUM & ifp->if_capenable)
2638 ifp->if_capenable &= ~IFCAP_HWCSUM;
2639 else
2640 ifp->if_capenable |= IFCAP_HWCSUM;
2641 }
2642 error = 0;
2643 break;
2644 default:
2645 error = EINVAL;
2646 break;
2647 }
2648
2649 (void)splx(s);
2650
2651 return(error);
2652}
2653
2654static void
2655bge_watchdog(ifp)
2656 struct ifnet *ifp;
2657{
2658 struct bge_softc *sc;
2659
2660 sc = ifp->if_softc;
2661
2662 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit);
2663
2664 ifp->if_flags &= ~IFF_RUNNING;
2665 bge_init(sc);
2666
2667 ifp->if_oerrors++;
2668
2669 return;
2670}
2671
2672/*
2673 * Stop the adapter and free any mbufs allocated to the
2674 * RX and TX lists.
2675 */
2676static void
2677bge_stop(sc)
2678 struct bge_softc *sc;
2679{
2680 struct ifnet *ifp;
2681 struct ifmedia_entry *ifm;
2682 struct mii_data *mii = NULL;
2683 int mtmp, itmp;
2684
2685 ifp = &sc->arpcom.ac_if;
2686
2687 if (!sc->bge_tbi)
2688 mii = device_get_softc(sc->bge_miibus);
2689
2690 untimeout(bge_tick, sc, sc->bge_stat_ch);
2691
2692 /*
2693 * Disable all of the receiver blocks
2694 */
2695 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2696 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2697 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2698 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2699 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
2700 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2701 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
2702
2703 /*
2704 * Disable all of the transmit blocks
2705 */
2706 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2707 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2708 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2709 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
2710 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
2711 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2712 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2713
2714 /*
2715 * Shut down all of the memory managers and related
2716 * state machines.
2717 */
2718 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
2719 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
2720 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2721 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2722 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2723 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
2724 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2725
2726 /* Disable host interrupts. */
2727 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2728 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2729
2730 /*
2731 * Tell firmware we're shutting down.
2732 */
2733 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2734
2735 /* Free the RX lists. */
2736 bge_free_rx_ring_std(sc);
2737
2738 /* Free jumbo RX list. */
2739 bge_free_rx_ring_jumbo(sc);
2740
2741 /* Free TX buffers. */
2742 bge_free_tx_ring(sc);
2743
2744 /*
2745 * Isolate/power down the PHY, but leave the media selection
2746 * unchanged so that things will be put back to normal when
2747 * we bring the interface back up.
2748 */
2749 if (!sc->bge_tbi) {
2750 itmp = ifp->if_flags;
2751 ifp->if_flags |= IFF_UP;
2752 ifm = mii->mii_media.ifm_cur;
2753 mtmp = ifm->ifm_media;
2754 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2755 mii_mediachg(mii);
2756 ifm->ifm_media = mtmp;
2757 ifp->if_flags = itmp;
2758 }
2759
2760 sc->bge_link = 0;
2761
2762 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
2763
2764 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2765
2766 return;
2767}
2768
2769/*
2770 * Stop all chip I/O so that the kernel's probe routines don't
2771 * get confused by errant DMAs when rebooting.
2772 */
2773static void
2774bge_shutdown(dev)
2775 device_t dev;
2776{
2777 struct bge_softc *sc;
2778
2779 sc = device_get_softc(dev);
2780
2781 bge_stop(sc);
2782 bge_reset(sc);
2783
2784 return;
2785}
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