| if_athvar.h (190096) | if_athvar.h (190571) |
|---|---|
| 1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 12 unchanged lines hidden (view full) --- 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * | 1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 12 unchanged lines hidden (view full) --- 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * |
| 29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 190096 2009-03-19 19:29:10Z sam $ | 29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 190571 2009-03-30 19:23:49Z sam $ |
| 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 --- 302 unchanged lines hidden (view full) --- 340 int sc_slotupdate; /* slot to advance fsm */ 341 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 342 int sc_nbcnvaps; /* # vaps with beacons */ 343 344 struct callout sc_cal_ch; /* callout handle for cals */ 345 int sc_lastlongcal; /* last long cal completed */ 346 int sc_lastcalreset;/* last cal reset done */ 347 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ | 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 --- 302 unchanged lines hidden (view full) --- 340 int sc_slotupdate; /* slot to advance fsm */ 341 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 342 int sc_nbcnvaps; /* # vaps with beacons */ 343 344 struct callout sc_cal_ch; /* callout handle for cals */ 345 int sc_lastlongcal; /* last long cal completed */ 346 int sc_lastcalreset;/* last cal reset done */ 347 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ |
| 348#ifdef ATH_SUPPORT_TDMA | |
| 349 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 350 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 351 u_int sc_tdmaswba; /* TDMA SWBA counter */ 352 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 353 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 354 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 355 u_int sc_tdmabintcnt; /* TDMA beacon intvl (slots) */ 356 struct ath_rx_status *sc_tdmars; /* TDMA status of last rx */ 357 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 358 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ | 348 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 349 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 350 u_int sc_tdmaswba; /* TDMA SWBA counter */ 351 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 352 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 353 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 354 u_int sc_tdmabintcnt; /* TDMA beacon intvl (slots) */ 355 struct ath_rx_status *sc_tdmars; /* TDMA status of last rx */ 356 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 357 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ |
| 359#endif | |
| 360}; 361 362#define ATH_LOCK_INIT(_sc) \ 363 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 364 NULL, MTX_DEF | MTX_RECURSE) 365#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 366#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 367#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) --- 309 unchanged lines hidden --- | 358}; 359 360#define ATH_LOCK_INIT(_sc) \ 361 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 362 NULL, MTX_DEF | MTX_RECURSE) 363#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 364#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 365#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) --- 309 unchanged lines hidden --- |