| ar5416_reset.c (221535) | ar5416_reset.c (221574) |
|---|---|
| 1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * | 1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * |
| 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c 221535 2011-05-06 15:33:56Z adrian $ | 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c 221574 2011-05-07 02:59:24Z adrian $ |
| 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" --- 1434 unchanged lines hidden (view full) --- 1460 * XXX make sure that the reg chain swapping is only done for 1461 * XXX AR5416 v2.0 or greater, and not later chips? 1462 */ 1463int 1464ar5416GetRegChainOffset(struct ath_hal *ah, int i) 1465{ 1466 int regChainOffset; 1467 | 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" --- 1434 unchanged lines hidden (view full) --- 1460 * XXX make sure that the reg chain swapping is only done for 1461 * XXX AR5416 v2.0 or greater, and not later chips? 1462 */ 1463int 1464ar5416GetRegChainOffset(struct ath_hal *ah, int i) 1465{ 1466 int regChainOffset; 1467 |
| 1468 if (AR_SREV_OWL_20_OR_LATER(ah) && | 1468 if (AR_SREV_5416_V20_OR_LATER(ah) && |
| 1469 (AH5416(ah)->ah_rx_chainmask == 0x5 || 1470 AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) { 1471 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 1472 * only chains 0 and 2 populated 1473 */ 1474 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1475 } else { 1476 regChainOffset = i * 0x1000; --- 36 unchanged lines hidden (view full) --- 1513 SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 1514 SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 1515 1516 /* 1517 * Large signal upgrade. 1518 * XXX update 1519 */ 1520 | 1469 (AH5416(ah)->ah_rx_chainmask == 0x5 || 1470 AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) { 1471 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 1472 * only chains 0 and 2 populated 1473 */ 1474 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1475 } else { 1476 regChainOffset = i * 0x1000; --- 36 unchanged lines hidden (view full) --- 1513 SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 1514 SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 1515 1516 /* 1517 * Large signal upgrade. 1518 * XXX update 1519 */ 1520 |
| 1521 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) | 1521 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) |
| 1522 ar5416SetDefGainValues(ah, pModal, eep, txRxAttenLocal, regChainOffset, i); 1523 1524 } 1525 1526 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 1527 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1528 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_OB, pModal->ob); 1529 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_DB, pModal->db); --- 682 unchanged lines hidden (view full) --- 2212 2213 /* Fetch the gain boundaries and the PDADC values */ 2214 ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 2215 pCalBChans, numPiers, 2216 pdGainOverlap_t2, 2217 &tMinCalPower, gainBoundaries, 2218 pdadcValues, numXpdGain); 2219 | 1522 ar5416SetDefGainValues(ah, pModal, eep, txRxAttenLocal, regChainOffset, i); 1523 1524 } 1525 1526 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 1527 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1528 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_OB, pModal->ob); 1529 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_DB, pModal->db); --- 682 unchanged lines hidden (view full) --- 2212 2213 /* Fetch the gain boundaries and the PDADC values */ 2214 ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 2215 pCalBChans, numPiers, 2216 pdGainOverlap_t2, 2217 &tMinCalPower, gainBoundaries, 2218 pdadcValues, numXpdGain); 2219 |
| 2220 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) { | 2220 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { |
| 2221 ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, 2222 gainBoundaries); 2223 } 2224 2225 /* Write the power values into the baseband power table */ 2226 ar5416WritePdadcValues(ah, i, pdadcValues); 2227 } 2228 } --- 95 unchanged lines hidden (view full) --- 2324 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 2325 } else { 2326 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 2327 } 2328 2329 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 2330 2331 /* NB: only applies to owl 1.0 */ | 2221 ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, 2222 gainBoundaries); 2223 } 2224 2225 /* Write the power values into the baseband power table */ 2226 ar5416WritePdadcValues(ah, i, pdadcValues); 2227 } 2228 } --- 95 unchanged lines hidden (view full) --- 2324 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 2325 } else { 2326 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 2327 } 2328 2329 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 2330 2331 /* NB: only applies to owl 1.0 */ |
| 2332 if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) { | 2332 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah) ) { |
| 2333 /* 2334 * fix the gain delta, but get a delta that can be applied to min to 2335 * keep the upper power values accurate, don't think max needs to 2336 * be adjusted because should not be at that area of the table? 2337 */ 2338 minDelta = pPdGainBoundaries[0] - 23; 2339 pPdGainBoundaries[0] = 23; 2340 } --- 155 unchanged lines hidden (view full) --- 2496 2497 if (AR_SREV_9287_11_OR_LATER(ah)) 2498 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 2499 2500 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 2501 } 2502 2503 /* | 2333 /* 2334 * fix the gain delta, but get a delta that can be applied to min to 2335 * keep the upper power values accurate, don't think max needs to 2336 * be adjusted because should not be at that area of the table? 2337 */ 2338 minDelta = pPdGainBoundaries[0] - 23; 2339 pPdGainBoundaries[0] = 23; 2340 } --- 155 unchanged lines hidden (view full) --- 2496 2497 if (AR_SREV_9287_11_OR_LATER(ah)) 2498 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 2499 2500 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 2501 } 2502 2503 /* |
| 2504 * The AR5416 initvals have this already set to 0x11; AR9160 has 2505 * the register set to 0x0. Figure out whether AR9130/AR9160 needs 2506 * this before moving forward with it. 2507 */ 2508#if 0 2509 /* Disable BB clock gating for AR5416v2, AR9130, AR9160 */ 2510 if (AR_SREV_OWL_20_OR_LATER(ah) || AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) { 2511 /* 2512 * Disable BB clock gating 2513 * Necessary to avoid issues on AR5416 2.0 2514 */ 2515 OS_REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 2516 } 2517#endif 2518 2519 /* | |
| 2520 * Disable RIFS search on some chips to avoid baseband 2521 * hang issues. 2522 */ 2523 if (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) 2524 (void) ar5416SetRifsDelay(ah, AH_FALSE); | 2504 * Disable RIFS search on some chips to avoid baseband 2505 * hang issues. 2506 */ 2507 if (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) 2508 (void) ar5416SetRifsDelay(ah, AH_FALSE); |
| 2509 2510 if (!AR_SREV_5416_V20_OR_LATER(ah) || AR_SREV_MERLIN(ah)) 2511 return; 2512 2513 /* 2514 * Disable BB clock gating 2515 * Necessary to avoid issues on AR5416 2.0 2516 */ 2517 OS_REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); |
|
| 2525} 2526 2527struct ini { 2528 uint32_t *data; /* NB: !const */ 2529 int rows, cols; 2530}; 2531 2532/* --- 71 unchanged lines hidden --- | 2518} 2519 2520struct ini { 2521 uint32_t *data; /* NB: !const */ 2522 int rows, cols; 2523}; 2524 2525/* --- 71 unchanged lines hidden --- |