| ar5212reg.h (192399) | ar5212reg.h (192400) |
|---|---|
| 1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * | 1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * |
| 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212reg.h 192399 2009-05-19 17:43:31Z sam $ | 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212reg.h 192400 2009-05-19 17:53:53Z sam $ |
| 18 */ 19#ifndef _DEV_ATH_AR5212REG_H_ 20#define _DEV_ATH_AR5212REG_H_ 21 22/* 23 * Definitions for the Atheros 5212 chipset. 24 */ 25 --- 432 unchanged lines hidden (view full) --- 458#define AR_ISR_S2_SSERR 0x00020000 /* SERR interrupt */ 459#define AR_ISR_S2_DPERR 0x00040000 /* PCI bus parity error */ 460#define AR_ISR_S2_TIM 0x01000000 /* TIM */ 461#define AR_ISR_S2_CABEND 0x02000000 /* CABEND */ 462#define AR_ISR_S2_DTIMSYNC 0x04000000 /* DTIMSYNC */ 463#define AR_ISR_S2_BCNTO 0x08000000 /* BCNTO */ 464#define AR_ISR_S2_CABTO 0x10000000 /* CABTO */ 465#define AR_ISR_S2_DTIM 0x20000000 /* DTIM */ | 18 */ 19#ifndef _DEV_ATH_AR5212REG_H_ 20#define _DEV_ATH_AR5212REG_H_ 21 22/* 23 * Definitions for the Atheros 5212 chipset. 24 */ 25 --- 432 unchanged lines hidden (view full) --- 458#define AR_ISR_S2_SSERR 0x00020000 /* SERR interrupt */ 459#define AR_ISR_S2_DPERR 0x00040000 /* PCI bus parity error */ 460#define AR_ISR_S2_TIM 0x01000000 /* TIM */ 461#define AR_ISR_S2_CABEND 0x02000000 /* CABEND */ 462#define AR_ISR_S2_DTIMSYNC 0x04000000 /* DTIMSYNC */ 463#define AR_ISR_S2_BCNTO 0x08000000 /* BCNTO */ 464#define AR_ISR_S2_CABTO 0x10000000 /* CABTO */ 465#define AR_ISR_S2_DTIM 0x20000000 /* DTIM */ |
| 466#define AR_ISR_S2_RESV0 0xE0F8FC00 /* Reserved */ | 466#define AR_ISR_S2_TSFOOR 0x40000000 /* TSF OOR */ 467#define AR_ISR_S2_TBTT 0x80000000 /* TBTT timer */ |
| 467 468#define AR_ISR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ 469#define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ 470 471#define AR_ISR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */ 472#define AR_ISR_S4_RESV0 0xFFFFFC00 /* Reserved */ 473 474/* --- 51 unchanged lines hidden (view full) --- 526#define AR_IMR_S2_SSERR 0x00020000 /* SERR interrupt */ 527#define AR_IMR_S2_DPERR 0x00040000 /* PCI bus parity error */ 528#define AR_IMR_S2_TIM 0x01000000 /* TIM */ 529#define AR_IMR_S2_CABEND 0x02000000 /* CABEND */ 530#define AR_IMR_S2_DTIMSYNC 0x04000000 /* DTIMSYNC */ 531#define AR_IMR_S2_BCNTO 0x08000000 /* BCNTO */ 532#define AR_IMR_S2_CABTO 0x10000000 /* CABTO */ 533#define AR_IMR_S2_DTIM 0x20000000 /* DTIM */ | 468 469#define AR_ISR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ 470#define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ 471 472#define AR_ISR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */ 473#define AR_ISR_S4_RESV0 0xFFFFFC00 /* Reserved */ 474 475/* --- 51 unchanged lines hidden (view full) --- 527#define AR_IMR_S2_SSERR 0x00020000 /* SERR interrupt */ 528#define AR_IMR_S2_DPERR 0x00040000 /* PCI bus parity error */ 529#define AR_IMR_S2_TIM 0x01000000 /* TIM */ 530#define AR_IMR_S2_CABEND 0x02000000 /* CABEND */ 531#define AR_IMR_S2_DTIMSYNC 0x04000000 /* DTIMSYNC */ 532#define AR_IMR_S2_BCNTO 0x08000000 /* BCNTO */ 533#define AR_IMR_S2_CABTO 0x10000000 /* CABTO */ 534#define AR_IMR_S2_DTIM 0x20000000 /* DTIM */ |
| 534#define AR_IMR_S2_TSFOOR 0x80000000 /* TSF OOR */ 535#define AR_IMR_S2_RESV0 0xE0F8FC00 /* Reserved */ | 535#define AR_IMR_S2_TSFOOR 0x40000000 /* TSF OOR */ 536#define AR_IMR_S2_TBTT 0x80000000 /* TBTT timer */ |
| 536 537/* AR_IMR_SR2 bits that correspond to AR_IMR_BCNMISC */ 538#define AR_IMR_SR2_BCNMISC \ 539 (AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | \ | 537 538/* AR_IMR_SR2 bits that correspond to AR_IMR_BCNMISC */ 539#define AR_IMR_SR2_BCNMISC \ 540 (AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | \ |
| 540 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR) | 541 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR | \ 542 AR_IMR_S2_TBTT) |
| 541 542#define AR_IMR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ 543#define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ 544#define AR_IMR_S3_QCU_QCBRURN_S 16 /* Shift for QCBRURN (QCU 0-9) */ 545 546#define AR_IMR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */ 547#define AR_IMR_S4_RESV0 0xFFFFFC00 /* Reserved */ 548 --- 452 unchanged lines hidden --- | 543 544#define AR_IMR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ 545#define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ 546#define AR_IMR_S3_QCU_QCBRURN_S 16 /* Shift for QCBRURN (QCU 0-9) */ 547 548#define AR_IMR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */ 549#define AR_IMR_S4_RESV0 0xFFFFFC00 /* Reserved */ 550 --- 452 unchanged lines hidden --- |