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ar5212_interrupts.c (192397) ar5212_interrupts.c (192399)
1/*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
1/*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c 192397 2009-05-19 17:35:15Z sam $
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c 192399 2009-05-19 17:43:31Z sam $
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23
24#include "ar5212/ar5212.h"
25#include "ar5212/ar5212reg.h"

--- 24 unchanged lines hidden (view full) ---

50 *
51 * Returns: A hardware-abstracted bitmap of all non-masked-out
52 * interrupts pending, as well as an unmasked value
53 */
54HAL_BOOL
55ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
56{
57 uint32_t isr, isr0, isr1;
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23
24#include "ar5212/ar5212.h"
25#include "ar5212/ar5212reg.h"

--- 24 unchanged lines hidden (view full) ---

50 *
51 * Returns: A hardware-abstracted bitmap of all non-masked-out
52 * interrupts pending, as well as an unmasked value
53 */
54HAL_BOOL
55ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
56{
57 uint32_t isr, isr0, isr1;
58 uint32_t mask2=0;
58 uint32_t mask2;
59 struct ath_hal_5212 *ahp = AH5212(ah);
60
61 isr = OS_REG_READ(ah, AR_ISR);
59 struct ath_hal_5212 *ahp = AH5212(ah);
60
61 isr = OS_REG_READ(ah, AR_ISR);
62 mask2 = 0;
62 if (isr & AR_ISR_BCNMISC) {
63 if (isr & AR_ISR_BCNMISC) {
63 uint32_t isr2;
64 isr2 = OS_REG_READ(ah, AR_ISR_S2);
64 uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2);
65 if (isr2 & AR_ISR_S2_TIM)
66 mask2 |= HAL_INT_TIM;
67 if (isr2 & AR_ISR_S2_DTIM)
68 mask2 |= HAL_INT_DTIM;
69 if (isr2 & AR_ISR_S2_DTIMSYNC)
70 mask2 |= HAL_INT_DTIMSYNC;
65 if (isr2 & AR_ISR_S2_TIM)
66 mask2 |= HAL_INT_TIM;
67 if (isr2 & AR_ISR_S2_DTIM)
68 mask2 |= HAL_INT_DTIM;
69 if (isr2 & AR_ISR_S2_DTIMSYNC)
70 mask2 |= HAL_INT_DTIMSYNC;
71 if (isr2 & (AR_ISR_S2_CABEND ))
71 if (isr2 & AR_ISR_S2_CABEND)
72 mask2 |= HAL_INT_CABEND;
73 }
74 isr = OS_REG_READ(ah, AR_ISR_RAC);
75 if (isr == 0xffffffff) {
76 *masked = 0;
77 return AH_FALSE;;
78 }
79

--- 52 unchanged lines hidden (view full) ---

132 * Atomically enables NIC interrupts. Interrupts are passed in
133 * via the enumerated bitmask in ints.
134 */
135HAL_INT
136ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
137{
138 struct ath_hal_5212 *ahp = AH5212(ah);
139 uint32_t omask = ahp->ah_maskReg;
72 mask2 |= HAL_INT_CABEND;
73 }
74 isr = OS_REG_READ(ah, AR_ISR_RAC);
75 if (isr == 0xffffffff) {
76 *masked = 0;
77 return AH_FALSE;;
78 }
79

--- 52 unchanged lines hidden (view full) ---

132 * Atomically enables NIC interrupts. Interrupts are passed in
133 * via the enumerated bitmask in ints.
134 */
135HAL_INT
136ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
137{
138 struct ath_hal_5212 *ahp = AH5212(ah);
139 uint32_t omask = ahp->ah_maskReg;
140 uint32_t mask,mask2;
140 uint32_t mask, mask2;
141
142 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
143 __func__, omask, ints);
144
145 if (omask & HAL_INT_GLOBAL) {
146 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
147 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
148 (void) OS_REG_READ(ah, AR_IER); /* flush write to HW */

--- 17 unchanged lines hidden (view full) ---

166 mask |= AR_IMR_BCNMISC;
167 if (ints & HAL_INT_TIM)
168 mask2 |= AR_IMR_S2_TIM;
169 if (ints & HAL_INT_DTIM)
170 mask2 |= AR_IMR_S2_DTIM;
171 if (ints & HAL_INT_DTIMSYNC)
172 mask2 |= AR_IMR_S2_DTIMSYNC;
173 if (ints & HAL_INT_CABEND)
141
142 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
143 __func__, omask, ints);
144
145 if (omask & HAL_INT_GLOBAL) {
146 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
147 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
148 (void) OS_REG_READ(ah, AR_IER); /* flush write to HW */

--- 17 unchanged lines hidden (view full) ---

166 mask |= AR_IMR_BCNMISC;
167 if (ints & HAL_INT_TIM)
168 mask2 |= AR_IMR_S2_TIM;
169 if (ints & HAL_INT_DTIM)
170 mask2 |= AR_IMR_S2_DTIM;
171 if (ints & HAL_INT_DTIMSYNC)
172 mask2 |= AR_IMR_S2_DTIMSYNC;
173 if (ints & HAL_INT_CABEND)
174 mask2 |= (AR_IMR_S2_CABEND );
174 mask2 |= AR_IMR_S2_CABEND;
175 }
176 if (ints & HAL_INT_FATAL) {
177 /*
178 * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2
179 * so enabling HIUERR enables delivery.
180 */
181 mask |= AR_IMR_HIUERR;
182 }
183
184 /* Write the new IMR and store off our SW copy. */
185 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
186 OS_REG_WRITE(ah, AR_IMR, mask);
175 }
176 if (ints & HAL_INT_FATAL) {
177 /*
178 * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2
179 * so enabling HIUERR enables delivery.
180 */
181 mask |= AR_IMR_HIUERR;
182 }
183
184 /* Write the new IMR and store off our SW copy. */
185 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
186 OS_REG_WRITE(ah, AR_IMR, mask);
187 OS_REG_WRITE(ah, AR_IMR_S2,
188 (OS_REG_READ(ah, AR_IMR_S2) &
189 ~(AR_IMR_S2_TIM |
190 AR_IMR_S2_DTIM |
191 AR_IMR_S2_DTIMSYNC |
192 AR_IMR_S2_CABEND |
193 AR_IMR_S2_CABTO |
194 AR_IMR_S2_TSFOOR ) )
195 | mask2);
187 OS_REG_WRITE(ah, AR_IMR_S2,
188 (OS_REG_READ(ah, AR_IMR_S2) &~ AR_IMR_SR2_BCNMISC) | mask2);
196 ahp->ah_maskReg = ints;
197
198 /* Re-enable interrupts if they were enabled before. */
199 if (ints & HAL_INT_GLOBAL) {
200 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
201 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
202 }
189 ahp->ah_maskReg = ints;
190
191 /* Re-enable interrupts if they were enabled before. */
192 if (ints & HAL_INT_GLOBAL) {
193 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
194 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
195 }
203
204
205 return omask;
206}
196 return omask;
197}