1/*
2 * Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org>
3 * Copyright (c) 2008 Sam Leffler, Errno Consulting
4 * Copyright (c) 2008 Atheros Communications, Inc.
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
| 1/*
2 * Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org>
3 * Copyright (c) 2008 Sam Leffler, Errno Consulting
4 * Copyright (c) 2008 Atheros Communications, Inc.
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
|
26#undef owl_eep_start_loc
27#ifdef __LINUX_ARM_ARCH__ /* AP71 */
28#define owl_eep_start_loc 0
29#else
30#define owl_eep_start_loc 64
31#endif
32
33// 16-bit offset location start of calibration struct
34#define AR5416_4K_EEP_START_LOC 64
35#define AR5416_4K_NUM_2G_CAL_PIERS 3
36#define AR5416_4K_NUM_2G_CCK_TARGET_POWERS 3
37#define AR5416_4K_NUM_2G_20_TARGET_POWERS 3
38#define AR5416_4K_NUM_2G_40_TARGET_POWERS 3
39#define AR5416_4K_NUM_CTLS 12
40#define AR5416_4K_NUM_BAND_EDGES 4
41#define AR5416_4K_NUM_PD_GAINS 2
42#define AR5416_4K_MAX_CHAINS 1
43
44/*
45 * NB: The format in EEPROM has words 0 and 2 swapped (i.e. version
46 * and length are swapped). We reverse their position after reading
47 * the data into host memory so the version field is at the same
48 * offset as in previous EEPROM layouts. This makes utilities that
49 * inspect the EEPROM contents work without looking at the PCI device
50 * id which may or may not be reliable.
51 */
52typedef struct BaseEepHeader4k {
53 uint16_t version; /* NB: length in EEPROM */
54 uint16_t checksum;
55 uint16_t length; /* NB: version in EEPROM */
56 uint8_t opCapFlags;
57 uint8_t eepMisc;
58 uint16_t regDmn[2];
59 uint8_t macAddr[6];
60 uint8_t rxMask;
61 uint8_t txMask;
62 uint16_t rfSilent;
63 uint16_t blueToothOptions;
64 uint16_t deviceCap;
65 uint32_t binBuildNumber;
66 uint8_t deviceType;
67 uint8_t txGainType; /* high power tx gain table support */
68} __packed BASE_EEP4K_HEADER; // 32 B
69
70typedef struct ModalEepHeader4k {
71 uint32_t antCtrlChain[AR5416_4K_MAX_CHAINS]; // 12
72 uint32_t antCtrlCommon; // 4
73 int8_t antennaGainCh[AR5416_4K_MAX_CHAINS]; // 1
74 uint8_t switchSettling; // 1
75 uint8_t txRxAttenCh[AR5416_4K_MAX_CHAINS]; // 1
76 uint8_t rxTxMarginCh[AR5416_4K_MAX_CHAINS]; // 1
77 uint8_t adcDesiredSize; // 1
78 int8_t pgaDesiredSize; // 1
79 uint8_t xlnaGainCh[AR5416_4K_MAX_CHAINS]; // 1
80 uint8_t txEndToXpaOff; // 1
81 uint8_t txEndToRxOn; // 1
82 uint8_t txFrameToXpaOn; // 1
83 uint8_t thresh62; // 1
84 uint8_t noiseFloorThreshCh[AR5416_4K_MAX_CHAINS]; // 1
85 uint8_t xpdGain; // 1
86 uint8_t xpd; // 1
87 int8_t iqCalICh[AR5416_4K_MAX_CHAINS]; // 1
88 int8_t iqCalQCh[AR5416_4K_MAX_CHAINS]; // 1
89 uint8_t pdGainOverlap; // 1
90 uint8_t ob; // 1
91 uint8_t db; // 1
92 uint8_t xpaBiasLvl; // 1
93#if 0
94 uint8_t pwrDecreaseFor2Chain; // 1
95 uint8_t pwrDecreaseFor3Chain; // 1 -> 48 B
96#endif
97 uint8_t txFrameToDataStart; // 1
98 uint8_t txFrameToPaOn; // 1
99 uint8_t ht40PowerIncForPdadc; // 1
100 uint8_t bswAtten[AR5416_4K_MAX_CHAINS]; // 1
101 uint8_t bswMargin[AR5416_4K_MAX_CHAINS]; // 1
102 uint8_t swSettleHt40; // 1
103 uint8_t xatten2Db[AR5416_4K_MAX_CHAINS]; // 1
104 uint8_t xatten2Margin[AR5416_4K_MAX_CHAINS]; // 1
105 uint8_t ob_ch1; // 1 -> ob and db become chain specific from AR9280
106 uint8_t db_ch1; // 1
107 uint8_t flagBits; // 1
108#define AR5416_EEP_FLAG_USEANT1 0x01 /* +1 configured antenna */
109#define AR5416_EEP_FLAG_FORCEXPAON 0x02 /* force XPA bit for 5G */
110#define AR5416_EEP_FLAG_LOCALBIAS 0x04 /* enable local bias */
111#define AR5416_EEP_FLAG_FEMBANDSELECT 0x08 /* FEM band select used */
112#define AR5416_EEP_FLAG_XLNABUFIN 0x10
113#define AR5416_EEP_FLAG_XLNAISEL 0x60
114#define AR5416_EEP_FLAG_XLNAISEL_S 5
115#define AR5416_EEP_FLAG_XLNABUFMODE 0x80
116 uint8_t miscBits; // [0..1]: bb_tx_dac_scale_cck
117 uint16_t xpaBiasLvlFreq[3]; // 6
118 uint8_t futureModal[2]; // 2
119
120 SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B
121} __packed MODAL_EEP4K_HEADER; // == 68 B
122
123typedef struct CalCtlData4k {
124 CAL_CTL_EDGES ctlEdges[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_BAND_EDGES];
125} __packed CAL_CTL_DATA_4K;
126
127typedef struct calDataPerFreq4k {
128 uint8_t pwrPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
129 uint8_t vpdPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
130} __packed CAL_DATA_PER_FREQ_4K;
131
132struct ar5416eeprom_4k {
133 BASE_EEP4K_HEADER baseEepHeader; // 32 B
134 uint8_t custData[20]; // 20 B
135 MODAL_EEP4K_HEADER modalHeader; // 68 B
136 uint8_t calFreqPier2G[AR5416_4K_NUM_2G_CAL_PIERS];
137 CAL_DATA_PER_FREQ_4K calPierData2G[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_2G_CAL_PIERS];
138 CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_4K_NUM_2G_CCK_TARGET_POWERS];
139 CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_4K_NUM_2G_20_TARGET_POWERS];
140 CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_4K_NUM_2G_20_TARGET_POWERS];
141 CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_4K_NUM_2G_40_TARGET_POWERS];
142 uint8_t ctlIndex[AR5416_4K_NUM_CTLS];
143 CAL_CTL_DATA_4K ctlData[AR5416_4K_NUM_CTLS];
144 uint8_t padding;
145} __packed;
146
147typedef struct {
148 struct ar5416eeprom_4k ee_base;
149#define NUM_EDGES 8
150 uint16_t ee_numCtls;
151 RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_4K_NUM_CTLS];
152 /* XXX these are dynamically calculated for use by shared code */
| 28#undef owl_eep_start_loc
29#ifdef __LINUX_ARM_ARCH__ /* AP71 */
30#define owl_eep_start_loc 0
31#else
32#define owl_eep_start_loc 64
33#endif
34
35// 16-bit offset location start of calibration struct
36#define AR5416_4K_EEP_START_LOC 64
37#define AR5416_4K_NUM_2G_CAL_PIERS 3
38#define AR5416_4K_NUM_2G_CCK_TARGET_POWERS 3
39#define AR5416_4K_NUM_2G_20_TARGET_POWERS 3
40#define AR5416_4K_NUM_2G_40_TARGET_POWERS 3
41#define AR5416_4K_NUM_CTLS 12
42#define AR5416_4K_NUM_BAND_EDGES 4
43#define AR5416_4K_NUM_PD_GAINS 2
44#define AR5416_4K_MAX_CHAINS 1
45
46/*
47 * NB: The format in EEPROM has words 0 and 2 swapped (i.e. version
48 * and length are swapped). We reverse their position after reading
49 * the data into host memory so the version field is at the same
50 * offset as in previous EEPROM layouts. This makes utilities that
51 * inspect the EEPROM contents work without looking at the PCI device
52 * id which may or may not be reliable.
53 */
54typedef struct BaseEepHeader4k {
55 uint16_t version; /* NB: length in EEPROM */
56 uint16_t checksum;
57 uint16_t length; /* NB: version in EEPROM */
58 uint8_t opCapFlags;
59 uint8_t eepMisc;
60 uint16_t regDmn[2];
61 uint8_t macAddr[6];
62 uint8_t rxMask;
63 uint8_t txMask;
64 uint16_t rfSilent;
65 uint16_t blueToothOptions;
66 uint16_t deviceCap;
67 uint32_t binBuildNumber;
68 uint8_t deviceType;
69 uint8_t txGainType; /* high power tx gain table support */
70} __packed BASE_EEP4K_HEADER; // 32 B
71
72typedef struct ModalEepHeader4k {
73 uint32_t antCtrlChain[AR5416_4K_MAX_CHAINS]; // 12
74 uint32_t antCtrlCommon; // 4
75 int8_t antennaGainCh[AR5416_4K_MAX_CHAINS]; // 1
76 uint8_t switchSettling; // 1
77 uint8_t txRxAttenCh[AR5416_4K_MAX_CHAINS]; // 1
78 uint8_t rxTxMarginCh[AR5416_4K_MAX_CHAINS]; // 1
79 uint8_t adcDesiredSize; // 1
80 int8_t pgaDesiredSize; // 1
81 uint8_t xlnaGainCh[AR5416_4K_MAX_CHAINS]; // 1
82 uint8_t txEndToXpaOff; // 1
83 uint8_t txEndToRxOn; // 1
84 uint8_t txFrameToXpaOn; // 1
85 uint8_t thresh62; // 1
86 uint8_t noiseFloorThreshCh[AR5416_4K_MAX_CHAINS]; // 1
87 uint8_t xpdGain; // 1
88 uint8_t xpd; // 1
89 int8_t iqCalICh[AR5416_4K_MAX_CHAINS]; // 1
90 int8_t iqCalQCh[AR5416_4K_MAX_CHAINS]; // 1
91 uint8_t pdGainOverlap; // 1
92 uint8_t ob; // 1
93 uint8_t db; // 1
94 uint8_t xpaBiasLvl; // 1
95#if 0
96 uint8_t pwrDecreaseFor2Chain; // 1
97 uint8_t pwrDecreaseFor3Chain; // 1 -> 48 B
98#endif
99 uint8_t txFrameToDataStart; // 1
100 uint8_t txFrameToPaOn; // 1
101 uint8_t ht40PowerIncForPdadc; // 1
102 uint8_t bswAtten[AR5416_4K_MAX_CHAINS]; // 1
103 uint8_t bswMargin[AR5416_4K_MAX_CHAINS]; // 1
104 uint8_t swSettleHt40; // 1
105 uint8_t xatten2Db[AR5416_4K_MAX_CHAINS]; // 1
106 uint8_t xatten2Margin[AR5416_4K_MAX_CHAINS]; // 1
107 uint8_t ob_ch1; // 1 -> ob and db become chain specific from AR9280
108 uint8_t db_ch1; // 1
109 uint8_t flagBits; // 1
110#define AR5416_EEP_FLAG_USEANT1 0x01 /* +1 configured antenna */
111#define AR5416_EEP_FLAG_FORCEXPAON 0x02 /* force XPA bit for 5G */
112#define AR5416_EEP_FLAG_LOCALBIAS 0x04 /* enable local bias */
113#define AR5416_EEP_FLAG_FEMBANDSELECT 0x08 /* FEM band select used */
114#define AR5416_EEP_FLAG_XLNABUFIN 0x10
115#define AR5416_EEP_FLAG_XLNAISEL 0x60
116#define AR5416_EEP_FLAG_XLNAISEL_S 5
117#define AR5416_EEP_FLAG_XLNABUFMODE 0x80
118 uint8_t miscBits; // [0..1]: bb_tx_dac_scale_cck
119 uint16_t xpaBiasLvlFreq[3]; // 6
120 uint8_t futureModal[2]; // 2
121
122 SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B
123} __packed MODAL_EEP4K_HEADER; // == 68 B
124
125typedef struct CalCtlData4k {
126 CAL_CTL_EDGES ctlEdges[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_BAND_EDGES];
127} __packed CAL_CTL_DATA_4K;
128
129typedef struct calDataPerFreq4k {
130 uint8_t pwrPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
131 uint8_t vpdPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
132} __packed CAL_DATA_PER_FREQ_4K;
133
134struct ar5416eeprom_4k {
135 BASE_EEP4K_HEADER baseEepHeader; // 32 B
136 uint8_t custData[20]; // 20 B
137 MODAL_EEP4K_HEADER modalHeader; // 68 B
138 uint8_t calFreqPier2G[AR5416_4K_NUM_2G_CAL_PIERS];
139 CAL_DATA_PER_FREQ_4K calPierData2G[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_2G_CAL_PIERS];
140 CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_4K_NUM_2G_CCK_TARGET_POWERS];
141 CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_4K_NUM_2G_20_TARGET_POWERS];
142 CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_4K_NUM_2G_20_TARGET_POWERS];
143 CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_4K_NUM_2G_40_TARGET_POWERS];
144 uint8_t ctlIndex[AR5416_4K_NUM_CTLS];
145 CAL_CTL_DATA_4K ctlData[AR5416_4K_NUM_CTLS];
146 uint8_t padding;
147} __packed;
148
149typedef struct {
150 struct ar5416eeprom_4k ee_base;
151#define NUM_EDGES 8
152 uint16_t ee_numCtls;
153 RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_4K_NUM_CTLS];
154 /* XXX these are dynamically calculated for use by shared code */
|