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ata-sis.c (230132) ata-sis.c (233282)
1/*-
2 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-sis.c 230132 2012-01-15 13:23:18Z uqs $");
28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-sis.c 233282 2012-03-21 16:59:39Z marius $");
29
30#include "opt_ata.h"
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/ata.h>
36#include <sys/bus.h>

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61#define SIS_33 1
62#define SIS_66 2
63#define SIS_100NEW 3
64#define SIS_100OLD 4
65#define SIS_133NEW 5
66#define SIS_133OLD 6
67#define SIS_SATA 7
68
29
30#include "opt_ata.h"
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/ata.h>
36#include <sys/bus.h>

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61#define SIS_33 1
62#define SIS_66 2
63#define SIS_100NEW 3
64#define SIS_100OLD 4
65#define SIS_133NEW 5
66#define SIS_133OLD 6
67#define SIS_SATA 7
68
69
70/*
71 * Silicon Integrated Systems Corp. (SiS) chipset support functions
72 */
73static int
74ata_sis_probe(device_t dev)
75{
76 struct ata_pci_controller *ctlr = device_get_softc(dev);
69/*
70 * Silicon Integrated Systems Corp. (SiS) chipset support functions
71 */
72static int
73ata_sis_probe(device_t dev)
74{
75 struct ata_pci_controller *ctlr = device_get_softc(dev);
77 struct ata_chip_id *idx;
78 static struct ata_chip_id ids[] =
76 const struct ata_chip_id *idx;
77 static const struct ata_chip_id const ids[] =
79 {{ ATA_SIS182, 0x00, SIS_SATA, 0, ATA_SA150, "182" }, /* south */
80 { ATA_SIS181, 0x00, SIS_SATA, 0, ATA_SA150, "181" }, /* south */
81 { ATA_SIS180, 0x00, SIS_SATA, 0, ATA_SA150, "180" }, /* south */
82 { ATA_SIS965, 0x00, SIS_133NEW, 0, ATA_UDMA6, "965" }, /* south */
83 { ATA_SIS964, 0x00, SIS_133NEW, 0, ATA_UDMA6, "964" }, /* south */
84 { ATA_SIS963, 0x00, SIS_133NEW, 0, ATA_UDMA6, "963" }, /* south */
85 { ATA_SIS962, 0x00, SIS_133NEW, 0, ATA_UDMA6, "962" }, /* south */
86

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97
98 { ATA_SIS550, 0x00, SIS_66, 0, ATA_UDMA5, "550" },
99 { ATA_SIS540, 0x00, SIS_66, 0, ATA_UDMA4, "540" },
100 { ATA_SIS530, 0x00, SIS_66, 0, ATA_UDMA4, "530" },
101
102 { ATA_SIS5513, 0xc2, SIS_33, 1, ATA_UDMA2, "5513" },
103 { ATA_SIS5513, 0x00, SIS_33, 1, ATA_WDMA2, "5513" },
104 { 0, 0, 0, 0, 0, 0 }};
78 {{ ATA_SIS182, 0x00, SIS_SATA, 0, ATA_SA150, "182" }, /* south */
79 { ATA_SIS181, 0x00, SIS_SATA, 0, ATA_SA150, "181" }, /* south */
80 { ATA_SIS180, 0x00, SIS_SATA, 0, ATA_SA150, "180" }, /* south */
81 { ATA_SIS965, 0x00, SIS_133NEW, 0, ATA_UDMA6, "965" }, /* south */
82 { ATA_SIS964, 0x00, SIS_133NEW, 0, ATA_UDMA6, "964" }, /* south */
83 { ATA_SIS963, 0x00, SIS_133NEW, 0, ATA_UDMA6, "963" }, /* south */
84 { ATA_SIS962, 0x00, SIS_133NEW, 0, ATA_UDMA6, "962" }, /* south */
85

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96
97 { ATA_SIS550, 0x00, SIS_66, 0, ATA_UDMA5, "550" },
98 { ATA_SIS540, 0x00, SIS_66, 0, ATA_UDMA4, "540" },
99 { ATA_SIS530, 0x00, SIS_66, 0, ATA_UDMA4, "530" },
100
101 { ATA_SIS5513, 0xc2, SIS_33, 1, ATA_UDMA2, "5513" },
102 { ATA_SIS5513, 0x00, SIS_33, 1, ATA_WDMA2, "5513" },
103 { 0, 0, 0, 0, 0, 0 }};
104 static struct ata_chip_id id[] =
105 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
105 char buffer[64];
106 int found = 0;
107
108 if (pci_get_class(dev) != PCIC_STORAGE)
109 return (ENXIO);
110
111 if (pci_get_vendor(dev) != ATA_SIS_ID)
112 return ENXIO;
113
114 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
115 return ENXIO;
116
106 char buffer[64];
107 int found = 0;
108
109 if (pci_get_class(dev) != PCIC_STORAGE)
110 return (ENXIO);
111
112 if (pci_get_vendor(dev) != ATA_SIS_ID)
113 return ENXIO;
114
115 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
116 return ENXIO;
117
117 if (idx->cfg2 && !found) {
118 if (idx->cfg2) {
118 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
119
120 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
121 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
122 found = 1;
119 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
120
121 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
122 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
123 found = 1;
123 idx->cfg1 = SIS_133NEW;
124 idx->max_dma = ATA_UDMA6;
124 memcpy(&id[0], idx, sizeof(id[0]));
125 id[0].cfg1 = SIS_133NEW;
126 id[0].max_dma = ATA_UDMA6;
125 sprintf(buffer, "SiS 962/963 %s controller",
126 ata_mode2str(idx->max_dma));
127 }
128 pci_write_config(dev, 0x57, reg57, 1);
129 }
130 if (idx->cfg2 && !found) {
131 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
132
133 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
134 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
127 sprintf(buffer, "SiS 962/963 %s controller",
128 ata_mode2str(idx->max_dma));
129 }
130 pci_write_config(dev, 0x57, reg57, 1);
131 }
132 if (idx->cfg2 && !found) {
133 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
134
135 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
136 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
135 struct ata_chip_id id[] =
136 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
137
138 found = 1;
139 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
137 found = 1;
138 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
140 idx->cfg1 = SIS_133OLD;
141 idx->max_dma = ATA_UDMA6;
139 id[0].cfg1 = SIS_133OLD;
140 id[0].max_dma = ATA_UDMA6;
141 } else {
142 id[0].cfg1 = SIS_100NEW;
143 id[0].max_dma = ATA_UDMA5;
142 }
144 }
143 else {
144 idx->cfg1 = SIS_100NEW;
145 idx->max_dma = ATA_UDMA5;
146 }
147 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
148 }
149 pci_write_config(dev, 0x4a, reg4a, 1);
150 }
151 if (!found)
152 sprintf(buffer,"SiS %s %s controller",
153 idx->text, ata_mode2str(idx->max_dma));
145 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
146 }
147 pci_write_config(dev, 0x4a, reg4a, 1);
148 }
149 if (!found)
150 sprintf(buffer,"SiS %s %s controller",
151 idx->text, ata_mode2str(idx->max_dma));
152 else
153 idx = &id[0];
154
155 device_set_desc_copy(dev, buffer);
156 ctlr->chip = idx;
157 ctlr->chipinit = ata_sis_chipinit;
158 return (BUS_PROBE_DEFAULT);
159}
160
161static int

--- 95 unchanged lines hidden (view full) ---

257 pci_read_config(parent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
258 ata_print_cable(dev, "controller");
259 mode = ATA_UDMA2;
260 }
261 }
262
263 switch (ctlr->chip->cfg1) {
264 case SIS_133NEW: {
154
155 device_set_desc_copy(dev, buffer);
156 ctlr->chip = idx;
157 ctlr->chipinit = ata_sis_chipinit;
158 return (BUS_PROBE_DEFAULT);
159}
160
161static int

--- 95 unchanged lines hidden (view full) ---

257 pci_read_config(parent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
258 ata_print_cable(dev, "controller");
259 mode = ATA_UDMA2;
260 }
261 }
262
263 switch (ctlr->chip->cfg1) {
264 case SIS_133NEW: {
265 u_int32_t timings[] =
265 static const uint32_t timings[] =
266 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
267 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
268 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
269 u_int32_t reg;
270
271 reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
272 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4);
273 break;
274 }
275 case SIS_133OLD: {
266 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
267 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
268 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
269 u_int32_t reg;
270
271 reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
272 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4);
273 break;
274 }
275 case SIS_133OLD: {
276 u_int16_t timings[] =
276 static const uint16_t timings[] =
277 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
278 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
279
280 u_int16_t reg = 0x40 + (devno << 1);
281
282 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
283 break;
284 }
285 case SIS_100NEW: {
277 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
278 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
279
280 u_int16_t reg = 0x40 + (devno << 1);
281
282 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
283 break;
284 }
285 case SIS_100NEW: {
286 u_int16_t timings[] =
286 static const uint16_t timings[] =
287 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
288 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
289 u_int16_t reg = 0x40 + (devno << 1);
290
291 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
292 break;
293 }
294 case SIS_100OLD:
295 case SIS_66:
296 case SIS_33: {
287 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
288 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
289 u_int16_t reg = 0x40 + (devno << 1);
290
291 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
292 break;
293 }
294 case SIS_100OLD:
295 case SIS_66:
296 case SIS_33: {
297 u_int16_t timings[] =
297 static const uint16_t timings[] =
298 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
299 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
300 u_int16_t reg = 0x40 + (devno << 1);
301
302 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
303 break;
304 }
305 }
306 return (mode);
307}
308
309ATA_DECLARE_DRIVER(ata_sis);
298 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
299 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
300 u_int16_t reg = 0x40 + (devno << 1);
301
302 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
303 break;
304 }
305 }
306 return (mode);
307}
308
309ATA_DECLARE_DRIVER(ata_sis);