ata-sis.c (194893) | ata-sis.c (200171) |
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1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-sis.c 194893 2009-06-24 19:49:18Z mav $"); | 28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-sis.c 200171 2009-12-06 00:10:13Z mav $"); |
29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> --- 13 unchanged lines hidden (view full) --- 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_sis_chipinit(device_t dev); 56static int ata_sis_ch_attach(device_t dev); 57static void ata_sis_reset(device_t dev); | 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> --- 13 unchanged lines hidden (view full) --- 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_sis_chipinit(device_t dev); 56static int ata_sis_ch_attach(device_t dev); 57static void ata_sis_reset(device_t dev); |
58static void ata_sis_setmode(device_t dev, int mode); | 58static int ata_sis_setmode(device_t dev, int target, int mode); |
59 60/* misc defines */ 61#define SIS_33 1 62#define SIS_66 2 63#define SIS_100NEW 3 64#define SIS_100OLD 4 65#define SIS_133NEW 5 66#define SIS_133OLD 6 --- 119 unchanged lines hidden (view full) --- 186 ctlr->r_rid2 = PCIR_BAR(5); 187 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 188 &ctlr->r_rid2, RF_ACTIVE))) { 189 ctlr->ch_attach = ata_sis_ch_attach; 190 ctlr->ch_detach = ata_pci_ch_detach; 191 ctlr->reset = ata_sis_reset; 192 } 193 ctlr->setmode = ata_sata_setmode; | 59 60/* misc defines */ 61#define SIS_33 1 62#define SIS_66 2 63#define SIS_100NEW 3 64#define SIS_100OLD 4 65#define SIS_133NEW 5 66#define SIS_133OLD 6 --- 119 unchanged lines hidden (view full) --- 186 ctlr->r_rid2 = PCIR_BAR(5); 187 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 188 &ctlr->r_rid2, RF_ACTIVE))) { 189 ctlr->ch_attach = ata_sis_ch_attach; 190 ctlr->ch_detach = ata_pci_ch_detach; 191 ctlr->reset = ata_sis_reset; 192 } 193 ctlr->setmode = ata_sata_setmode; |
194 ctlr->getrev = ata_sata_getrev; |
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194 return 0; 195 default: 196 return ENXIO; 197 } 198 ctlr->setmode = ata_sis_setmode; 199 return 0; 200} 201 --- 10 unchanged lines hidden (view full) --- 212 213 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 214 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 215 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 216 ch->r_io[ATA_SERROR].offset = 0x04 + offset; 217 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 218 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 219 ch->flags |= ATA_NO_SLAVE; | 195 return 0; 196 default: 197 return ENXIO; 198 } 199 ctlr->setmode = ata_sis_setmode; 200 return 0; 201} 202 --- 10 unchanged lines hidden (view full) --- 213 214 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 215 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 216 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 217 ch->r_io[ATA_SERROR].offset = 0x04 + offset; 218 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 219 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 220 ch->flags |= ATA_NO_SLAVE; |
221 ch->flags |= ATA_SATA; |
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220 221 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 222 /* XXX SOS unknown how to enable PHY state change interrupt */ 223 return 0; 224} 225 226static void 227ata_sis_reset(device_t dev) 228{ 229 if (ata_sata_phy_reset(dev, -1, 1)) 230 ata_generic_reset(dev); 231} 232 | 222 223 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 224 /* XXX SOS unknown how to enable PHY state change interrupt */ 225 return 0; 226} 227 228static void 229ata_sis_reset(device_t dev) 230{ 231 if (ata_sata_phy_reset(dev, -1, 1)) 232 ata_generic_reset(dev); 233} 234 |
233static void 234ata_sis_setmode(device_t dev, int mode) | 235static int 236ata_sis_setmode(device_t dev, int target, int mode) |
235{ | 237{ |
236 device_t gparent = GRANDPARENT(dev); 237 struct ata_pci_controller *ctlr = device_get_softc(gparent); 238 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 239 struct ata_device *atadev = device_get_softc(dev); 240 int devno = (ch->unit << 1) + atadev->unit; 241 int error; | 238 device_t parent = device_get_parent(dev); 239 struct ata_pci_controller *ctlr = device_get_softc(parent); 240 struct ata_channel *ch = device_get_softc(dev); 241 int devno = (ch->unit << 1) + target; |
242 | 242 |
243 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); | 243 mode = min(mode, ctlr->chip->max_dma); |
244 | 244 |
245 if (ctlr->chip->cfg1 == SIS_133NEW) { 246 if (mode > ATA_UDMA2 && 247 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 248 ata_print_cable(dev, "controller"); 249 mode = ATA_UDMA2; 250 } 251 } 252 else { 253 if (mode > ATA_UDMA2 && 254 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 255 ata_print_cable(dev, "controller"); 256 mode = ATA_UDMA2; 257 } 258 } | 245 if (ctlr->chip->cfg1 == SIS_133NEW) { 246 if (mode > ATA_UDMA2 && 247 pci_read_config(parent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 248 ata_print_cable(dev, "controller"); 249 mode = ATA_UDMA2; 250 } 251 } else { 252 if (mode > ATA_UDMA2 && 253 pci_read_config(parent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 254 ata_print_cable(dev, "controller"); 255 mode = ATA_UDMA2; 256 } 257 } |
259 | 258 |
260 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 261 262 if (bootverbose) 263 device_printf(dev, "%ssetting %s on %s chip\n", 264 (error) ? "FAILURE " : "", 265 ata_mode2str(mode), ctlr->chip->text); 266 if (!error) { | |
267 switch (ctlr->chip->cfg1) { 268 case SIS_133NEW: { 269 u_int32_t timings[] = 270 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 271 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 272 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 273 u_int32_t reg; 274 | 259 switch (ctlr->chip->cfg1) { 260 case SIS_133NEW: { 261 u_int32_t timings[] = 262 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 263 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 264 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 265 u_int32_t reg; 266 |
275 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 276 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4); | 267 reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 268 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4); |
277 break; 278 } 279 case SIS_133OLD: { 280 u_int16_t timings[] = 281 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 282 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 283 284 u_int16_t reg = 0x40 + (devno << 1); 285 | 269 break; 270 } 271 case SIS_133OLD: { 272 u_int16_t timings[] = 273 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 274 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 275 276 u_int16_t reg = 0x40 + (devno << 1); 277 |
286 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); | 278 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); |
287 break; 288 } 289 case SIS_100NEW: { 290 u_int16_t timings[] = 291 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 292 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 293 u_int16_t reg = 0x40 + (devno << 1); 294 | 279 break; 280 } 281 case SIS_100NEW: { 282 u_int16_t timings[] = 283 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 284 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 285 u_int16_t reg = 0x40 + (devno << 1); 286 |
295 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); | 287 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); |
296 break; 297 } 298 case SIS_100OLD: 299 case SIS_66: 300 case SIS_33: { 301 u_int16_t timings[] = 302 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 303 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 304 u_int16_t reg = 0x40 + (devno << 1); 305 | 288 break; 289 } 290 case SIS_100OLD: 291 case SIS_66: 292 case SIS_33: { 293 u_int16_t timings[] = 294 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 295 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 296 u_int16_t reg = 0x40 + (devno << 1); 297 |
306 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); | 298 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); |
307 break; 308 } 309 } | 299 break; 300 } 301 } |
310 atadev->mode = mode; 311 } | 302 return (mode); |
312} 313 314ATA_DECLARE_DRIVER(ata_sis); | 303} 304 305ATA_DECLARE_DRIVER(ata_sis); |