| ata-ite.c (194893) | ata-ite.c (200171) |
|---|---|
| 1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
| 28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-ite.c 194893 2009-06-24 19:49:18Z mav $"); | 28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-ite.c 200171 2009-12-06 00:10:13Z mav $"); |
| 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> --- 11 unchanged lines hidden (view full) --- 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_ite_chipinit(device_t dev); | 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> --- 11 unchanged lines hidden (view full) --- 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_ite_chipinit(device_t dev); |
| 56static void ata_ite_821x_setmode(device_t dev, int mode); 57static void ata_ite_8213_setmode(device_t dev, int mode); | 56static int ata_ite_ch_attach(device_t dev); 57static int ata_ite_821x_setmode(device_t dev, int target, int mode); 58static int ata_ite_8213_setmode(device_t dev, int target, int mode); |
| 58 59 60/* 61 * Integrated Technology Express Inc. (ITE) chipset support functions 62 */ 63static int 64ata_ite_probe(device_t dev) 65{ --- 34 unchanged lines hidden (view full) --- 100 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 101 102 /* set default active & recover timings */ 103 pci_write_config(dev, 0x54, 0x31, 1); 104 pci_write_config(dev, 0x56, 0x31, 1); 105 106 ctlr->setmode = ata_ite_821x_setmode; 107 } | 59 60 61/* 62 * Integrated Technology Express Inc. (ITE) chipset support functions 63 */ 64static int 65ata_ite_probe(device_t dev) 66{ --- 34 unchanged lines hidden (view full) --- 101 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 102 103 /* set default active & recover timings */ 104 pci_write_config(dev, 0x54, 0x31, 1); 105 pci_write_config(dev, 0x56, 0x31, 1); 106 107 ctlr->setmode = ata_ite_821x_setmode; 108 } |
| 108 | 109 ctlr->ch_attach = ata_ite_ch_attach; |
| 109 return 0; 110} | 110 return 0; 111} |
| 112 113static int 114ata_ite_ch_attach(device_t dev) 115{ 116 struct ata_channel *ch = device_get_softc(dev); 117 int error; |
|
| 111 | 118 |
| 112static void 113ata_ite_821x_setmode(device_t dev, int mode) | 119 error = ata_pci_ch_attach(dev); 120 ch->flags |= ATA_CHECKS_CABLE; 121 return (error); 122} 123 124static int 125ata_ite_821x_setmode(device_t dev, int target, int mode) |
| 114{ | 126{ |
| 115 device_t gparent = GRANDPARENT(dev); 116 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 117 struct ata_device *atadev = device_get_softc(dev); 118 int devno = (ch->unit << 1) + atadev->unit; 119 int error; | 127 device_t parent = device_get_parent(dev); 128 struct ata_pci_controller *ctlr = device_get_softc(parent); 129 struct ata_channel *ch = device_get_softc(dev); 130 int devno = (ch->unit << 1) + target; 131 int piomode; 132 u_int8_t udmatiming[] = 133 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 134 u_int8_t chtiming[] = 135 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; |
| 120 | 136 |
| 121 /* correct the mode for what the HW supports */ 122 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 123 124 /* check the CBLID bits for 80 conductor cable detection */ 125 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) & | 137 mode = min(mode, ctlr->chip->max_dma); 138 /* check the CBLID bits for 80 conductor cable detection */ 139 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x40, 2) & |
| 126 (ch->unit ? (1<<3) : (1<<2)))) { | 140 (ch->unit ? (1<<3) : (1<<2)))) { |
| 127 ata_print_cable(dev, "controller"); 128 mode = ATA_UDMA2; 129 } 130 131 /* set the wanted mode on the device */ 132 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 133 134 if (bootverbose) 135 device_printf(dev, "%s setting %s on ITE8212F chip\n", 136 (error) ? "failed" : "success", ata_mode2str(mode)); 137 138 /* if the device accepted the mode change, setup the HW accordingly */ 139 if (!error) { | 141 ata_print_cable(dev, "controller"); 142 mode = ATA_UDMA2; 143 } |
| 140 if (mode >= ATA_UDMA0) { | 144 if (mode >= ATA_UDMA0) { |
| 141 u_int8_t udmatiming[] = 142 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 143 144 /* enable UDMA mode */ 145 pci_write_config(gparent, 0x50, 146 pci_read_config(gparent, 0x50, 1) & | 145 /* enable UDMA mode */ 146 pci_write_config(parent, 0x50, 147 pci_read_config(parent, 0x50, 1) & |
| 147 ~(1 << (devno + 3)), 1); | 148 ~(1 << (devno + 3)), 1); |
| 148 149 /* set UDMA timing */ 150 pci_write_config(gparent, 151 0x56 + (ch->unit << 2) + atadev->unit, | 149 /* set UDMA timing */ 150 pci_write_config(parent, 151 0x56 + (ch->unit << 2) + target, |
| 152 udmatiming[mode & ATA_MODE_MASK], 1); | 152 udmatiming[mode & ATA_MODE_MASK], 1); |
| 153 } 154 else { 155 u_int8_t chtiming[] = 156 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 157 158 /* disable UDMA mode */ 159 pci_write_config(gparent, 0x50, 160 pci_read_config(gparent, 0x50, 1) | | 153 piomode = ATA_PIO4; 154 } else { 155 /* disable UDMA mode */ 156 pci_write_config(parent, 0x50, 157 pci_read_config(parent, 0x50, 1) | |
| 161 (1 << (devno + 3)), 1); | 158 (1 << (devno + 3)), 1); |
| 162 163 /* set active and recover timing (shared between master & slave) */ 164 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) < 165 chtiming[ata_mode2idx(mode)]) 166 pci_write_config(gparent, 0x54 + (ch->unit << 2), 167 chtiming[ata_mode2idx(mode)], 1); | 159 piomode = mode; |
| 168 } | 160 } |
| 169 atadev->mode = mode; 170 } | 161 /* set active and recover timing (shared between master & slave) */ 162 if (pci_read_config(parent, 0x54 + (ch->unit << 2), 1) < 163 chtiming[ata_mode2idx(piomode)]) 164 pci_write_config(parent, 0x54 + (ch->unit << 2), 165 chtiming[ata_mode2idx(piomode)], 1); 166 return (mode); |
| 171} 172 | 167} 168 |
| 173static void 174ata_ite_8213_setmode(device_t dev, int mode) | 169static int 170ata_ite_8213_setmode(device_t dev, int target, int mode) |
| 175{ | 171{ |
| 176 device_t gparent = GRANDPARENT(dev); 177 struct ata_pci_controller *ctlr = device_get_softc(gparent); 178 struct ata_device *atadev = device_get_softc(dev); 179 u_int16_t reg40 = pci_read_config(gparent, 0x40, 2); 180 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1); 181 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1); 182 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2); 183 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2); 184 u_int16_t mask40 = 0, new40 = 0; 185 u_int8_t mask44 = 0, new44 = 0; 186 int devno = atadev->unit; 187 int error; 188 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 189 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 }; | 172 device_t parent = device_get_parent(dev); 173 struct ata_pci_controller *ctlr = device_get_softc(parent); 174 int piomode; 175 u_int16_t reg40 = pci_read_config(parent, 0x40, 2); 176 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 177 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 178 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 179 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 180 u_int16_t mask40 = 0, new40 = 0; 181 u_int8_t mask44 = 0, new44 = 0; 182 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 183 u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; |
| 190 | 184 |
| 191 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); | 185 mode = min(mode, ctlr->chip->max_dma); |
| 192 | 186 |
| 193 if (mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 194 ata_print_cable(dev, "controller"); 195 mode = ATA_UDMA2; 196 } 197 198 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 199 200 if (bootverbose) 201 device_printf(dev, "%ssetting %s on %s chip\n", 202 (error) ? "FAILURE " : "", 203 ata_mode2str(mode), ctlr->chip->text); 204 if (!error) { | 187 if (mode > ATA_UDMA2 && !(reg54 & (0x10 << target))) { 188 ata_print_cable(dev, "controller"); 189 mode = ATA_UDMA2; 190 } 191 /* Enable/disable UDMA and set timings. */ |
| 205 if (mode >= ATA_UDMA0) { | 192 if (mode >= ATA_UDMA0) { |
| 206 u_int8_t utimings[] = { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 }; 207 208 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2); 209 pci_write_config(gparent, 0x4a, 210 (reg4a & ~(0x3 << (devno << 2))) | 211 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); | 193 pci_write_config(parent, 0x48, reg48 | (0x0001 << target), 2); 194 pci_write_config(parent, 0x4a, 195 (reg4a & ~(0x3 << (target << 2))) | 196 (utimings[mode & ATA_MODE_MASK] << (target<<2)), 2); 197 piomode = ATA_PIO4; 198 } else { 199 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << target), 2); 200 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (target << 2))),2); 201 piomode = mode; |
| 212 } | 202 } |
| 213 else { 214 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2); 215 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 216 } 217 if (mode >= ATA_UDMA2) 218 reg54 |= (0x1 << devno); 219 else 220 reg54 &= ~(0x1 << devno); | 203 /* Set UDMA reference clock (33/66/133MHz). */ 204 reg54 &= ~(0x1001 << target); |
| 221 if (mode >= ATA_UDMA5) | 205 if (mode >= ATA_UDMA5) |
| 222 reg54 |= (0x1000 << devno); 223 else 224 reg54 &= ~(0x1000 << devno); 225 pci_write_config(gparent, 0x54, reg54, 2); 226 | 206 reg54 |= (0x1000 << target); 207 else if (mode >= ATA_UDMA3) 208 reg54 |= (0x1 << target); 209 pci_write_config(parent, 0x54, reg54, 2); 210 /* Allow PIO/WDMA timing controls. */ |
| 227 reg40 &= 0xff00; 228 reg40 |= 0x4033; | 211 reg40 &= 0xff00; 212 reg40 |= 0x4033; |
| 229 if (atadev->unit == ATA_MASTER) { | 213 /* Set PIO/WDMA timings. */ 214 if (target == 0) { |
| 230 reg40 |= (ata_atapi(dev) ? 0x04 : 0x00); 231 mask40 = 0x3300; | 215 reg40 |= (ata_atapi(dev) ? 0x04 : 0x00); 216 mask40 = 0x3300; |
| 232 new40 = timings[ata_mode2idx(mode)] << 8; | 217 new40 = timings[ata_mode2idx(piomode)] << 8; |
| 233 } 234 else { 235 reg40 |= (ata_atapi(dev) ? 0x40 : 0x00); 236 mask44 = 0x0f; | 218 } 219 else { 220 reg40 |= (ata_atapi(dev) ? 0x40 : 0x00); 221 mask44 = 0x0f; |
| 237 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) | 238 (timings[ata_mode2idx(mode)] & 0x03); | 222 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 223 (timings[ata_mode2idx(piomode)] & 0x03); |
| 239 } | 224 } |
| 240 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4); 241 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1); 242 243 atadev->mode = mode; 244 } | 225 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 226 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 227 return (mode); |
| 245} 246 247ATA_DECLARE_DRIVER(ata_ite); | 228} 229 230ATA_DECLARE_DRIVER(ata_ite); |