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if_ale.c (213844) if_ale.c (213893)
1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
29
30#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 14 unchanged lines hidden (view full) ---

23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/ale/if_ale.c 213844 2010-10-14 18:31:40Z yongari $");
31__FBSDID("$FreeBSD: head/sys/dev/ale/if_ale.c 213893 2010-10-15 14:52:11Z marius $");
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/endian.h>
37#include <sys/kernel.h>
38#include <sys/malloc.h>
39#include <sys/mbuf.h>

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203ale_miibus_readreg(device_t dev, int phy, int reg)
204{
205 struct ale_softc *sc;
206 uint32_t v;
207 int i;
208
209 sc = device_get_softc(dev);
210
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/endian.h>
37#include <sys/kernel.h>
38#include <sys/malloc.h>
39#include <sys/mbuf.h>

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203ale_miibus_readreg(device_t dev, int phy, int reg)
204{
205 struct ale_softc *sc;
206 uint32_t v;
207 int i;
208
209 sc = device_get_softc(dev);
210
211 if (phy != sc->ale_phyaddr)
212 return (0);
213
214 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
215 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
216 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
217 DELAY(5);
218 v = CSR_READ_4(sc, ALE_MDIO);
219 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
220 break;
221 }

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232ale_miibus_writereg(device_t dev, int phy, int reg, int val)
233{
234 struct ale_softc *sc;
235 uint32_t v;
236 int i;
237
238 sc = device_get_softc(dev);
239
211 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
212 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
213 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
214 DELAY(5);
215 v = CSR_READ_4(sc, ALE_MDIO);
216 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
217 break;
218 }

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229ale_miibus_writereg(device_t dev, int phy, int reg, int val)
230{
231 struct ale_softc *sc;
232 uint32_t v;
233 int i;
234
235 sc = device_get_softc(dev);
236
240 if (phy != sc->ale_phyaddr)
241 return (0);
242
243 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
244 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
245 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
246 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
247 DELAY(5);
248 v = CSR_READ_4(sc, ALE_MDIO);
249 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
250 break;

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600 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO;
601 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
602 sc->ale_flags |= ALE_FLAG_PMCAP;
603 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
604 }
605 ifp->if_capenable = ifp->if_capabilities;
606
607 /* Set up MII bus. */
237 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
238 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
239 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
240 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
241 DELAY(5);
242 v = CSR_READ_4(sc, ALE_MDIO);
243 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
244 break;

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594 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO;
595 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
596 sc->ale_flags |= ALE_FLAG_PMCAP;
597 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
598 }
599 ifp->if_capenable = ifp->if_capabilities;
600
601 /* Set up MII bus. */
608 if ((error = mii_phy_probe(dev, &sc->ale_miibus, ale_mediachange,
609 ale_mediastatus)) != 0) {
610 device_printf(dev, "no PHY found!\n");
602 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange,
603 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY,
604 0);
605 if (error != 0) {
606 device_printf(dev, "attaching PHYs failed\n");
611 goto fail;
612 }
613
614 ether_ifattach(ifp, sc->ale_eaddr);
615
616 /* VLAN capability setup. */
617 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
618 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;

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607 goto fail;
608 }
609
610 ether_ifattach(ifp, sc->ale_eaddr);
611
612 /* VLAN capability setup. */
613 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
614 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;

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