Deleted Added
sdiff udiff text old ( 72811 ) new ( 74094 )
full compact
aic7xxx_pci.c (72811) aic7xxx_pci.c (74094)
1/*
2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
5 *
6 * Copyright (c) 1995-2000 Justin T. Gibbs
7 * All rights reserved.
8 *

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25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
1/*
2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
5 *
6 * Copyright (c) 1995-2000 Justin T. Gibbs
7 * All rights reserved.
8 *

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25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $Id: //depot/src/aic7xxx/aic7xxx_pci.c#16 $
33 * $Id: //depot/src/aic7xxx/aic7xxx_pci.c#19 $
34 *
34 *
35 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx_pci.c 72811 2001-02-21 20:50:36Z gibbs $
35 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx_pci.c 74094 2001-03-11 06:34:17Z gibbs $
36 */
37
38#ifdef __linux__
39#include "aic7xxx_linux.h"
40#include "aic7xxx_inline.h"
41#include "aic7xxx_93cx6.h"
42#endif
43

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58 id = subvendor
59 | (subdevice << 16)
60 | ((uint64_t)vendor << 32)
61 | ((uint64_t)device << 48);
62
63 return (id);
64}
65
36 */
37
38#ifdef __linux__
39#include "aic7xxx_linux.h"
40#include "aic7xxx_inline.h"
41#include "aic7xxx_93cx6.h"
42#endif
43

--- 14 unchanged lines hidden (view full) ---

58 id = subvendor
59 | (subdevice << 16)
60 | ((uint64_t)vendor << 32)
61 | ((uint64_t)device << 48);
62
63 return (id);
64}
65
66#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
67#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
68#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
69#define ID_9005_SISL_MASK 0x000FFFFF00000000ull
70#define ID_9005_SISL_ID 0x0005900500000000ull
71#define ID_AIC7850 0x5078900400000000ull
72#define ID_AHA_2910_15_20_30C 0x5078900478509004ull
73#define ID_AIC7855 0x5578900400000000ull
74#define ID_AIC7859 0x3860900400000000ull
75#define ID_AHA_2930CU 0x3860900438699004ull
76#define ID_AIC7860 0x6078900400000000ull
77#define ID_AIC7860C 0x6078900478609004ull
78#define ID_AHA_1480A 0x6075900400000000ull
79#define ID_AHA_2940AU_0 0x6178900400000000ull
80#define ID_AHA_2940AU_1 0x6178900478619004ull
81#define ID_AHA_2940AU_CN 0x2178900478219004ull
82#define ID_AHA_2930C_VAR 0x6038900438689004ull
66#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
67#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
68#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
69#define ID_9005_SISL_MASK 0x000FFFFF00000000ull
70#define ID_9005_SISL_ID 0x0005900500000000ull
71#define ID_AIC7850 0x5078900400000000ull
72#define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull
73#define ID_AIC7855 0x5578900400000000ull
74#define ID_AIC7859 0x3860900400000000ull
75#define ID_AHA_2930CU 0x3860900438699004ull
76#define ID_AIC7860 0x6078900400000000ull
77#define ID_AIC7860C 0x6078900478609004ull
78#define ID_AHA_1480A 0x6075900400000000ull
79#define ID_AHA_2940AU_0 0x6178900400000000ull
80#define ID_AHA_2940AU_1 0x6178900478619004ull
81#define ID_AHA_2940AU_CN 0x2178900478219004ull
82#define ID_AHA_2930C_VAR 0x6038900438689004ull
83
83
84#define ID_AIC7870 0x7078900400000000ull
85#define ID_AHA_2940 0x7178900400000000ull
86#define ID_AHA_3940 0x7278900400000000ull
87#define ID_AHA_398X 0x7378900400000000ull
88#define ID_AHA_2944 0x7478900400000000ull
89#define ID_AHA_3944 0x7578900400000000ull
90#define ID_AHA_4944 0x7678900400000000ull
84#define ID_AIC7870 0x7078900400000000ull
85#define ID_AHA_2940 0x7178900400000000ull
86#define ID_AHA_3940 0x7278900400000000ull
87#define ID_AHA_398X 0x7378900400000000ull
88#define ID_AHA_2944 0x7478900400000000ull
89#define ID_AHA_3944 0x7578900400000000ull
90#define ID_AHA_4944 0x7678900400000000ull
91
91
92#define ID_AIC7880 0x8078900400000000ull
93#define ID_AIC7880_B 0x8078900478809004ull
94#define ID_AHA_2940U 0x8178900400000000ull
95#define ID_AHA_3940U 0x8278900400000000ull
96#define ID_AHA_2944U 0x8478900400000000ull
97#define ID_AHA_3944U 0x8578900400000000ull
98#define ID_AHA_398XU 0x8378900400000000ull
99#define ID_AHA_4944U 0x8678900400000000ull
100#define ID_AHA_2940UB 0x8178900478819004ull
101#define ID_AHA_2930U 0x8878900478889004ull
102#define ID_AHA_2940U_PRO 0x8778900478879004ull
103#define ID_AHA_2940U_CN 0x0078900478009004ull
92#define ID_AIC7880 0x8078900400000000ull
93#define ID_AIC7880_B 0x8078900478809004ull
94#define ID_AHA_2940U 0x8178900400000000ull
95#define ID_AHA_3940U 0x8278900400000000ull
96#define ID_AHA_2944U 0x8478900400000000ull
97#define ID_AHA_3944U 0x8578900400000000ull
98#define ID_AHA_398XU 0x8378900400000000ull
99#define ID_AHA_4944U 0x8678900400000000ull
100#define ID_AHA_2940UB 0x8178900478819004ull
101#define ID_AHA_2930U 0x8878900478889004ull
102#define ID_AHA_2940U_PRO 0x8778900478879004ull
103#define ID_AHA_2940U_CN 0x0078900478009004ull
104
104
105#define ID_AIC7895 0x7895900478959004ull
106#define ID_AIC7895_ARO 0x7890900478939004ull
107#define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
108#define ID_AHA_2940U_DUAL 0x7895900478919004ull
109#define ID_AHA_3940AU 0x7895900478929004ull
110#define ID_AHA_3944AU 0x7895900478949004ull
105#define ID_AIC7895 0x7895900478959004ull
106#define ID_AIC7895_ARO 0x7890900478939004ull
107#define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
108#define ID_AHA_2940U_DUAL 0x7895900478919004ull
109#define ID_AHA_3940AU 0x7895900478929004ull
110#define ID_AHA_3944AU 0x7895900478949004ull
111
111
112#define ID_AIC7890 0x001F9005000F9005ull
113#define ID_AIC7890_ARO 0x00139005000F9005ull
114#define ID_AAA_131U2 0x0013900500039005ull
115#define ID_AHA_2930U2 0x0011900501819005ull
116#define ID_AHA_2940U2B 0x00109005A1009005ull
117#define ID_AHA_2940U2_OEM 0x0010900521809005ull
118#define ID_AHA_2940U2 0x00109005A1809005ull
119#define ID_AHA_2950U2B 0x00109005E1009005ull
112#define ID_AIC7890 0x001F9005000F9005ull
113#define ID_AIC7890_ARO 0x00139005000F9005ull
114#define ID_AAA_131U2 0x0013900500039005ull
115#define ID_AHA_2930U2 0x0011900501819005ull
116#define ID_AHA_2940U2B 0x00109005A1009005ull
117#define ID_AHA_2940U2_OEM 0x0010900521809005ull
118#define ID_AHA_2940U2 0x00109005A1809005ull
119#define ID_AHA_2950U2B 0x00109005E1009005ull
120
120
121#define ID_AIC7892 0x008F9005FFFF9005ull
122#define ID_AIC7892_ARO 0x00839005FFFF9005ull
123#define ID_AHA_29160 0x00809005E2A09005ull
124#define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
125#define ID_AHA_29160N 0x0080900562A09005ull
126#define ID_AHA_29160C 0x0080900562209005ull
127#define ID_AHA_29160B 0x00809005E2209005ull
128#define ID_AHA_19160B 0x0081900562A19005ull
121#define ID_AIC7892 0x008F9005FFFF9005ull
122#define ID_AIC7892_ARO 0x00839005FFFF9005ull
123#define ID_AHA_29160 0x00809005E2A09005ull
124#define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
125#define ID_AHA_29160N 0x0080900562A09005ull
126#define ID_AHA_29160C 0x0080900562209005ull
127#define ID_AHA_29160B 0x00809005E2209005ull
128#define ID_AHA_19160B 0x0081900562A19005ull
129
129
130#define ID_AIC7896 0x005F9005FFFF9005ull
131#define ID_AIC7896_ARO 0x00539005FFFF9005ull
132#define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
133#define ID_AHA_3950U2B_1 0x00509005F5009005ull
134#define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
135#define ID_AHA_3950U2D_1 0x00519005B5009005ull
130#define ID_AIC7896 0x005F9005FFFF9005ull
131#define ID_AIC7896_ARO 0x00539005FFFF9005ull
132#define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
133#define ID_AHA_3950U2B_1 0x00509005F5009005ull
134#define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
135#define ID_AHA_3950U2D_1 0x00519005B5009005ull
136
136
137#define ID_AIC7899 0x00CF9005FFFF9005ull
138#define ID_AIC7899_ARO 0x00C39005FFFF9005ull
139#define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */
140#define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
137#define ID_AIC7899 0x00CF9005FFFF9005ull
138#define ID_AIC7899_ARO 0x00C39005FFFF9005ull
139#define ID_AHA_3960D 0x00C09005F6209005ull
140#define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
141
141
142#define ID_AIC7810 0x1078900400000000ull
143#define ID_AIC7815 0x7815900400000000ull
142#define ID_AIC7810 0x1078900400000000ull
143#define ID_AIC7815 0x7815900400000000ull
144
145#define DEVID_9005_TYPE(id) ((id) & 0xF)
146#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
147#define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
148#define DEVID_9005_TYPE_SISL 0x5 /* Low Cost Card */
149#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
150
151#define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)

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207/*
208 * Informational only. Should use chip register to be
209 * ceratian, but may be use in identification strings.
210 */
211#define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
212#define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
213#define SUBID_9005_CARD_SEDIFF_MASK 0x8000
214
144
145#define DEVID_9005_TYPE(id) ((id) & 0xF)
146#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
147#define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
148#define DEVID_9005_TYPE_SISL 0x5 /* Low Cost Card */
149#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
150
151#define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)

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207/*
208 * Informational only. Should use chip register to be
209 * ceratian, but may be use in identification strings.
210 */
211#define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
212#define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
213#define SUBID_9005_CARD_SEDIFF_MASK 0x8000
214
215static ahc_device_setup_t ahc_aic7850_setup;
216static ahc_device_setup_t ahc_aic7855_setup;
215static ahc_device_setup_t ahc_aic785X_setup;
217static ahc_device_setup_t ahc_aic7860_setup;
218static ahc_device_setup_t ahc_apa1480_setup;
219static ahc_device_setup_t ahc_aic7870_setup;
220static ahc_device_setup_t ahc_aha394X_setup;
221static ahc_device_setup_t ahc_aha494X_setup;
222static ahc_device_setup_t ahc_aha398X_setup;
223static ahc_device_setup_t ahc_aic7880_setup;
224static ahc_device_setup_t ahc_aha2940Pro_setup;

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234static ahc_device_setup_t ahc_aha394XX_setup;
235static ahc_device_setup_t ahc_aha494XX_setup;
236static ahc_device_setup_t ahc_aha398XX_setup;
237
238struct ahc_pci_identity ahc_pci_ident_table [] =
239{
240 /* aic7850 based controllers */
241 {
216static ahc_device_setup_t ahc_aic7860_setup;
217static ahc_device_setup_t ahc_apa1480_setup;
218static ahc_device_setup_t ahc_aic7870_setup;
219static ahc_device_setup_t ahc_aha394X_setup;
220static ahc_device_setup_t ahc_aha494X_setup;
221static ahc_device_setup_t ahc_aha398X_setup;
222static ahc_device_setup_t ahc_aic7880_setup;
223static ahc_device_setup_t ahc_aha2940Pro_setup;

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233static ahc_device_setup_t ahc_aha394XX_setup;
234static ahc_device_setup_t ahc_aha494XX_setup;
235static ahc_device_setup_t ahc_aha398XX_setup;
236
237struct ahc_pci_identity ahc_pci_ident_table [] =
238{
239 /* aic7850 based controllers */
240 {
242 ID_AHA_2910_15_20_30C,
241 ID_AHA_2902_04_10_15_20_30C,
243 ID_ALL_MASK,
242 ID_ALL_MASK,
244 "Adaptec 2910/15/20/30C SCSI adapter",
245 ahc_aic7850_setup
243 "Adaptec 2902/04/10/15/20/30C SCSI adapter",
244 ahc_aic785X_setup
246 },
247 /* aic7860 based controllers */
248 {
249 ID_AHA_2930CU,
250 ID_ALL_MASK,
251 "Adaptec 2930CU SCSI adapter",
252 ahc_aic7860_setup
253 },

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539 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
540 ahc_aic7899_setup
541 },
542 /* Generic chip probes for devices we don't know 'exactly' */
543 {
544 ID_AIC7850 & ID_DEV_VENDOR_MASK,
545 ID_DEV_VENDOR_MASK,
546 "Adaptec aic7850 SCSI adapter",
245 },
246 /* aic7860 based controllers */
247 {
248 ID_AHA_2930CU,
249 ID_ALL_MASK,
250 "Adaptec 2930CU SCSI adapter",
251 ahc_aic7860_setup
252 },

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538 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
539 ahc_aic7899_setup
540 },
541 /* Generic chip probes for devices we don't know 'exactly' */
542 {
543 ID_AIC7850 & ID_DEV_VENDOR_MASK,
544 ID_DEV_VENDOR_MASK,
545 "Adaptec aic7850 SCSI adapter",
547 ahc_aic7850_setup
546 ahc_aic785X_setup
548 },
549 {
550 ID_AIC7855 & ID_DEV_VENDOR_MASK,
551 ID_DEV_VENDOR_MASK,
552 "Adaptec aic7855 SCSI adapter",
547 },
548 {
549 ID_AIC7855 & ID_DEV_VENDOR_MASK,
550 ID_DEV_VENDOR_MASK,
551 "Adaptec aic7855 SCSI adapter",
553 ahc_aic7855_setup
552 ahc_aic785X_setup
554 },
555 {
556 ID_AIC7859 & ID_DEV_VENDOR_MASK,
557 ID_DEV_VENDOR_MASK,
558 "Adaptec aic7859 Ultra SCSI adapter",
559 ahc_aic7860_setup
560 },
561 {

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631
632#define AHC_494X_SLOT_CHANNEL_A 4
633#define AHC_494X_SLOT_CHANNEL_B 5
634#define AHC_494X_SLOT_CHANNEL_C 6
635#define AHC_494X_SLOT_CHANNEL_D 7
636
637#define DEVCONFIG 0x40
638#define SCBSIZE32 0x00010000ul /* aic789X only */
553 },
554 {
555 ID_AIC7859 & ID_DEV_VENDOR_MASK,
556 ID_DEV_VENDOR_MASK,
557 "Adaptec aic7859 Ultra SCSI adapter",
558 ahc_aic7860_setup
559 },
560 {

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630
631#define AHC_494X_SLOT_CHANNEL_A 4
632#define AHC_494X_SLOT_CHANNEL_B 5
633#define AHC_494X_SLOT_CHANNEL_C 6
634#define AHC_494X_SLOT_CHANNEL_D 7
635
636#define DEVCONFIG 0x40
637#define SCBSIZE32 0x00010000ul /* aic789X only */
638#define REXTVALID 0x00001000ul /* ultra cards only */
639#define MPORTMODE 0x00000400ul /* aic7870 only */
640#define RAMPSM 0x00000200ul /* aic7870 only */
641#define VOLSENSE 0x00000100ul
642#define SCBRAMSEL 0x00000080ul
643#define MRDCEN 0x00000040ul
644#define EXTSCBTIME 0x00000020ul /* aic7870 only */
645#define EXTSCBPEN 0x00000010ul /* aic7870 only */
646#define BERREN 0x00000008ul
647#define DACEN 0x00000004ul
648#define STPWLEVEL 0x00000002ul
649#define DIFACTNEGEN 0x00000001ul /* aic7870 only */
650
651#define CSIZE_LATTIME 0x0c
652#define CACHESIZE 0x0000003ful /* only 5 bits */
653#define LATTIME 0x0000ff00ul
654
639#define MPORTMODE 0x00000400ul /* aic7870 only */
640#define RAMPSM 0x00000200ul /* aic7870 only */
641#define VOLSENSE 0x00000100ul
642#define SCBRAMSEL 0x00000080ul
643#define MRDCEN 0x00000040ul
644#define EXTSCBTIME 0x00000020ul /* aic7870 only */
645#define EXTSCBPEN 0x00000010ul /* aic7870 only */
646#define BERREN 0x00000008ul
647#define DACEN 0x00000004ul
648#define STPWLEVEL 0x00000002ul
649#define DIFACTNEGEN 0x00000001ul /* aic7870 only */
650
651#define CSIZE_LATTIME 0x0c
652#define CACHESIZE 0x0000003ful /* only 5 bits */
653#define LATTIME 0x0000ff00ul
654
655typedef enum
656{
657 AHC_POWER_STATE_D0,
658 AHC_POWER_STATE_D1,
659 AHC_POWER_STATE_D2,
660 AHC_POWER_STATE_D3
661} ahc_power_state;
662
663static void ahc_power_state_change(struct ahc_softc *ahc,
664 ahc_power_state new_state);
665static int ahc_ext_scbram_present(struct ahc_softc *ahc);
666static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
667 int pcheck, int fast, int large);
668static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
669static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
670static void configure_termination(struct ahc_softc *ahc,
671 struct seeprom_descriptor *sd,
672 u_int adapter_control,

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766 probe_config.flags |= AHC_PAGESCBS;
767
768 error = ahc_softc_init(ahc, &probe_config);
769 if (error != 0)
770 return (error);
771
772 /* Remeber how the card was setup in case there is no SEEPROM */
773 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
655static int ahc_ext_scbram_present(struct ahc_softc *ahc);
656static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
657 int pcheck, int fast, int large);
658static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
659static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
660static void configure_termination(struct ahc_softc *ahc,
661 struct seeprom_descriptor *sd,
662 u_int adapter_control,

--- 93 unchanged lines hidden (view full) ---

756 probe_config.flags |= AHC_PAGESCBS;
757
758 error = ahc_softc_init(ahc, &probe_config);
759 if (error != 0)
760 return (error);
761
762 /* Remeber how the card was setup in case there is no SEEPROM */
763 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
774 pause_sequencer(ahc);
764 ahc_pause(ahc);
775 if ((ahc->features & AHC_ULTRA2) != 0)
776 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
777 else
778 our_id = ahc_inb(ahc, SCSIID) & OID;
779 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
780 scsiseq = ahc_inb(ahc, SCSISEQ);
781 } else {
782 sxfrctl1 = STPWEN;

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882
883 /*
884 * Record our termination setting for the
885 * generic initialization routine.
886 */
887 if ((sxfrctl1 & STPWEN) != 0)
888 ahc->flags |= AHC_TERM_ENB_A;
889
765 if ((ahc->features & AHC_ULTRA2) != 0)
766 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
767 else
768 our_id = ahc_inb(ahc, SCSIID) & OID;
769 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
770 scsiseq = ahc_inb(ahc, SCSISEQ);
771 } else {
772 sxfrctl1 = STPWEN;

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872
873 /*
874 * Record our termination setting for the
875 * generic initialization routine.
876 */
877 if ((sxfrctl1 & STPWEN) != 0)
878 ahc->flags |= AHC_TERM_ENB_A;
879
880 /*
881 * We cannot perform ULTRA speeds without
882 * the presense of the external precision
883 * resistor.
884 */
885 if ((ahc->features & AHC_ULTRA) != 0) {
886 uint32_t devconfig;
887
888 devconfig = ahc_pci_read_config(ahc->dev_softc,
889 DEVCONFIG, /*bytes*/4);
890 if ((devconfig & REXTVALID) == 0)
891 ahc->flags |= AHC_ULTRA_DISABLED;
892 }
893
890 /* Core initialization */
891 error = ahc_init(ahc);
892 if (error != 0)
893 return (error);
894
895 /*
896 * Link this softc in with all other ahc instances.
897 */
898 ahc_softc_insert(ahc);
899
900 return (0);
901}
902
894 /* Core initialization */
895 error = ahc_init(ahc);
896 if (error != 0)
897 return (error);
898
899 /*
900 * Link this softc in with all other ahc instances.
901 */
902 ahc_softc_insert(ahc);
903
904 return (0);
905}
906
903static void
904ahc_power_state_change(struct ahc_softc *ahc, ahc_power_state new_state)
905{
906 uint32_t cap;
907 u_int cap_offset;
908
909 /*
910 * Traverse the capability list looking for
911 * the power management capability.
912 */
913 cap = 0;
914 cap_offset = ahc_pci_read_config(ahc->dev_softc,
915 PCIR_CAP_PTR, /*bytes*/1);
916 while (cap_offset != 0) {
917
918 cap = ahc_pci_read_config(ahc->dev_softc,
919 cap_offset, /*bytes*/4);
920 if ((cap & 0xFF) == 1
921 && ((cap >> 16) & 0x3) > 0) {
922 uint32_t pm_control;
923
924 pm_control = ahc_pci_read_config(ahc->dev_softc,
925 cap_offset + 4,
926 /*bytes*/4);
927 pm_control &= ~0x3;
928 pm_control |= new_state;
929 ahc_pci_write_config(ahc->dev_softc,
930 cap_offset + 4,
931 pm_control, /*bytes*/2);
932 break;
933 }
934 cap_offset = (cap >> 8) & 0xFF;
935 }
936}
937
938/*
939 * Test for the presense of external sram in an
940 * "unshared" configuration.
941 */
942static int
943ahc_ext_scbram_present(struct ahc_softc *ahc)
944{
945 u_int chip;

--- 233 unchanged lines hidden (view full) ---

1179 printf ("checksum error\n");
1180 else
1181 printf ("done.\n");
1182 }
1183 break;
1184 }
1185 sd.sd_chip = C56_66;
1186 }
907/*
908 * Test for the presense of external sram in an
909 * "unshared" configuration.
910 */
911static int
912ahc_ext_scbram_present(struct ahc_softc *ahc)
913{
914 u_int chip;

--- 233 unchanged lines hidden (view full) ---

1148 printf ("checksum error\n");
1149 else
1150 printf ("done.\n");
1151 }
1152 break;
1153 }
1154 sd.sd_chip = C56_66;
1155 }
1156 release_seeprom(&sd);
1187 }
1188
1157 }
1158
1189#if 0
1190 if (!have_seeprom) {
1191 /*
1192 * Pull scratch ram settings and treat them as
1193 * if they are the contents of an seeprom if
1194 * the 'ADPT' signature is found in SCB2.
1159 if (!have_seeprom) {
1160 /*
1161 * Pull scratch ram settings and treat them as
1162 * if they are the contents of an seeprom if
1163 * the 'ADPT' signature is found in SCB2.
1164 * We manually compose the data as 16bit values
1165 * to avoid endian issues.
1195 */
1196 ahc_outb(ahc, SCBPTR, 2);
1197 if (ahc_inb(ahc, SCB_BASE) == 'A'
1198 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1199 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1200 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1166 */
1167 ahc_outb(ahc, SCBPTR, 2);
1168 if (ahc_inb(ahc, SCB_BASE) == 'A'
1169 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1170 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1171 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1201 uint8_t *sc_bytes;
1172 uint16_t *sc_data;
1202 int i;
1203
1173 int i;
1174
1204 sc_bytes = (uint8_t *)&sc;
1205 for (i = 0; i < 64; i++)
1206 sc_bytes[i] = ahc_inb(ahc, TARG_SCSIRATE + i);
1207 /* Byte 0x1c is stored in byte 4 of SCB2 */
1208 sc_bytes[0x1c] = ahc_inb(ahc, SCB_BASE + 4);
1175 sc_data = (uint16_t *)&sc;
1176 for (i = 0; i < 32; i++) {
1177 uint16_t val;
1178 int j;
1179
1180 j = i * 2;
1181 val = ahc_inb(ahc, SRAM_BASE + j)
1182 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1183 }
1209 have_seeprom = verify_cksum(&sc);
1210 }
1211 }
1184 have_seeprom = verify_cksum(&sc);
1185 }
1186 }
1212#endif
1213
1214 if (!have_seeprom) {
1215 if (bootverbose)
1216 printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1217 ahc->flags |= AHC_USEDEFAULTS;
1218 } else {
1219 /*
1220 * Put the data we've collected down into SRAM

--- 69 unchanged lines hidden (view full) ---

1290 ahc->our_id = sc.brtime_id & CFSCSIID;
1291
1292 scsi_conf = (ahc->our_id & 0x7);
1293 if (sc.adapter_control & CFSPARITY)
1294 scsi_conf |= ENSPCHK;
1295 if (sc.adapter_control & CFRESETB)
1296 scsi_conf |= RESET_SCSI;
1297
1187
1188 if (!have_seeprom) {
1189 if (bootverbose)
1190 printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1191 ahc->flags |= AHC_USEDEFAULTS;
1192 } else {
1193 /*
1194 * Put the data we've collected down into SRAM

--- 69 unchanged lines hidden (view full) ---

1264 ahc->our_id = sc.brtime_id & CFSCSIID;
1265
1266 scsi_conf = (ahc->our_id & 0x7);
1267 if (sc.adapter_control & CFSPARITY)
1268 scsi_conf |= ENSPCHK;
1269 if (sc.adapter_control & CFRESETB)
1270 scsi_conf |= RESET_SCSI;
1271
1298 if ((sc.adapter_control & CFCHNLBPRIMARY) != 0
1299 && (ahc->features & AHC_MULTI_FUNC) != 0)
1300 ahc->flags |= AHC_CHANNEL_B_PRIMARY;
1272 ahc->flags |=
1273 (sc.adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1301
1302 if (sc.bios_control & CFEXTEND)
1303 ahc->flags |= AHC_EXTENDED_TRANS_A;
1304
1305 if (sc.bios_control & CFBIOSEN)
1306 ahc->flags |= AHC_BIOS_ENABLED;
1307 if (ahc->features & AHC_ULTRA
1308 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1309 /* Should we enable Ultra mode? */
1310 if (!(sc.adapter_control & CFULTRAEN))
1311 /* Treat us as a non-ultra card */
1312 ultraenb = 0;
1313 }
1314
1274
1275 if (sc.bios_control & CFEXTEND)
1276 ahc->flags |= AHC_EXTENDED_TRANS_A;
1277
1278 if (sc.bios_control & CFBIOSEN)
1279 ahc->flags |= AHC_BIOS_ENABLED;
1280 if (ahc->features & AHC_ULTRA
1281 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1282 /* Should we enable Ultra mode? */
1283 if (!(sc.adapter_control & CFULTRAEN))
1284 /* Treat us as a non-ultra card */
1285 ultraenb = 0;
1286 }
1287
1315 if (sc.signature == CFSIGNATURE) {
1288 if (sc.signature == CFSIGNATURE
1289 || sc.signature == CFSIGNATURE2) {
1316 uint32_t devconfig;
1317
1318 /* Honor the STPWLEVEL settings */
1319 devconfig = ahc_pci_read_config(ahc->dev_softc,
1320 DEVCONFIG, /*bytes*/4);
1321 devconfig &= ~STPWLEVEL;
1322 if ((sc.bios_control & CFSTPWLEVEL) != 0)
1323 devconfig |= STPWLEVEL;

--- 27 unchanged lines hidden (view full) ---

1351 */
1352 if ((ahc->features & AHC_SPIOCAP) != 0) {
1353 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0)
1354 have_autoterm = TRUE;
1355 else
1356 have_autoterm = FALSE;
1357 }
1358
1290 uint32_t devconfig;
1291
1292 /* Honor the STPWLEVEL settings */
1293 devconfig = ahc_pci_read_config(ahc->dev_softc,
1294 DEVCONFIG, /*bytes*/4);
1295 devconfig &= ~STPWLEVEL;
1296 if ((sc.bios_control & CFSTPWLEVEL) != 0)
1297 devconfig |= STPWLEVEL;

--- 27 unchanged lines hidden (view full) ---

1325 */
1326 if ((ahc->features & AHC_SPIOCAP) != 0) {
1327 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0)
1328 have_autoterm = TRUE;
1329 else
1330 have_autoterm = FALSE;
1331 }
1332
1359 if (have_autoterm)
1333 if (have_autoterm) {
1334 acquire_seeprom(ahc, &sd);
1360 configure_termination(ahc, &sd, adapter_control, sxfrctl1);
1335 configure_termination(ahc, &sd, adapter_control, sxfrctl1);
1361
1362 release_seeprom(&sd);
1336 release_seeprom(&sd);
1337 }
1363}
1364
1365static void
1366configure_termination(struct ahc_softc *ahc,
1367 struct seeprom_descriptor *sd,
1368 u_int adapter_control,
1369 u_int *sxfrctl1)
1370{

--- 424 unchanged lines hidden (view full) ---

1795 }
1796 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1797 status1, /*bytes*/1);
1798
1799 if (status1 & (DPR|RMA|RTA)) {
1800 ahc_outb(ahc, CLRINT, CLRPARERR);
1801 }
1802
1338}
1339
1340static void
1341configure_termination(struct ahc_softc *ahc,
1342 struct seeprom_descriptor *sd,
1343 u_int adapter_control,
1344 u_int *sxfrctl1)
1345{

--- 424 unchanged lines hidden (view full) ---

1770 }
1771 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1772 status1, /*bytes*/1);
1773
1774 if (status1 & (DPR|RMA|RTA)) {
1775 ahc_outb(ahc, CLRINT, CLRPARERR);
1776 }
1777
1803 unpause_sequencer(ahc);
1778 ahc_unpause(ahc);
1804}
1805
1806static int
1779}
1780
1781static int
1807ahc_aic7850_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config)
1782ahc_aic785X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config)
1808{
1783{
1784 uint8_t rev;
1785
1809 probe_config->channel = 'A';
1810 probe_config->chip = AHC_AIC7850;
1811 probe_config->features = AHC_AIC7850_FE;
1812 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG
1813 | AHC_PCI_MWI_BUG;
1786 probe_config->channel = 'A';
1787 probe_config->chip = AHC_AIC7850;
1788 probe_config->features = AHC_AIC7850_FE;
1789 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG
1790 | AHC_PCI_MWI_BUG;
1791 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
1792 if (rev >= 1)
1793 probe_config->bugs |= AHC_PCI_2_1_RETRY_BUG;
1814 return (0);
1815}
1816
1817static int
1794 return (0);
1795}
1796
1797static int
1818ahc_aic7855_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config)
1819{
1820 probe_config->channel = 'A';
1821 probe_config->chip = AHC_AIC7855;
1822 probe_config->features = AHC_AIC7855_FE;
1823 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG
1824 | AHC_PCI_MWI_BUG;
1825 return (0);
1826}
1827
1828static int
1829ahc_aic7860_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config)
1830{
1831 uint8_t rev;
1832
1833 probe_config->channel = 'A';
1834 probe_config->chip = AHC_AIC7860;
1835 probe_config->features = AHC_AIC7860_FE;
1836 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG

--- 301 unchanged lines hidden --- 		1798ahc_aic7860_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config)
1799{
1800 uint8_t rev;
1801
1802 probe_config->channel = 'A';
1803 probe_config->chip = AHC_AIC7860;
1804 probe_config->features = AHC_AIC7860_FE;
1805 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG

--- 301 unchanged lines hidden ---