| aic7xxx_pci.c (107419) | aic7xxx_pci.c (107623) |
|---|---|
| 1/* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. --- 25 unchanged lines hidden (view full) --- 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * | 1/* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. --- 25 unchanged lines hidden (view full) --- 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * |
| 42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#52 $ | 42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#53 $ |
| 43 * | 43 * |
| 44 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx_pci.c 107419 2002-11-30 19:13:55Z scottl $ | 44 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx_pci.c 107623 2002-12-04 22:51:29Z scottl $ |
| 45 */ 46 47#ifdef __linux__ 48#include "aic7xxx_osm.h" 49#include "aic7xxx_inline.h" 50#include "aic7xxx_93cx6.h" 51#else 52#include <dev/aic7xxx/aic7xxx_osm.h> --- 1144 unchanged lines hidden (view full) --- 1197 1198/* 1199 * Perform some simple tests that should catch situations where 1200 * our registers are invalidly mapped. 1201 */ 1202int 1203ahc_pci_test_register_access(struct ahc_softc *ahc) 1204{ | 45 */ 46 47#ifdef __linux__ 48#include "aic7xxx_osm.h" 49#include "aic7xxx_inline.h" 50#include "aic7xxx_93cx6.h" 51#else 52#include <dev/aic7xxx/aic7xxx_osm.h> --- 1144 unchanged lines hidden (view full) --- 1197 1198/* 1199 * Perform some simple tests that should catch situations where 1200 * our registers are invalidly mapped. 1201 */ 1202int 1203ahc_pci_test_register_access(struct ahc_softc *ahc) 1204{ |
| 1205 int i; 1206 u_int status1; | 1205 int error; 1206 u_int status1; 1207 uint8_t seqctl; |
| 1207 | 1208 |
| 1209 error = EIO; 1210 1211 /* Enable PCI error interrupt status */ 1212 seqctl = ahc_inb(ahc, SEQCTL); 1213 ahc_outb(ahc, SEQCTL, seqctl & ~FAILDIS); 1214 |
|
| 1208 /* 1209 * First a simple test to see if any 1210 * registers can be read. Reading 1211 * HCNTRL has no side effects and has 1212 * at least one bit that is guaranteed to 1213 * be zero so it is a good register to 1214 * use for this test. 1215 */ 1216 if (ahc_inb(ahc, HCNTRL) == 0xFF) | 1215 /* 1216 * First a simple test to see if any 1217 * registers can be read. Reading 1218 * HCNTRL has no side effects and has 1219 * at least one bit that is guaranteed to 1220 * be zero so it is a good register to 1221 * use for this test. 1222 */ 1223 if (ahc_inb(ahc, HCNTRL) == 0xFF) |
| 1217 return (EIO); | 1224 goto fail; |
| 1218 1219 /* 1220 * Next create a situation where write combining 1221 * or read prefetching could be initiated by the 1222 * CPU or host bridge. Our device does not support 1223 * either, so look for data corruption and/or flagged 1224 * PCI errors. 1225 */ | 1225 1226 /* 1227 * Next create a situation where write combining 1228 * or read prefetching could be initiated by the 1229 * CPU or host bridge. Our device does not support 1230 * either, so look for data corruption and/or flagged 1231 * PCI errors. 1232 */ |
| 1226 for (i = 0; i < 16; i++) 1227 ahc_outb(ahc, SRAM_BASE + i, i); | 1233 ahc_outb(ahc, SRAM_BASE, 0xaa); 1234 ahc_outb(ahc, SRAM_BASE + 1, 0x55); 1235 ahc_outb(ahc, SRAM_BASE + 2, 0xa5); 1236 ahc_outb(ahc, SRAM_BASE + 3, 0x5a); |
| 1228 | 1237 |
| 1229 for (i = 0; i < 16; i++) 1230 if (ahc_inb(ahc, SRAM_BASE + i) != i) 1231 return (EIO); | 1238 if ((ahc_inb(ahc, SRAM_BASE) != 0xaa) 1239 || (ahc_inb(ahc, SRAM_BASE + 1) != 0x55) 1240 || (ahc_inb(ahc, SRAM_BASE + 2) != 0xa5) 1241 || (ahc_inb(ahc, SRAM_BASE + 3) != 0x5a)) 1242 goto fail; |
| 1232 1233 status1 = ahc_pci_read_config(ahc->dev_softc, 1234 PCIR_STATUS + 1, /*bytes*/1); | 1243 1244 status1 = ahc_pci_read_config(ahc->dev_softc, 1245 PCIR_STATUS + 1, /*bytes*/1); |
| 1235 if ((status1 & STA) != 0) { | 1246 if ((status1 & STA) != 0) 1247 goto fail; |
| 1236 | 1248 |
| 1237 /* Silently clear any latched errors. */ 1238 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1239 status1, /*bytes*/1); 1240 ahc_outb(ahc, CLRINT, CLRPARERR); 1241 return (EIO); 1242 } | 1249 error = 0; |
| 1243 | 1250 |
| 1244 return (0); | 1251fail: 1252 /* Silently clear any latched errors. */ 1253 status1 = ahc_pci_read_config(ahc->dev_softc, 1254 PCIR_STATUS + 1, /*bytes*/1); 1255 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1256 status1, /*bytes*/1); 1257 ahc_outb(ahc, CLRINT, CLRPARERR); 1258 ahc_outb(ahc, SEQCTL, seqctl); 1259 return (error); |
| 1245} 1246 1247/* 1248 * Check the external port logic for a serial eeprom 1249 * and termination/cable detection contrls. 1250 */ 1251static void 1252check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) --- 1059 unchanged lines hidden --- | 1260} 1261 1262/* 1263 * Check the external port logic for a serial eeprom 1264 * and termination/cable detection contrls. 1265 */ 1266static void 1267check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) --- 1059 unchanged lines hidden --- |