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aic7xxx.seq (22234) aic7xxx.seq (22451)
1/*+M***********************************************************************
2 *Adaptec 274x/284x/294x device driver for Linux and FreeBSD.
3 *
4 *Copyright (c) 1994 John Aycock
5 * The University of Calgary Department of Computer Science.
6 * All rights reserved.
7 *
8 *FreeBSD, Twin, Wide, 2 command per target support, tagged queuing,

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34 *OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 *HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 *OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 *SUCH DAMAGE.
39 *
40 *-M************************************************************************/
41
1/*+M***********************************************************************
2 *Adaptec 274x/284x/294x device driver for Linux and FreeBSD.
3 *
4 *Copyright (c) 1994 John Aycock
5 * The University of Calgary Department of Computer Science.
6 * All rights reserved.
7 *
8 *FreeBSD, Twin, Wide, 2 command per target support, tagged queuing,

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34 *OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 *HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 *OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 *SUCH DAMAGE.
39 *
40 *-M************************************************************************/
41
42VERSION AIC7XXX_SEQ_VER "$FreeBSD: head/sys/dev/aic7xxx/aic7xxx.seq 22234 1997-02-03 02:02:04Z gibbs $"
42VERSION AIC7XXX_SEQ_VER "$FreeBSD: head/sys/dev/aic7xxx/aic7xxx.seq 22451 1997-02-09 03:23:28Z gibbs $"
43
44#if defined(__NetBSD__)
45#include "../../../../dev/ic/aic7xxxreg.h"
46#include "../../../../scsi/scsi_message.h"
47#elif defined(__FreeBSD__)
48#include "../../dev/aic7xxx/aic7xxx_reg.h"
49#include "../../scsi/scsi_message.h"
50#endif

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79 * We assume that the kernel driver may reset us at any time, even in the
80 * middle of a DMA, so clear DFCNTRL too.
81 */
82reset:
83 clr DFCNTRL
84 clr SCSISIGO /* De-assert BSY */
85
86p_busfree:
43
44#if defined(__NetBSD__)
45#include "../../../../dev/ic/aic7xxxreg.h"
46#include "../../../../scsi/scsi_message.h"
47#elif defined(__FreeBSD__)
48#include "../../dev/aic7xxx/aic7xxx_reg.h"
49#include "../../scsi/scsi_message.h"
50#endif

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79 * We assume that the kernel driver may reset us at any time, even in the
80 * middle of a DMA, so clear DFCNTRL too.
81 */
82reset:
83 clr DFCNTRL
84 clr SCSISIGO /* De-assert BSY */
85
86p_busfree:
87 or SXFRCTL0, CLRCHN
88 clr SCSIRATE /*
89 * We don't know the target we will
90 * connect to, so default to narrow
91 * transfers to avoid parity problems.
92 */
87 clr SCSIRATE /*
88 * We don't know the target we will
89 * connect to, so default to narrow
90 * transfers to avoid parity problems.
91 */
92 and SXFRCTL0, 0xdf /* ~FAST20*/
93 mvi SCSISEQ,ENRSELI /* Always allow reselection */
94 mvi LASTPHASE, P_BUSFREE
95 and FLAGS,0x07 /* clear target specific flags */
96poll_for_work:
97 /*
98 * Are we a twin channel device?
99 * For fairness, we check the other bus first,
100 * since we just finished a transaction on the

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286 mvi CLRSINT1,CLRBUSFREE
287 or SIMODE1, ENBUSFREE /*
288 * We aren't expecting a
289 * bus free, so interrupt
290 * the kernel driver if it
291 * happens.
292 */
293/*
93 mvi SCSISEQ,ENRSELI /* Always allow reselection */
94 mvi LASTPHASE, P_BUSFREE
95 and FLAGS,0x07 /* clear target specific flags */
96poll_for_work:
97 /*
98 * Are we a twin channel device?
99 * For fairness, we check the other bus first,
100 * since we just finished a transaction on the

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286 mvi CLRSINT1,CLRBUSFREE
287 or SIMODE1, ENBUSFREE /*
288 * We aren't expecting a
289 * bus free, so interrupt
290 * the kernel driver if it
291 * happens.
292 */
293/*
294 * Initialize Ultra mode setting and clear the SCSI channel.
295 */
296 or SXFRCTL0, 0x1a /* CLRSTCNT|SPIOEN|CLRCHN */
297ultra:
298 mvi SINDEX, ULTRA_ENB_B
299 test SAVED_TCL, 0x80 jnz ultra_2 /* Target ID > 7 */
300 test SBLKCTL, SELBUSB jnz ultra_2 /* Second channel */
301 dec SINDEX
302ultra_2:
303 mov FUNCTION1,SAVED_TCL
304 mov A,FUNCTION1
305 test SINDIR, A jz ndx_dtr
306 or SXFRCTL0, FAST20
307
308/*
294 * Initialize SCSIRATE with the appropriate value for this target.
295 * The SCSIRATE settings for each target are stored in an array
296 * based at TARG_SCRATCH.
297 */
298ndx_dtr:
299 shr A,SAVED_TCL,4
300 test SBLKCTL,SELBUSB jz ndx_dtr_2
301 or SAVED_TCL, SELBUSB /* Add the channel bit while we're here */
302 or A,0x08 /* Channel B entries add 8 */
303ndx_dtr_2:
304 add SINDEX,TARG_SCRATCH,A
305 mov SCSIRATE,SINDIR
306
309 * Initialize SCSIRATE with the appropriate value for this target.
310 * The SCSIRATE settings for each target are stored in an array
311 * based at TARG_SCRATCH.
312 */
313ndx_dtr:
314 shr A,SAVED_TCL,4
315 test SBLKCTL,SELBUSB jz ndx_dtr_2
316 or SAVED_TCL, SELBUSB /* Add the channel bit while we're here */
317 or A,0x08 /* Channel B entries add 8 */
318ndx_dtr_2:
319 add SINDEX,TARG_SCRATCH,A
320 mov SCSIRATE,SINDIR
321
307/*
308 * Initialize Ultra mode setting and clear the SCSI channel.
309 */
310ultra:
311 and DINDEX,0xdf,SXFRCTL0 /* default to Ultra disabled */
312 mvi SINDEX, ULTRA_ENB_B
313 test SAVED_TCL, 0x80 jnz ultra_2 /* Target ID > 7 */
314 test SBLKCTL, SELBUSB jnz ultra_2 /* Second channel device */
315 dec SINDEX
316ultra_2:
317 mov FUNCTION1,SAVED_TCL
318 mov A,FUNCTION1
319 test SINDIR, A jz set_sxfrctl0
320 or DINDEX, ULTRAEN
321
322set_sxfrctl0:
323 mov SXFRCTL0,DINDEX
324
325/*
326 * Main loop for information transfer phases. If BSY is false, then
327 * we have a bus free condition, expected or not. Otherwise, wait
328 * for the target to assert REQ before checking MSG, C/D and I/O
329 * for the bus phase.
330 *
331 */
332ITloop:
322
323/*
324 * Main loop for information transfer phases. If BSY is false, then
325 * we have a bus free condition, expected or not. Otherwise, wait
326 * for the target to assert REQ before checking MSG, C/D and I/O
327 * for the bus phase.
328 *
329 */
330ITloop:
331 test SSTAT1,0x9 jz ITloop /* REQINIT|BUSFREE */
333 test SSTAT1,BUSFREE jnz p_busfree
332 test SSTAT1,BUSFREE jnz p_busfree
334 test SSTAT1,REQINIT jz ITloop
335
336 and A,PHASE_MASK,SCSISIGI
337 mov LASTPHASE,A
338 mov SCSISIGO,A
339
340 cmp ALLZEROS,A je p_dataout
341 cmp A,P_DATAIN je p_datain
342 cmp A,P_COMMAND je p_command

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400 test SG_COUNT, 0xff jnz data_phase_inbounds
401/*
402 * Turn on 'Bit Bucket' mode, set the transfer count to
403 * 16meg and let the target run until it changes phase.
404 * When the transfer completes, notify the host that we
405 * had an overrun.
406 */
407 or SXFRCTL1,BITBUCKET
333
334 and A,PHASE_MASK,SCSISIGI
335 mov LASTPHASE,A
336 mov SCSISIGO,A
337
338 cmp ALLZEROS,A je p_dataout
339 cmp A,P_DATAIN je p_datain
340 cmp A,P_COMMAND je p_command

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398 test SG_COUNT, 0xff jnz data_phase_inbounds
399/*
400 * Turn on 'Bit Bucket' mode, set the transfer count to
401 * 16meg and let the target run until it changes phase.
402 * When the transfer completes, notify the host that we
403 * had an overrun.
404 */
405 or SXFRCTL1,BITBUCKET
408 and DMAPARAMS, 0xf7 /* Turn off HDMAEN */
409 mvi STCNT0,0xff
410 mvi STCNT1,0xff
411 mvi STCNT2,0xff
406 mvi HCNT0, 0xff
407 mvi HCNT1, 0xff
408 mvi HCNT2, 0xff
409 call set_stcnt_from_hcnt
412
413data_phase_inbounds:
414/* If we are the last SG block, ensure wideodd is off. */
415 cmp SG_COUNT,0x01 jne data_phase_wideodd
416 and DMAPARAMS, 0xbf /* Turn off WIDEODD */
417data_phase_wideodd:
418 mov DMAPARAMS call dma
419
420/* Go tell the host about any overruns */
421 test SXFRCTL1,BITBUCKET jnz data_phase_overrun
422
410
411data_phase_inbounds:
412/* If we are the last SG block, ensure wideodd is off. */
413 cmp SG_COUNT,0x01 jne data_phase_wideodd
414 and DMAPARAMS, 0xbf /* Turn off WIDEODD */
415data_phase_wideodd:
416 mov DMAPARAMS call dma
417
418/* Go tell the host about any overruns */
419 test SXFRCTL1,BITBUCKET jnz data_phase_overrun
420
423/* Exit if we had an underrun */
424 test SSTAT0,SDONE jz data_phase_finish /* underrun STCNT != 0 */
421/* Exit if we had an underrun. dma clears SINDEX in this case. */
422 test SINDEX,0xff jz data_phase_finish
425
426/*
427 * Advance the scatter-gather pointers if needed
428 */
429sg_advance:
430 dec SG_COUNT /* one less segment to go */
431
432 test SG_COUNT, 0xff jz data_phase_finish /* Are we done? */

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583
584 test A,MSG_IDENTIFYFLAG jnz mesgin_identify
585 cmp A,MSG_DISCONNECT je mesgin_disconnect
586 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs
587 cmp ALLZEROS,A je mesgin_complete
588 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs
589 cmp A,MSG_EXTENDED je mesgin_extended
590 cmp A,MSG_MESSAGE_REJECT je mesgin_reject
423
424/*
425 * Advance the scatter-gather pointers if needed
426 */
427sg_advance:
428 dec SG_COUNT /* one less segment to go */
429
430 test SG_COUNT, 0xff jz data_phase_finish /* Are we done? */

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581
582 test A,MSG_IDENTIFYFLAG jnz mesgin_identify
583 cmp A,MSG_DISCONNECT je mesgin_disconnect
584 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs
585 cmp ALLZEROS,A je mesgin_complete
586 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs
587 cmp A,MSG_EXTENDED je mesgin_extended
588 cmp A,MSG_MESSAGE_REJECT je mesgin_reject
589 cmp A,MSG_NOOP je mesgin_done
591
592rej_mesgin:
593/*
594 * We have no idea what this message in is, so we issue a message reject
595 * and hope for the best. In any case, rejection should be a rare
596 * occurrence - signal the driver when it happens.
597 */
598 mvi INTSTAT,SEND_REJECT /* let driver know */
599
600 mvi MSG_MESSAGE_REJECT call mk_mesg
601
602mesgin_done:
590
591rej_mesgin:
592/*
593 * We have no idea what this message in is, so we issue a message reject
594 * and hope for the best. In any case, rejection should be a rare
595 * occurrence - signal the driver when it happens.
596 */
597 mvi INTSTAT,SEND_REJECT /* let driver know */
598
599 mvi MSG_MESSAGE_REJECT call mk_mesg
600
601mesgin_done:
603 call inb_last /*ack & turn auto PIO back on*/
602 call inb_last
604 jmp ITloop
605
606
607mesgin_complete:
608/*
609 * We got a "command complete" message, so put the SCB_TAG into the QOUTFIFO,
610 * and trigger a completion interrupt. Before doing so, check to see if there
611 * is a residual or the status byte is something other than NO_ERROR (0). In

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906 * host->scsi, or 0x39 for scsi->host. The SCSI channel is cleared
907 * during initialization.
908 */
909dma:
910 mov DFCNTRL,SINDEX
911dma1:
912 test SSTAT0,DMADONE jnz dma3
913 test SSTAT1,PHASEMIS jz dma1 /* ie. underrun */
603 jmp ITloop
604
605
606mesgin_complete:
607/*
608 * We got a "command complete" message, so put the SCB_TAG into the QOUTFIFO,
609 * and trigger a completion interrupt. Before doing so, check to see if there
610 * is a residual or the status byte is something other than NO_ERROR (0). In

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905 * host->scsi, or 0x39 for scsi->host. The SCSI channel is cleared
906 * during initialization.
907 */
908dma:
909 mov DFCNTRL,SINDEX
910dma1:
911 test SSTAT0,DMADONE jnz dma3
912 test SSTAT1,PHASEMIS jz dma1 /* ie. underrun */
913 test SSTAT0,SDONE jnz dma3
914 mov SINDEX,ALLZEROS /* Notify caller of phasemiss */
914
915/*
916 * We will be "done" DMAing when the transfer count goes to zero, or
917 * the target changes the phase (in light of this, it makes sense that
918 * the DMA circuitry doesn't ACK when PHASEMIS is active). If we are
919 * doing a SCSI->Host transfer, the data FIFO should be flushed auto-
920 * magically on STCNT=0 or a phase change, so just wait for FIFO empty
921 * status.
922 */
923dma3:
915
916/*
917 * We will be "done" DMAing when the transfer count goes to zero, or
918 * the target changes the phase (in light of this, it makes sense that
919 * the DMA circuitry doesn't ACK when PHASEMIS is active). If we are
920 * doing a SCSI->Host transfer, the data FIFO should be flushed auto-
921 * magically on STCNT=0 or a phase change, so just wait for FIFO empty
922 * status.
923 */
924dma3:
924 test SINDEX,DIRECTION jnz dma5
925 test DFCNTRL,DIRECTION jnz dma5
925dma4:
926 test DFSTATUS,FIFOEMP jz dma4
927
928/*
929 * Now shut the DMA enables off and make sure that the DMA enables are
930 * actually off first lest we get an ILLSADDR.
931 */
932dma5:
933 /* Don't clobber an inprogress host data transfer */
934 test DFSTATUS, MREQPEND jnz dma5
935 /* disable DMA */
926dma4:
927 test DFSTATUS,FIFOEMP jz dma4
928
929/*
930 * Now shut the DMA enables off and make sure that the DMA enables are
931 * actually off first lest we get an ILLSADDR.
932 */
933dma5:
934 /* Don't clobber an inprogress host data transfer */
935 test DFSTATUS, MREQPEND jnz dma5
936 /* disable DMA */
936 and DFCNTRL, 0xc7 /* ~(SCSIEN|SDMAEN|HDMAEN|DIRECTION) */
937 and DFCNTRL, 0xc7 /* ~(SCSIEN|SDMAEN|HDMAEN) */
937dma6:
938dma6:
938 test DFCNTRL, 0x38 jnz dma6 /* (SCSIEN|SDMAEN|HDMAEN|DIRECTION) */
939 test DFCNTRL, 0x38 jnz dma6 /* (SCSIEN|SDMAEN|HDMAEN) */
939return:
940 ret
941
942/*
943 * Common SCSI initialization for selection and reselection. Expects
944 * the target SCSI ID to be in the upper four bits of SINDEX, and A's
945 * contents are stomped on return.
946 */

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940return:
941 ret
942
943/*
944 * Common SCSI initialization for selection and reselection. Expects
945 * the target SCSI ID to be in the upper four bits of SINDEX, and A's
946 * contents are stomped on return.
947 */

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