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aic7xxx.reg (54211) aic7xxx.reg (55581)
1/*
2 * Aic7xxx register and scratch ram definitions.
3 *
1/*
2 * Aic7xxx register and scratch ram definitions.
3 *
4 * Copyright (c) 1994-1999 Justin Gibbs.
4 * Copyright (c) 1994-2000 Justin Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.

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23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.

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23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.reg 54211 1999-12-06 18:23:31Z gibbs $
31 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.reg 55581 2000-01-07 23:08:20Z gibbs $
32 */
33
34/*
35 * This file is processed by the aic7xxx_asm utility for use in assembling
36 * firmware for the aic7xxx family of SCSI host adapters as well as to generate
37 * a C header file for use in the kernel portion of the Aic7xxx driver.
38 *
39 * All page numbers refer to the Adaptec AIC-7770 Data Book available from

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151 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the
152 * SOFS (3:0) bits disables synchronous data transfers. Any offset value
153 * greater than 0 enables synchronous transfers.
154 */
155register SCSIRATE {
156 address 0x004
157 access_mode RW
158 bit WIDEXFER 0x80 /* Wide transfer control */
32 */
33
34/*
35 * This file is processed by the aic7xxx_asm utility for use in assembling
36 * firmware for the aic7xxx family of SCSI host adapters as well as to generate
37 * a C header file for use in the kernel portion of the Aic7xxx driver.
38 *
39 * All page numbers refer to the Adaptec AIC-7770 Data Book available from

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151 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the
152 * SOFS (3:0) bits disables synchronous data transfers. Any offset value
153 * greater than 0 enables synchronous transfers.
154 */
155register SCSIRATE {
156 address 0x004
157 access_mode RW
158 bit WIDEXFER 0x80 /* Wide transfer control */
159 bit ENABLE_CRC 0x40 /* CRC for D-Phases */
160 bit SINGLE_EDGE 0x10 /* Disable DT Transfers */
159 mask SXFR 0x70 /* Sync transfer rate */
161 mask SXFR 0x70 /* Sync transfer rate */
160 mask SXFR_ULTRA2 0x7f /* Sync transfer rate */
162 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */
161 mask SOFS 0x0f /* Sync offset */
162}
163
164/*
165 * SCSI ID (p. 3-18).
166 * Contains the ID of the board and the current target on the
167 * selected channel.
168 */

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204 * set when STCNT goes to 0
205 */
206register STCNT {
207 address 0x008
208 size 3
209 access_mode RW
210}
211
163 mask SOFS 0x0f /* Sync offset */
164}
165
166/*
167 * SCSI ID (p. 3-18).
168 * Contains the ID of the board and the current target on the
169 * selected channel.
170 */

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206 * set when STCNT goes to 0
207 */
208register STCNT {
209 address 0x008
210 size 3
211 access_mode RW
212}
213
214/* ALT_MODE register on Ultra160 chips */
215register OPTIONMODE {
216 address 0x008
217 access_mode RW
218 bit AUTORATEEN 0x80
219 bit AUTOACKEN 0x40
220 bit ATNMGMNTEN 0x20
221 bit BUSFREEREV 0x10
222 bit EXPPHASEDIS 0x08
223 bit SCSIDATL_IMGEN 0x04
224 bit AUTO_MSGOUT_DE 0x02
225 bit DIS_MSGIN_DUALEDGE 0x01
226 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE
227}
228
229/* ALT_MODE register on Ultra160 chips */
230register TARGCRCCNT {
231 address 0x00a
232 size 2
233 access_mode RW
234}
235
212/*
213 * Clear SCSI Interrupt 0 (p. 3-20)
214 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
215 */
216register CLRSINT0 {
217 address 0x00b
218 access_mode WO
219 bit CLRSELDO 0x40

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391 */
392register SELID {
393 address 0x019
394 access_mode RW
395 mask SELID_MASK 0xf0
396 bit ONEBIT 0x08
397}
398
236/*
237 * Clear SCSI Interrupt 0 (p. 3-20)
238 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
239 */
240register CLRSINT0 {
241 address 0x00b
242 access_mode WO
243 bit CLRSELDO 0x40

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415 */
416register SELID {
417 address 0x019
418 access_mode RW
419 mask SELID_MASK 0xf0
420 bit ONEBIT 0x08
421}
422
423register SCAMCTL {
424 address 0x01a
425 access_mode RW
426 bit ENSCAMSELO 0x80
427 bit CLRSCAMSELID 0x40
428 bit ALTSTIM 0x20
429 bit DFLTTID 0x10
430 mask SCAMLVL 0x03
431}
432
399/*
400 * Target Mode Selecting in ID bitmask (aic7890/91/96/97)
401 */
402register TARGID {
403 address 0x01b
404 size 2
405 access_mode RW
406}

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869 * Queue Out FIFO (p. 3-61)
870 * Queue of SCBs that have completed and await the host
871 */
872register QOUTFIFO {
873 address 0x09d
874 access_mode WO
875}
876
433/*
434 * Target Mode Selecting in ID bitmask (aic7890/91/96/97)
435 */
436register TARGID {
437 address 0x01b
438 size 2
439 access_mode RW
440}

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903 * Queue Out FIFO (p. 3-61)
904 * Queue of SCBs that have completed and await the host
905 */
906register QOUTFIFO {
907 address 0x09d
908 access_mode WO
909}
910
911register CRCCONTROL1 {
912 address 0x09d
913 access_mode RW
914 bit CRCONSEEN 0x80
915 bit CRCVALCHKEN 0x40
916 bit CRCENDCHKEN 0x20
917 bit CRCREQCHKEN 0x10
918 bit TARGCRCENDEN 0x08
919 bit TARGCRCCNTEN 0x04
920}
921
922
877/*
878 * Queue Out Count (p. 3-61)
879 * Number of queued SCBs in the Out FIFO
880 */
881register QOUTCNT {
882 address 0x09e
883 access_mode RO
884}
885
923/*
924 * Queue Out Count (p. 3-61)
925 * Number of queued SCBs in the Out FIFO
926 */
927register QOUTCNT {
928 address 0x09e
929 access_mode RO
930}
931
932register SCSIPHASE {
933 address 0x09e
934 access_mode RO
935 bit STATUS_PHASE 0x20
936 bit COMMAND_PHASE 0x10
937 bit MSG_IN_PHASE 0x08
938 bit MSG_OUT_PHASE 0x04
939 bit DATA_IN_PHASE 0x02
940 bit DATA_OUT_PHASE 0x01
941}
942
886/*
887 * Special Function
888 */
889register SFUNCT {
890 address 0x09f
891 access_mode RW
943/*
944 * Special Function
945 */
946register SFUNCT {
947 address 0x09f
948 access_mode RW
949 bit ALT_MODE 0x80
892}
893
894/*
895 * SCB Definition (p. 5-4)
896 */
897scb {
898 address 0x0a0
899 SCB_CONTROL {

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951
952/*
953 * SCB Definition (p. 5-4)
954 */
955scb {
956 address 0x0a0
957 SCB_CONTROL {

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