| aic7xxx.h (72325) | aic7xxx.h (72640) |
|---|---|
| 1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 16 unchanged lines hidden (view full) --- 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: //depot/src/aic7xxx/aic7xxx.h#18 $ 32 * | 1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 16 unchanged lines hidden (view full) --- 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: //depot/src/aic7xxx/aic7xxx.h#18 $ 32 * |
| 33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.h 72325 2001-02-10 18:04:27Z gibbs $ | 33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.h 72640 2001-02-18 10:25:42Z asmodai $ |
| 34 */ 35 36#ifndef _AIC7XXX_H_ 37#define _AIC7XXX_H_ 38 39/* Register Definitions */ 40#include "aic7xxx_reg.h" 41 --- 95 unchanged lines hidden (view full) --- 137 * 3) Our input queue scheme requires one SCB to always be reserved 138 * in advance of queuing any SCBs. This takes us down to 254. 139 * 4) To handle our output queue correctly on machines that only 140 * support 32bit stores, we must clear the array 4 bytes at a 141 * time. To avoid colliding with a DMA write from the sequencer, 142 * we must be sure that 4 slots are empty when we write to clear 143 * the queue. This reduces us to 253 SCBs: 1 that just completed 144 * and the known three additional empty slots in the queue that | 34 */ 35 36#ifndef _AIC7XXX_H_ 37#define _AIC7XXX_H_ 38 39/* Register Definitions */ 40#include "aic7xxx_reg.h" 41 --- 95 unchanged lines hidden (view full) --- 137 * 3) Our input queue scheme requires one SCB to always be reserved 138 * in advance of queuing any SCBs. This takes us down to 254. 139 * 4) To handle our output queue correctly on machines that only 140 * support 32bit stores, we must clear the array 4 bytes at a 141 * time. To avoid colliding with a DMA write from the sequencer, 142 * we must be sure that 4 slots are empty when we write to clear 143 * the queue. This reduces us to 253 SCBs: 1 that just completed 144 * and the known three additional empty slots in the queue that |
| 145 * preceed it. | 145 * precede it. |
| 146 */ 147#define AHC_MAX_QUEUE 253 148 149/* 150 * Ring Buffer of incoming target commands. 151 * We allocate 256 to simplify the logic in the sequencer 152 * by using the natural wrap point of an 8bit counter. 153 */ --- 1043 unchanged lines hidden --- | 146 */ 147#define AHC_MAX_QUEUE 253 148 149/* 150 * Ring Buffer of incoming target commands. 151 * We allocate 256 to simplify the logic in the sequencer 152 * by using the natural wrap point of an 8bit counter. 153 */ --- 1043 unchanged lines hidden --- |