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aic7xxx.h (54211) aic7xxx.h (55581)
1/*
2 * Interface to the generic driver for the aic7xxx based adaptec
3 * SCSI controllers. This is used to implement product specific
4 * probe and attach routines.
5 *
1/*
2 * Interface to the generic driver for the aic7xxx based adaptec
3 * SCSI controllers. This is used to implement product specific
4 * probe and attach routines.
5 *
6 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999 Justin T. Gibbs.
6 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.

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25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.

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25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.h 54211 1999-12-06 18:23:31Z gibbs $
33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.h 55581 2000-01-07 23:08:20Z gibbs $
34 */
35
36#ifndef _AIC7XXX_H_
37#define _AIC7XXX_H_
38
39#include "ahc.h" /* for NAHC from config */
40#include "opt_aic7xxx.h" /* for config options */
41

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91 AHC_AIC7770 = 0x0001,
92 AHC_AIC7850 = 0x0002,
93 AHC_AIC7855 = 0x0003,
94 AHC_AIC7859 = 0x0004,
95 AHC_AIC7860 = 0x0005,
96 AHC_AIC7870 = 0x0006,
97 AHC_AIC7880 = 0x0007,
98 AHC_AIC7890 = 0x0008,
34 */
35
36#ifndef _AIC7XXX_H_
37#define _AIC7XXX_H_
38
39#include "ahc.h" /* for NAHC from config */
40#include "opt_aic7xxx.h" /* for config options */
41

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91 AHC_AIC7770 = 0x0001,
92 AHC_AIC7850 = 0x0002,
93 AHC_AIC7855 = 0x0003,
94 AHC_AIC7859 = 0x0004,
95 AHC_AIC7860 = 0x0005,
96 AHC_AIC7870 = 0x0006,
97 AHC_AIC7880 = 0x0007,
98 AHC_AIC7890 = 0x0008,
99 AHC_AIC7895 = 0x0009,
100 AHC_AIC7896 = 0x000a,
99 AHC_AIC7892 = 0x0009,
100 AHC_AIC7895 = 0x000a,
101 AHC_AIC7896 = 0x000b,
102 AHC_AIC7899 = 0x000c,
101 AHC_VL = 0x0100, /* Bus type VL */
102 AHC_EISA = 0x0200, /* Bus type EISA */
103 AHC_PCI = 0x0400, /* Bus type PCI */
104 AHC_BUS_MASK = 0x0F00
105} ahc_chip;
106
103 AHC_VL = 0x0100, /* Bus type VL */
104 AHC_EISA = 0x0200, /* Bus type EISA */
105 AHC_PCI = 0x0400, /* Bus type PCI */
106 AHC_BUS_MASK = 0x0F00
107} ahc_chip;
108
109extern char *ahc_chip_names[];
110
107typedef enum {
108 AHC_FENONE = 0x0000,
109 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */
110 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */
111 AHC_WIDE = 0x0004, /* Wide Channel */
112 AHC_TWIN = 0x0008, /* Twin Channel */
113 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */
114 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */
115 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */
116 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */
117 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */
118 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */
119 AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */
111typedef enum {
112 AHC_FENONE = 0x0000,
113 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */
114 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */
115 AHC_WIDE = 0x0004, /* Wide Channel */
116 AHC_TWIN = 0x0008, /* Twin Channel */
117 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */
118 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */
119 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */
120 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */
121 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */
122 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */
123 AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */
120 AHC_AIC7770_FE = AHC_FENONE,
121 AHC_AIC7850_FE = AHC_FENONE|AHC_SPIOCAP,
122 AHC_AIC7855_FE = AHC_FENONE|AHC_SPIOCAP,
123 AHC_AIC7859_FE = AHC_ULTRA|AHC_SPIOCAP,
124 AHC_AIC7860_FE = AHC_ULTRA|AHC_SPIOCAP,
124 AHC_DT = 0x0800, /* Double Transition transfers */
125 AHC_NEW_TERMCTL = 0x1000,
126 AHC_MULTI_FUNC = 0x2000, /* Multi-Function Twin Channel Device */
127 AHC_AIC7770_FE = AHC_FENONE,
128 AHC_AIC7850_FE = AHC_SPIOCAP,
129 AHC_AIC7855_FE = AHC_AIC7850_FE,
130 AHC_AIC7859_FE = AHC_AIC7850_FE|AHC_ULTRA,
131 AHC_AIC7860_FE = AHC_AIC7859_FE,
125 AHC_AIC7870_FE = AHC_FENONE,
126 AHC_AIC7880_FE = AHC_ULTRA,
127 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS
132 AHC_AIC7870_FE = AHC_FENONE,
133 AHC_AIC7880_FE = AHC_ULTRA,
134 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS
128 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX,
129 AHC_AIC7895_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA,
130 AHC_AIC7895C_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA|AHC_MULTI_TID,
131 AHC_AIC7896_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS
132 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX
135 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX
136 |AHC_NEW_TERMCTL,
137 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT,
138 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM
139 |AHC_CMD_CHAN|AHC_MULTI_FUNC,
140 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID,
141 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC,
142 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC
133} ahc_feature;
134
135typedef enum {
136 AHC_FNONE = 0x000,
137 AHC_PAGESCBS = 0x001,/* Enable SCB paging */
138 AHC_CHANNEL_B_PRIMARY = 0x002,/*
139 * On twin channel adapters, probe
140 * channel B first since it is the

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160 */
161 AHC_TARGETMODE = 0x2000,/*
162 * Allow target operations on this
163 * controller.
164 */
165 AHC_NEWEEPROM_FMT = 0x4000,
166 AHC_RESOURCE_SHORTAGE = 0x8000,
167 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */
143} ahc_feature;
144
145typedef enum {
146 AHC_FNONE = 0x000,
147 AHC_PAGESCBS = 0x001,/* Enable SCB paging */
148 AHC_CHANNEL_B_PRIMARY = 0x002,/*
149 * On twin channel adapters, probe
150 * channel B first since it is the

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170 */
171 AHC_TARGETMODE = 0x2000,/*
172 * Allow target operations on this
173 * controller.
174 */
175 AHC_NEWEEPROM_FMT = 0x4000,
176 AHC_RESOURCE_SHORTAGE = 0x8000,
177 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */
178 AHC_INT50_SPEEDFLEX = 0x20000,/*
179 * Internal 50pin connector
180 * sits behind an aic3860
181 */
168} ahc_flag;
169
170typedef enum {
171 SCB_FREE = 0x0000,
172 SCB_OTHERTCL_TIMEOUT = 0x0002,/*
173 * Another device was active
174 * during the first timeout for
175 * this SCB so we gave ourselves

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290#define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */
291#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */
292#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */
293
294struct ahc_transinfo {
295 u_int8_t width;
296 u_int8_t period;
297 u_int8_t offset;
182} ahc_flag;
183
184typedef enum {
185 SCB_FREE = 0x0000,
186 SCB_OTHERTCL_TIMEOUT = 0x0002,/*
187 * Another device was active
188 * during the first timeout for
189 * this SCB so we gave ourselves

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304#define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */
305#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */
306#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */
307
308struct ahc_transinfo {
309 u_int8_t width;
310 u_int8_t period;
311 u_int8_t offset;
312 u_int8_t ppr_flags;
298};
299
300struct ahc_initiator_tinfo {
301 u_int8_t scsirate;
302 struct ahc_transinfo current;
303 struct ahc_transinfo goal;
304 struct ahc_transinfo user;
305};

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318 * Per initiator state bitmasks.
319 */
320 u_int16_t ultraenb; /* Using ultra sync rate */
321 u_int16_t discenable; /* Disconnection allowed */
322 u_int16_t tagenable; /* Tagged Queuing allowed */
323};
324
325/*
313};
314
315struct ahc_initiator_tinfo {
316 u_int8_t scsirate;
317 struct ahc_transinfo current;
318 struct ahc_transinfo goal;
319 struct ahc_transinfo user;
320};

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333 * Per initiator state bitmasks.
334 */
335 u_int16_t ultraenb; /* Using ultra sync rate */
336 u_int16_t discenable; /* Disconnection allowed */
337 u_int16_t tagenable; /* Tagged Queuing allowed */
338};
339
340/*
326 * Define the format of the aic7XX0 SEEPROM registers (16 bits).
341 * Define the format of the aic7XXX SEEPROM registers (16 bits).
327 */
328
329struct seeprom_config {
330/*
331 * SCSI ID Configuration Flags
332 */
333 u_int16_t device_flags[16]; /* words 0-15 */
334#define CFXFER 0x0007 /* synchronous transfer rate */
335#define CFSYNCH 0x0008 /* enable synchronous transfer */
336#define CFDISC 0x0010 /* enable disconnection */
337#define CFWIDEB 0x0020 /* wide bus device */
338#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/
342 */
343
344struct seeprom_config {
345/*
346 * SCSI ID Configuration Flags
347 */
348 u_int16_t device_flags[16]; /* words 0-15 */
349#define CFXFER 0x0007 /* synchronous transfer rate */
350#define CFSYNCH 0x0008 /* enable synchronous transfer */
351#define CFDISC 0x0010 /* enable disconnection */
352#define CFWIDEB 0x0020 /* wide bus device */
353#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/
339/* UNUSED 0x0080 */
354#define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */
340#define CFSTART 0x0100 /* send start unit SCSI command */
341#define CFINCBIOS 0x0200 /* include in BIOS scan */
342#define CFRNFOUND 0x0400 /* report even if not found */
343#define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */
355#define CFSTART 0x0100 /* send start unit SCSI command */
356#define CFINCBIOS 0x0200 /* include in BIOS scan */
357#define CFRNFOUND 0x0400 /* report even if not found */
358#define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */
344/* UNUSED 0xf000 */
359#define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */
360#define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */
345
346/*
347 * BIOS Control Bits
348 */
349 u_int16_t bios_control; /* word 16 */
350#define CFSUPREM 0x0001 /* support all removeable drives */
361
362/*
363 * BIOS Control Bits
364 */
365 u_int16_t bios_control; /* word 16 */
366#define CFSUPREM 0x0001 /* support all removeable drives */
351#define CFSUPREMB 0x0002 /* support removeable drives for boot only */
367#define CFSUPREMB 0x0002 /* support removeable boot drives */
352#define CFBIOSEN 0x0004 /* BIOS enabled */
353/* UNUSED 0x0008 */
354#define CFSM2DRV 0x0010 /* support more than two drives */
355#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */
368#define CFBIOSEN 0x0004 /* BIOS enabled */
369/* UNUSED 0x0008 */
370#define CFSM2DRV 0x0010 /* support more than two drives */
371#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */
356/* UNUSED 0x0060 */
372/* UNUSED 0x0040 */
357#define CFEXTEND 0x0080 /* extended translation enabled */
358/* UNUSED 0xff00 */
359
360/*
361 * Host Adapter Control Bits
362 */
363 u_int16_t adapter_control; /* word 17 */
364#define CFAUTOTERM 0x0001 /* Perform Auto termination */
365#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */
366#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */
367#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */
368#define CFSTERM 0x0004 /* SCSI low byte termination */
369#define CFWSTERM 0x0008 /* SCSI high byte termination */
370#define CFSPARITY 0x0010 /* SCSI parity */
371#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */
372#define CFRESETB 0x0040 /* reset SCSI bus at boot */
373#define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */
374#define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/
375#define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */
373#define CFEXTEND 0x0080 /* extended translation enabled */
374/* UNUSED 0xff00 */
375
376/*
377 * Host Adapter Control Bits
378 */
379 u_int16_t adapter_control; /* word 17 */
380#define CFAUTOTERM 0x0001 /* Perform Auto termination */
381#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */
382#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */
383#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */
384#define CFSTERM 0x0004 /* SCSI low byte termination */
385#define CFWSTERM 0x0008 /* SCSI high byte termination */
386#define CFSPARITY 0x0010 /* SCSI parity */
387#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */
388#define CFRESETB 0x0040 /* reset SCSI bus at boot */
389#define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */
390#define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/
391#define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */
376/* UNUSED 0xf080 */
392/* UNUSED 0xf280 */
377
378/*
379 * Bus Release, Host Adapter ID
380 */
381 u_int16_t brtime_id; /* word 18 */
382#define CFSCSIID 0x000f /* host adapter SCSI ID */
383/* UNUSED 0x00f0 */
384#define CFBRTIME 0xff00 /* bus release time */

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389 u_int16_t max_targets; /* word 19 */
390#define CFMAXTARG 0x00ff /* maximum targets */
391/* UNUSED 0xff00 */
392 u_int16_t res_1[11]; /* words 20-30 */
393 u_int16_t checksum; /* word 31 */
394};
395
396struct ahc_syncrate {
393
394/*
395 * Bus Release, Host Adapter ID
396 */
397 u_int16_t brtime_id; /* word 18 */
398#define CFSCSIID 0x000f /* host adapter SCSI ID */
399/* UNUSED 0x00f0 */
400#define CFBRTIME 0xff00 /* bus release time */

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405 u_int16_t max_targets; /* word 19 */
406#define CFMAXTARG 0x00ff /* maximum targets */
407/* UNUSED 0xff00 */
408 u_int16_t res_1[11]; /* words 20-30 */
409 u_int16_t checksum; /* word 31 */
410};
411
412struct ahc_syncrate {
397 int sxfr_ultra2;
413 int sxfr_u2;
398 int sxfr;
399 /* Rates in Ultra mode have bit 8 of sxfr set */
400#define ULTRA_SXFR 0x100
414 int sxfr;
415 /* Rates in Ultra mode have bit 8 of sxfr set */
416#define ULTRA_SXFR 0x100
417#define ST_SXFR 0x010
401 u_int8_t period; /* Period to send to SCSI target */
402 char *rate;
403};
404
405typedef enum {
406 MSG_TYPE_NONE = 0x00,
407 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
408 MSG_TYPE_INITIATOR_MSGIN = 0x02,

--- 204 unchanged lines hidden --- 		418 u_int8_t period; /* Period to send to SCSI target */
419 char *rate;
420};
421
422typedef enum {
423 MSG_TYPE_NONE = 0x00,
424 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
425 MSG_TYPE_INITIATOR_MSGIN = 0x02,

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