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aic7xxx.h (107420) aic7xxx.h (109590)
1/*
2 * Core definitions and data structures shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without

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32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
1/*
2 * Core definitions and data structures shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without

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32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#62 $
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#70 $
41 *
41 *
42 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.h 107420 2002-11-30 19:30:09Z scottl $
42 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.h 109590 2003-01-20 20:44:55Z gibbs $
43 */
44
45#ifndef _AIC7XXX_H_
46#define _AIC7XXX_H_
47
48/* Register Definitions */
49#include "aic7xxx_reg.h"
50

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93#define SCB_GET_CHANNEL(ahc, scb) \
94 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid)
95#define SCB_GET_LUN(scb) \
96 ((scb)->hscb->lun)
97#define SCB_GET_TARGET_OFFSET(ahc, scb) \
98 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0))
99#define SCB_GET_TARGET_MASK(ahc, scb) \
100 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb)))
43 */
44
45#ifndef _AIC7XXX_H_
46#define _AIC7XXX_H_
47
48/* Register Definitions */
49#include "aic7xxx_reg.h"
50

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93#define SCB_GET_CHANNEL(ahc, scb) \
94 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid)
95#define SCB_GET_LUN(scb) \
96 ((scb)->hscb->lun)
97#define SCB_GET_TARGET_OFFSET(ahc, scb) \
98 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0))
99#define SCB_GET_TARGET_MASK(ahc, scb) \
100 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb)))
101#ifdef AHC_DEBUG
102#define SCB_IS_SILENT(scb) \
103 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \
104 && (((scb)->flags & SCB_SILENT) != 0))
105#else
106#define SCB_IS_SILENT(scb) \
107 (((scb)->flags & SCB_SILENT) != 0)
108#endif
101#define TCL_TARGET_OFFSET(tcl) \
102 ((((tcl) >> 4) & TID) >> 4)
103#define TCL_LUN(tcl) \
104 (tcl & (AHC_NUM_LUNS - 1))
105#define BUILD_TCL(scsiid, lun) \
106 ((lun) | (((scsiid) & TID) << 4))
107
108#ifndef AHC_TARGET_MODE

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305
306/*
307 * Configuration specific settings.
308 * The driver determines these settings by probing the
309 * chip/controller's configuration.
310 */
311typedef enum {
312 AHC_FNONE = 0x000,
109#define TCL_TARGET_OFFSET(tcl) \
110 ((((tcl) >> 4) & TID) >> 4)
111#define TCL_LUN(tcl) \
112 (tcl & (AHC_NUM_LUNS - 1))
113#define BUILD_TCL(scsiid, lun) \
114 ((lun) | (((scsiid) & TID) << 4))
115
116#ifndef AHC_TARGET_MODE

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313
314/*
315 * Configuration specific settings.
316 * The driver determines these settings by probing the
317 * chip/controller's configuration.
318 */
319typedef enum {
320 AHC_FNONE = 0x000,
313 AHC_PRIMARY_CHANNEL = 0x003,/*
321 AHC_PRIMARY_CHANNEL = 0x003, /*
314 * The channel that should
315 * be probed first.
316 */
322 * The channel that should
323 * be probed first.
324 */
317 AHC_USEDEFAULTS = 0x004,/*
325 AHC_USEDEFAULTS = 0x004, /*
318 * For cards without an seeprom
319 * or a BIOS to initialize the chip's
320 * SRAM, we use the default target
321 * settings.
322 */
323 AHC_SEQUENCER_DEBUG = 0x008,
324 AHC_SHARED_SRAM = 0x010,
326 * For cards without an seeprom
327 * or a BIOS to initialize the chip's
328 * SRAM, we use the default target
329 * settings.
330 */
331 AHC_SEQUENCER_DEBUG = 0x008,
332 AHC_SHARED_SRAM = 0x010,
325 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */
333 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */
326 AHC_RESET_BUS_A = 0x040,
327 AHC_RESET_BUS_B = 0x080,
328 AHC_EXTENDED_TRANS_A = 0x100,
329 AHC_EXTENDED_TRANS_B = 0x200,
330 AHC_TERM_ENB_A = 0x400,
331 AHC_TERM_ENB_B = 0x800,
334 AHC_RESET_BUS_A = 0x040,
335 AHC_RESET_BUS_B = 0x080,
336 AHC_EXTENDED_TRANS_A = 0x100,
337 AHC_EXTENDED_TRANS_B = 0x200,
338 AHC_TERM_ENB_A = 0x400,
339 AHC_TERM_ENB_B = 0x800,
332 AHC_INITIATORROLE = 0x1000,/*
340 AHC_INITIATORROLE = 0x1000, /*
333 * Allow initiator operations on
334 * this controller.
335 */
341 * Allow initiator operations on
342 * this controller.
343 */
336 AHC_TARGETROLE = 0x2000,/*
344 AHC_TARGETROLE = 0x2000, /*
337 * Allow target operations on this
338 * controller.
339 */
340 AHC_NEWEEPROM_FMT = 0x4000,
341 AHC_RESOURCE_SHORTAGE = 0x8000,
345 * Allow target operations on this
346 * controller.
347 */
348 AHC_NEWEEPROM_FMT = 0x4000,
349 AHC_RESOURCE_SHORTAGE = 0x8000,
342 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */
343 AHC_INT50_SPEEDFLEX = 0x20000,/*
350 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */
351 AHC_INT50_SPEEDFLEX = 0x20000, /*
344 * Internal 50pin connector
345 * sits behind an aic3860
346 */
352 * Internal 50pin connector
353 * sits behind an aic3860
354 */
347 AHC_SCB_BTT = 0x40000,/*
355 AHC_SCB_BTT = 0x40000, /*
348 * The busy targets table is
349 * stored in SCB space rather
350 * than SRAM.
351 */
352 AHC_BIOS_ENABLED = 0x80000,
353 AHC_ALL_INTERRUPTS = 0x100000,
354 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */
355 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */
356 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */
357 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */
356 * The busy targets table is
357 * stored in SCB space rather
358 * than SRAM.
359 */
360 AHC_BIOS_ENABLED = 0x80000,
361 AHC_ALL_INTERRUPTS = 0x100000,
362 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */
363 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */
364 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */
365 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */
358 AHC_SCB_CONFIG_USED = 0x4000000 /* No SEEPROM but SCB2 had info. */
366 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */
367 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */
368 AHC_DISABLE_PCI_PERR = 0x10000000
359} ahc_flag;
360
361/************************* Hardware SCB Definition ***************************/
362
363/*
364 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
365 * consists of a "hardware SCB" mirroring the fields availible on the card
366 * and additional information the kernel stores for each transaction.

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543 * error that has effected the
544 * payload of the command. This
545 * flag is checked when normal
546 * status is returned to catch
547 * the case of a target not
548 * responding to our attempt
549 * to report the error.
550 */
369} ahc_flag;
370
371/************************* Hardware SCB Definition ***************************/
372
373/*
374 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
375 * consists of a "hardware SCB" mirroring the fields availible on the card
376 * and additional information the kernel stores for each transaction.

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553 * error that has effected the
554 * payload of the command. This
555 * flag is checked when normal
556 * status is returned to catch
557 * the case of a target not
558 * responding to our attempt
559 * to report the error.
560 */
551 SCB_TARGET_SCB = 0x2000
561 SCB_TARGET_SCB = 0x2000,
562 SCB_SILENT = 0x4000 /*
563 * Be quiet about transmission type
564 * errors. They are expected and we
565 * don't want to upset the user. This
566 * flag is typically used during DV.
567 */
552} scb_flag;
553
554struct scb {
555 struct hardware_scb *hscb;
556 union {
557 SLIST_ENTRY(scb) sle;
558 TAILQ_ENTRY(scb) tqe;
559 } links;

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728#define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */
729#define ST_SXFR 0x010 /* Rate Single Transition Only */
730#define DT_SXFR 0x040 /* Rate Double Transition Only */
731 uint8_t period; /* Period to send to SCSI target */
732 char *rate;
733};
734
735/* Safe and valid period for async negotiations. */
568} scb_flag;
569
570struct scb {
571 struct hardware_scb *hscb;
572 union {
573 SLIST_ENTRY(scb) sle;
574 TAILQ_ENTRY(scb) tqe;
575 } links;

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744#define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */
745#define ST_SXFR 0x010 /* Rate Single Transition Only */
746#define DT_SXFR 0x040 /* Rate Double Transition Only */
747 uint8_t period; /* Period to send to SCSI target */
748 char *rate;
749};
750
751/* Safe and valid period for async negotiations. */
736#define AHC_ASYNC_XFER_PERIOD 0x44
752#define AHC_ASYNC_XFER_PERIOD 0x45
737#define AHC_ULTRA2_XFER_PERIOD 0x0a
738
739/*
740 * Indexes into our table of syncronous transfer rates.
741 */
742#define AHC_SYNCRATE_DT 0
743#define AHC_SYNCRATE_ULTRA2 1
744#define AHC_SYNCRATE_ULTRA 3
745#define AHC_SYNCRATE_FAST 6
753#define AHC_ULTRA2_XFER_PERIOD 0x0a
754
755/*
756 * Indexes into our table of syncronous transfer rates.
757 */
758#define AHC_SYNCRATE_DT 0
759#define AHC_SYNCRATE_ULTRA2 1
760#define AHC_SYNCRATE_ULTRA 3
761#define AHC_SYNCRATE_FAST 6
762#define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT
763#define AHC_SYNCRATE_MIN 13
746
747/***************************** Lookup Tables **********************************/
748/*
749 * Phase -> name and message out response
750 * to parity errors in each phase table.
751 */
752struct ahc_phase_table_entry {
753 uint8_t phase;

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1033
1034 /* Initialization level of this data structure */
1035 u_int init_level;
1036
1037 /* PCI cacheline size. */
1038 u_int pci_cachesize;
1039
1040 u_int stack_size;
764
765/***************************** Lookup Tables **********************************/
766/*
767 * Phase -> name and message out response
768 * to parity errors in each phase table.
769 */
770struct ahc_phase_table_entry {
771 uint8_t phase;

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1051
1052 /* Initialization level of this data structure */
1053 u_int init_level;
1054
1055 /* PCI cacheline size. */
1056 u_int pci_cachesize;
1057
1058 u_int stack_size;
1041 uint16_t *saved_stack;
1042
1043 /* Per-Unit descriptive information */
1044 const char *description;
1045 char *name;
1046 int unit;
1047
1048 /* Selection Timer settings */
1049 int seltime;

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1268#define AHC_SHOW_TERMCTL 0x0008
1269#define AHC_SHOW_MEMORY 0x0010
1270#define AHC_SHOW_MESSAGES 0x0020
1271#define AHC_SHOW_DV 0x0040
1272#define AHC_SHOW_SELTO 0x0080
1273#define AHC_SHOW_QFULL 0x0200
1274#define AHC_SHOW_QUEUE 0x0400
1275#define AHC_SHOW_TQIN 0x0800
1059
1060 /* Per-Unit descriptive information */
1061 const char *description;
1062 char *name;
1063 int unit;
1064
1065 /* Selection Timer settings */
1066 int seltime;

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1285#define AHC_SHOW_TERMCTL 0x0008
1286#define AHC_SHOW_MEMORY 0x0010
1287#define AHC_SHOW_MESSAGES 0x0020
1288#define AHC_SHOW_DV 0x0040
1289#define AHC_SHOW_SELTO 0x0080
1290#define AHC_SHOW_QFULL 0x0200
1291#define AHC_SHOW_QUEUE 0x0400
1292#define AHC_SHOW_TQIN 0x0800
1276#define AHC_DEBUG_SEQUENCER 0x1000
1293#define AHC_SHOW_MASKED_ERRORS 0x1000
1294#define AHC_DEBUG_SEQUENCER 0x2000
1277#endif
1278void ahc_print_scb(struct scb *scb);
1279void ahc_print_devinfo(struct ahc_softc *ahc,
1280 struct ahc_devinfo *dev);
1281void ahc_dump_card_state(struct ahc_softc *ahc);
1282int ahc_print_register(ahc_reg_parse_entry_t *table,
1283 u_int num_entries,
1284 const char *name,
1285 u_int address,
1286 u_int value,
1287 u_int *cur_column,
1288 u_int wrap_point);
1289/******************************* SEEPROM *************************************/
1290int ahc_acquire_seeprom(struct ahc_softc *ahc,
1291 struct seeprom_descriptor *sd);
1292void ahc_release_seeprom(struct seeprom_descriptor *sd);
1293#endif /* _AIC7XXX_H_ */
1295#endif
1296void ahc_print_scb(struct scb *scb);
1297void ahc_print_devinfo(struct ahc_softc *ahc,
1298 struct ahc_devinfo *dev);
1299void ahc_dump_card_state(struct ahc_softc *ahc);
1300int ahc_print_register(ahc_reg_parse_entry_t *table,
1301 u_int num_entries,
1302 const char *name,
1303 u_int address,
1304 u_int value,
1305 u_int *cur_column,
1306 u_int wrap_point);
1307/******************************* SEEPROM *************************************/
1308int ahc_acquire_seeprom(struct ahc_softc *ahc,
1309 struct seeprom_descriptor *sd);
1310void ahc_release_seeprom(struct seeprom_descriptor *sd);
1311#endif /* _AIC7XXX_H_ */