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aic7xxx.c (72811) aic7xxx.c (74094)
1/*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
1/*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $Id: //depot/src/aic7xxx/aic7xxx.c#30 $
31 * $Id: //depot/src/aic7xxx/aic7xxx.c#34 $
32 *
32 *
33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.c 72811 2001-02-21 20:50:36Z gibbs $
33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.c 74094 2001-03-11 06:34:17Z gibbs $
34 */
35
36#ifdef __linux__
37#include "aic7xxx_linux.h"
38#include "aic7xxx_inline.h"
39#include "aicasm/aicasm_insformat.h"
40#endif
41

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61 "aic7880",
62 "aic7895",
63 "aic7895C",
64 "aic7890/91",
65 "aic7896/97",
66 "aic7892",
67 "aic7899"
68};
34 */
35
36#ifdef __linux__
37#include "aic7xxx_linux.h"
38#include "aic7xxx_inline.h"
39#include "aicasm/aicasm_insformat.h"
40#endif
41

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61 "aic7880",
62 "aic7895",
63 "aic7895C",
64 "aic7890/91",
65 "aic7896/97",
66 "aic7892",
67 "aic7899"
68};
69const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names);
69static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names);
70
70
71struct hard_error_entry hard_error[] = {
71/*
72 * Hardware error codes.
73 */
74struct ahc_hard_error_entry {
75 uint8_t errno;
76 char *errmesg;
77};
78
79static struct ahc_hard_error_entry ahc_hard_errors[] = {
72 { ILLHADDR, "Illegal Host Access" },
73 { ILLSADDR, "Illegal Sequencer Address referrenced" },
74 { ILLOPCODE, "Illegal Opcode in sequencer program" },
75 { SQPARERR, "Sequencer Parity Error" },
76 { DPARERR, "Data-path Parity Error" },
77 { MPARERR, "Scratch or SCB Memory Parity Error" },
78 { PCIERRSTAT, "PCI Error detected" },
79 { CIOPARERR, "CIOBUS Parity Error" },
80};
80 { ILLHADDR, "Illegal Host Access" },
81 { ILLSADDR, "Illegal Sequencer Address referrenced" },
82 { ILLOPCODE, "Illegal Opcode in sequencer program" },
83 { SQPARERR, "Sequencer Parity Error" },
84 { DPARERR, "Data-path Parity Error" },
85 { MPARERR, "Scratch or SCB Memory Parity Error" },
86 { PCIERRSTAT, "PCI Error detected" },
87 { CIOPARERR, "CIOBUS Parity Error" },
88};
81const u_int num_errors = NUM_ELEMENTS(hard_error);
89static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
82
90
83struct phase_table_entry phase_table[] =
91static struct ahc_phase_table_entry ahc_phase_table[] =
84{
85 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
86 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
87 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
88 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
89 { P_COMMAND, MSG_NOOP, "in Command phase" },
90 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
91 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
92 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
93 { P_BUSFREE, MSG_NOOP, "while idle" },
94 { 0, MSG_NOOP, "in unknown phase" }
95};
96
97/*
98 * In most cases we only wish to itterate over real phases, so
99 * exclude the last element from the count.
100 */
92{
93 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
94 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
95 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
96 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
97 { P_COMMAND, MSG_NOOP, "in Command phase" },
98 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
99 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
100 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
101 { P_BUSFREE, MSG_NOOP, "while idle" },
102 { 0, MSG_NOOP, "in unknown phase" }
103};
104
105/*
106 * In most cases we only wish to itterate over real phases, so
107 * exclude the last element from the count.
108 */
101const u_int num_phases = NUM_ELEMENTS(phase_table) - 1;
109static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
102
103/*
104 * Valid SCSIRATE values. (p. 3-17)
105 * Provides a mapping of tranfer periods in ns to the proper value to
106 * stick in the scsixfer reg.
107 */
110
111/*
112 * Valid SCSIRATE values. (p. 3-17)
113 * Provides a mapping of tranfer periods in ns to the proper value to
114 * stick in the scsixfer reg.
115 */
108struct ahc_syncrate ahc_syncrates[] =
116static struct ahc_syncrate ahc_syncrates[] =
109{
110 /* ultra2 fast/ultra period rate */
111 { 0x42, 0x000, 9, "80.0" },
112 { 0x03, 0x000, 10, "40.0" },
113 { 0x04, 0x000, 11, "33.0" },
114 { 0x05, 0x100, 12, "20.0" },
115 { 0x06, 0x110, 15, "16.0" },
116 { 0x07, 0x120, 18, "13.4" },

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221static int ahc_handle_target_cmd(struct ahc_softc *ahc,
222 struct target_cmd *cmd);
223#endif
224/************************* Sequencer Execution Control ************************/
225/*
226 * Restart the sequencer program from address zero
227 */
228void
117{
118 /* ultra2 fast/ultra period rate */
119 { 0x42, 0x000, 9, "80.0" },
120 { 0x03, 0x000, 10, "40.0" },
121 { 0x04, 0x000, 11, "33.0" },
122 { 0x05, 0x100, 12, "20.0" },
123 { 0x06, 0x110, 15, "16.0" },
124 { 0x07, 0x120, 18, "13.4" },

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229static int ahc_handle_target_cmd(struct ahc_softc *ahc,
230 struct target_cmd *cmd);
231#endif
232/************************* Sequencer Execution Control ************************/
233/*
234 * Restart the sequencer program from address zero
235 */
236void
229restart_sequencer(struct ahc_softc *ahc)
237ahc_restart(struct ahc_softc *ahc)
230{
231
238{
239
232 pause_sequencer(ahc);
240 ahc_pause(ahc);
241
233 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
234 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
235 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
236
237 /*
238 * Ensure that the sequencer's idea of TQINPOS
239 * matches our own. The sequencer increments TQINPOS
240 * only after it sees a DMA complete and a reset could

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247 ahc_outb(ahc, SCSISEQ,
248 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
249 if ((ahc->features & AHC_CMD_CHAN) != 0) {
250 /* Ensure that no DMA operations are in progress */
251 ahc_outb(ahc, CCSCBCNT, 0);
252 ahc_outb(ahc, CCSGCTL, 0);
253 ahc_outb(ahc, CCSCBCTL, 0);
254 }
242 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
243 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
244 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
245
246 /*
247 * Ensure that the sequencer's idea of TQINPOS
248 * matches our own. The sequencer increments TQINPOS
249 * only after it sees a DMA complete and a reset could

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256 ahc_outb(ahc, SCSISEQ,
257 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
258 if ((ahc->features & AHC_CMD_CHAN) != 0) {
259 /* Ensure that no DMA operations are in progress */
260 ahc_outb(ahc, CCSCBCNT, 0);
261 ahc_outb(ahc, CCSGCTL, 0);
262 ahc_outb(ahc, CCSCBCTL, 0);
263 }
264 /*
265 * If we were in the process of DMA'ing SCB data into
266 * an SCB, replace that SCB on the free list. This prevents
267 * an SCB leak.
268 */
269 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
270 ahc_add_curscb_to_free_list(ahc);
271 ahc_outb(ahc, SEQ_FLAGS2,
272 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
273 }
255 ahc_outb(ahc, MWI_RESIDUAL, 0);
256 ahc_outb(ahc, SEQCTL, FASTMODE);
257 ahc_outb(ahc, SEQADDR0, 0);
258 ahc_outb(ahc, SEQADDR1, 0);
274 ahc_outb(ahc, MWI_RESIDUAL, 0);
275 ahc_outb(ahc, SEQCTL, FASTMODE);
276 ahc_outb(ahc, SEQADDR0, 0);
277 ahc_outb(ahc, SEQADDR1, 0);
259 unpause_sequencer(ahc);
278 ahc_unpause(ahc);
260}
261
262/************************* Input/Output Queues ********************************/
263void
264ahc_run_qoutfifo(struct ahc_softc *ahc)
265{
266 struct scb *scb;
267 u_int scb_index;

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332/************************* Interrupt Handling *********************************/
333void
334ahc_handle_brkadrint(struct ahc_softc *ahc)
335{
336 /*
337 * We upset the sequencer :-(
338 * Lookup the error message
339 */
279}
280
281/************************* Input/Output Queues ********************************/
282void
283ahc_run_qoutfifo(struct ahc_softc *ahc)
284{
285 struct scb *scb;
286 u_int scb_index;

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351/************************* Interrupt Handling *********************************/
352void
353ahc_handle_brkadrint(struct ahc_softc *ahc)
354{
355 /*
356 * We upset the sequencer :-(
357 * Lookup the error message
358 */
340 int i, error, num_errors;
359 int i;
360 int error;
341
342 error = ahc_inb(ahc, ERROR);
361
362 error = ahc_inb(ahc, ERROR);
343 num_errors = sizeof(hard_error)/sizeof(hard_error[0]);
344 for (i = 0; error != 1 && i < num_errors; i++)
345 error >>= 1;
346 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
363 for (i = 0; error != 1 && i < num_errors; i++)
364 error >>= 1;
365 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
347 ahc_name(ahc), hard_error[i].errmesg,
366 ahc_name(ahc), ahc_hard_errors[i].errmesg,
348 ahc_inb(ahc, SEQADDR0) |
349 (ahc_inb(ahc, SEQADDR1) << 8));
350
351 ahc_dump_card_state(ahc);
352
353 /* Tell everyone that this HBA is no longer availible */
354 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
355 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,

--- 269 unchanged lines hidden (view full) ---

625 {
626 u_int lastphase;
627
628 lastphase = ahc_inb(ahc, LASTPHASE);
629 printf("%s:%c:%d: Missed busfree. "
630 "Lastphase = 0x%x, Curphase = 0x%x\n",
631 ahc_name(ahc), devinfo.channel, devinfo.target,
632 lastphase, ahc_inb(ahc, SCSISIGI));
367 ahc_inb(ahc, SEQADDR0) |
368 (ahc_inb(ahc, SEQADDR1) << 8));
369
370 ahc_dump_card_state(ahc);
371
372 /* Tell everyone that this HBA is no longer availible */
373 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
374 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,

--- 269 unchanged lines hidden (view full) ---

644 {
645 u_int lastphase;
646
647 lastphase = ahc_inb(ahc, LASTPHASE);
648 printf("%s:%c:%d: Missed busfree. "
649 "Lastphase = 0x%x, Curphase = 0x%x\n",
650 ahc_name(ahc), devinfo.channel, devinfo.target,
651 lastphase, ahc_inb(ahc, SCSISIGI));
633 restart_sequencer(ahc);
652 ahc_restart(ahc);
634 return;
635 }
636 case HOST_MSG_LOOP:
637 {
638 /*
639 * The sequencer has encountered a message phase
640 * that requires host assistance for completion.
641 * While handling the message phase(s), we will be

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655 printf("ahc_intr: HOST_MSG_LOOP bad "
656 "phase 0x%x\n",
657 bus_phase);
658 /*
659 * Probably transitioned to bus free before
660 * we got here. Just punt the message.
661 */
662 ahc_clear_intstat(ahc);
653 return;
654 }
655 case HOST_MSG_LOOP:
656 {
657 /*
658 * The sequencer has encountered a message phase
659 * that requires host assistance for completion.
660 * While handling the message phase(s), we will be

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674 printf("ahc_intr: HOST_MSG_LOOP bad "
675 "phase 0x%x\n",
676 bus_phase);
677 /*
678 * Probably transitioned to bus free before
679 * we got here. Just punt the message.
680 */
681 ahc_clear_intstat(ahc);
663 restart_sequencer(ahc);
682 ahc_restart(ahc);
664 return;
665 }
666
667 if (devinfo.role == ROLE_INITIATOR) {
668 struct scb *scb;
669 u_int scb_index;
670
671 scb_index = ahc_inb(ahc, SCB_TAG);

--- 69 unchanged lines hidden (view full) ---

741 * no way of knowing how large the overrun was.
742 */
743 u_int scbindex = ahc_inb(ahc, SCB_TAG);
744 u_int lastphase = ahc_inb(ahc, LASTPHASE);
745 u_int i;
746
747 scb = ahc_lookup_scb(ahc, scbindex);
748 for (i = 0; i < num_phases; i++) {
683 return;
684 }
685
686 if (devinfo.role == ROLE_INITIATOR) {
687 struct scb *scb;
688 u_int scb_index;
689
690 scb_index = ahc_inb(ahc, SCB_TAG);

--- 69 unchanged lines hidden (view full) ---

760 * no way of knowing how large the overrun was.
761 */
762 u_int scbindex = ahc_inb(ahc, SCB_TAG);
763 u_int lastphase = ahc_inb(ahc, LASTPHASE);
764 u_int i;
765
766 scb = ahc_lookup_scb(ahc, scbindex);
767 for (i = 0; i < num_phases; i++) {
749 if (lastphase == phase_table[i].phase)
768 if (lastphase == ahc_phase_table[i].phase)
750 break;
751 }
752 ahc_print_path(ahc, scb);
753 printf("data overrun detected %s."
754 " Tag == 0x%x.\n",
769 break;
770 }
771 ahc_print_path(ahc, scb);
772 printf("data overrun detected %s."
773 " Tag == 0x%x.\n",
755 phase_table[i].phasemsg,
774 ahc_phase_table[i].phasemsg,
756 scb->hscb->tag);
757 ahc_print_path(ahc, scb);
758 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
759 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
760 ahc_get_transfer_length(scb), scb->sg_count);
761 if (scb->sg_count > 0) {
762 for (i = 0; i < scb->sg_count; i++) {
763 printf("sg[%d] - Addr 0x%x : Length %d\n",

--- 86 unchanged lines hidden (view full) ---

850 break;
851 }
852unpause:
853 /*
854 * The sequencer is paused immediately on
855 * a SEQINT, so we should restart it when
856 * we're done.
857 */
775 scb->hscb->tag);
776 ahc_print_path(ahc, scb);
777 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
778 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
779 ahc_get_transfer_length(scb), scb->sg_count);
780 if (scb->sg_count > 0) {
781 for (i = 0; i < scb->sg_count; i++) {
782 printf("sg[%d] - Addr 0x%x : Length %d\n",

--- 86 unchanged lines hidden (view full) ---

869 break;
870 }
871unpause:
872 /*
873 * The sequencer is paused immediately on
874 * a SEQINT, so we should restart it when
875 * we're done.
876 */
858 unpause_sequencer(ahc);
877 ahc_unpause(ahc);
859}
860
861void
862ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
863{
864 u_int scb_index;
865 u_int status0;
866 u_int status;

--- 22 unchanged lines hidden (view full) ---

889 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
890 status = ahc_inb(ahc, SSTAT1)
891 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
892 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
893 }
894 if (status == 0) {
895 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
896 ahc_outb(ahc, CLRINT, CLRSCSIINT);
878}
879
880void
881ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
882{
883 u_int scb_index;
884 u_int status0;
885 u_int status;

--- 22 unchanged lines hidden (view full) ---

908 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
909 status = ahc_inb(ahc, SSTAT1)
910 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
911 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
912 }
913 if (status == 0) {
914 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
915 ahc_outb(ahc, CLRINT, CLRSCSIINT);
897 unpause_sequencer(ahc);
916 ahc_unpause(ahc);
898 return;
899 }
900 }
901
902 scb_index = ahc_inb(ahc, SCB_TAG);
903 scb = ahc_lookup_scb(ahc, scb_index);
904 if (scb != NULL
905 && (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0)

--- 61 unchanged lines hidden (view full) ---

967 */
968 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
969 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
970 errorphase = curphase;
971 else
972 errorphase = lastphase;
973
974 for (i = 0; i < num_phases; i++) {
917 return;
918 }
919 }
920
921 scb_index = ahc_inb(ahc, SCB_TAG);
922 scb = ahc_lookup_scb(ahc, scb_index);
923 if (scb != NULL
924 && (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0)

--- 61 unchanged lines hidden (view full) ---

986 */
987 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
988 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
989 errorphase = curphase;
990 else
991 errorphase = lastphase;
992
993 for (i = 0; i < num_phases; i++) {
975 if (errorphase == phase_table[i].phase)
994 if (errorphase == ahc_phase_table[i].phase)
976 break;
977 }
995 break;
996 }
978 mesg_out = phase_table[i].mesg_out;
997 mesg_out = ahc_phase_table[i].mesg_out;
979 if (scb != NULL)
980 ahc_print_path(ahc, scb);
981 else
982 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
983 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
984 scsirate = ahc_inb(ahc, SCSIRATE);
985 printf("parity error detected %s. "
986 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
998 if (scb != NULL)
999 ahc_print_path(ahc, scb);
1000 else
1001 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1002 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1003 scsirate = ahc_inb(ahc, SCSIRATE);
1004 printf("parity error detected %s. "
1005 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
987 phase_table[i].phasemsg,
1006 ahc_phase_table[i].phasemsg,
988 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8),
989 scsirate);
990
991 if ((ahc->features & AHC_DT) != 0) {
992
993 if ((sstat2 & CRCVALERR) != 0)
994 printf("\tCRC Value Mismatch\n");
995 if ((sstat2 & CRCENDERR) != 0)

--- 14 unchanged lines hidden (view full) ---

1010 */
1011 if (mesg_out != MSG_NOOP) {
1012 if (ahc->msg_type != MSG_TYPE_NONE)
1013 ahc->send_msg_perror = TRUE;
1014 else
1015 ahc_outb(ahc, MSG_OUT, mesg_out);
1016 }
1017 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1007 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8),
1008 scsirate);
1009
1010 if ((ahc->features & AHC_DT) != 0) {
1011
1012 if ((sstat2 & CRCVALERR) != 0)
1013 printf("\tCRC Value Mismatch\n");
1014 if ((sstat2 & CRCENDERR) != 0)

--- 14 unchanged lines hidden (view full) ---

1029 */
1030 if (mesg_out != MSG_NOOP) {
1031 if (ahc->msg_type != MSG_TYPE_NONE)
1032 ahc->send_msg_perror = TRUE;
1033 else
1034 ahc_outb(ahc, MSG_OUT, mesg_out);
1035 }
1036 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1018 unpause_sequencer(ahc);
1037 ahc_unpause(ahc);
1019 } else if ((status & BUSFREE) != 0
1020 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1021 u_int lastphase;
1022 u_int saved_scsiid;
1023 u_int saved_lun;
1024 u_int target;
1025 u_int initiator_role_id;
1026 char channel;

--- 139 unchanged lines hidden (view full) ---

1166 } else {
1167 /*
1168 * We had not fully identified this connection,
1169 * so we cannot abort anything.
1170 */
1171 printf("%s: ", ahc_name(ahc));
1172 }
1173 for (i = 0; i < num_phases; i++) {
1038 } else if ((status & BUSFREE) != 0
1039 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1040 u_int lastphase;
1041 u_int saved_scsiid;
1042 u_int saved_lun;
1043 u_int target;
1044 u_int initiator_role_id;
1045 char channel;

--- 139 unchanged lines hidden (view full) ---

1185 } else {
1186 /*
1187 * We had not fully identified this connection,
1188 * so we cannot abort anything.
1189 */
1190 printf("%s: ", ahc_name(ahc));
1191 }
1192 for (i = 0; i < num_phases; i++) {
1174 if (lastphase == phase_table[i].phase)
1193 if (lastphase == ahc_phase_table[i].phase)
1175 break;
1176 }
1177 printf("Unexpected busfree %s\n"
1178 "SEQADDR == 0x%x\n",
1194 break;
1195 }
1196 printf("Unexpected busfree %s\n"
1197 "SEQADDR == 0x%x\n",
1179 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0)
1198 ahc_phase_table[i].phasemsg,
1199 ahc_inb(ahc, SEQADDR0)
1180 | (ahc_inb(ahc, SEQADDR1) << 8));
1181 }
1182 ahc_clear_msg_state(ahc);
1183 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1200 | (ahc_inb(ahc, SEQADDR1) << 8));
1201 }
1202 ahc_clear_msg_state(ahc);
1203 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1184 restart_sequencer(ahc);
1204 ahc_restart(ahc);
1185 } else if ((status & SELTO) != 0) {
1186 u_int scbptr;
1187
1188 /* Stop the selection */
1189 ahc_outb(ahc, SCSISEQ, 0);
1190
1191 /* No more pending messages */
1192 ahc_clear_msg_state(ahc);

--- 20 unchanged lines hidden (view full) ---

1213 printf("%s: ahc_intr - referenced scb not "
1214 "valid during SELTO scb(%d, %d)\n",
1215 ahc_name(ahc), scbptr, scb_index);
1216 } else {
1217 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1218 ahc_freeze_devq(ahc, scb);
1219 }
1220 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1205 } else if ((status & SELTO) != 0) {
1206 u_int scbptr;
1207
1208 /* Stop the selection */
1209 ahc_outb(ahc, SCSISEQ, 0);
1210
1211 /* No more pending messages */
1212 ahc_clear_msg_state(ahc);

--- 20 unchanged lines hidden (view full) ---

1233 printf("%s: ahc_intr - referenced scb not "
1234 "valid during SELTO scb(%d, %d)\n",
1235 ahc_name(ahc), scbptr, scb_index);
1236 } else {
1237 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1238 ahc_freeze_devq(ahc, scb);
1239 }
1240 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1221 restart_sequencer(ahc);
1241 ahc_restart(ahc);
1222 } else {
1223 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1224 ahc_name(ahc), status);
1225 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1226 }
1227}
1228
1229#define AHC_MAX_STEPS 2000

--- 52 unchanged lines hidden (view full) ---

1282 ahc_outb(ahc, SIMODE1, 0);
1283 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1284 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) | STEP);
1285 stepping = TRUE;
1286 }
1287 ahc_outb(ahc, HCNTRL, ahc->unpause);
1288 do {
1289 ahc_delay(200);
1242 } else {
1243 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1244 ahc_name(ahc), status);
1245 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1246 }
1247}
1248
1249#define AHC_MAX_STEPS 2000

--- 52 unchanged lines hidden (view full) ---

1302 ahc_outb(ahc, SIMODE1, 0);
1303 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1304 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) | STEP);
1305 stepping = TRUE;
1306 }
1307 ahc_outb(ahc, HCNTRL, ahc->unpause);
1308 do {
1309 ahc_delay(200);
1290 } while (!sequencer_paused(ahc));
1310 } while (!ahc_is_paused(ahc));
1291 }
1292 if (stepping) {
1293 ahc_outb(ahc, SIMODE0, simode0);
1294 ahc_outb(ahc, SIMODE1, simode1);
1295 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) & ~STEP);
1296 }
1297}
1298

--- 146 unchanged lines hidden (view full) ---

1445 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1446 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1447 maxsync = AHC_SYNCRATE_DT;
1448 } else {
1449 maxsync = AHC_SYNCRATE_ULTRA;
1450 /* Can't do DT on an SE bus */
1451 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1452 }
1311 }
1312 if (stepping) {
1313 ahc_outb(ahc, SIMODE0, simode0);
1314 ahc_outb(ahc, SIMODE1, simode1);
1315 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) & ~STEP);
1316 }
1317}
1318

--- 146 unchanged lines hidden (view full) ---

1465 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1466 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1467 maxsync = AHC_SYNCRATE_DT;
1468 } else {
1469 maxsync = AHC_SYNCRATE_ULTRA;
1470 /* Can't do DT on an SE bus */
1471 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1472 }
1453 } else if ((ahc->features & AHC_ULTRA) != 0) {
1473 } else if ((ahc->features & AHC_ULTRA) != 0
1474 && (ahc->flags & AHC_ULTRA_DISABLED) == 0) {
1454 maxsync = AHC_SYNCRATE_ULTRA;
1455 } else {
1456 maxsync = AHC_SYNCRATE_FAST;
1457 }
1458 /*
1459 * Never allow a value higher than our current goal
1460 * period otherwise we may allow a target initiated
1461 * negotiation to go above the limit as set by the

--- 200 unchanged lines hidden (view full) ---

1662 || tinfo->goal.ppr_options != 0)))
1663 ahc->targ_msg_req |= devinfo->target_mask;
1664 else
1665 ahc->targ_msg_req &= ~devinfo->target_mask;
1666
1667 if (ahc->targ_msg_req != targ_msg_req_orig) {
1668 /* Update the message request bit for this target */
1669 if (!paused)
1475 maxsync = AHC_SYNCRATE_ULTRA;
1476 } else {
1477 maxsync = AHC_SYNCRATE_FAST;
1478 }
1479 /*
1480 * Never allow a value higher than our current goal
1481 * period otherwise we may allow a target initiated
1482 * negotiation to go above the limit as set by the

--- 200 unchanged lines hidden (view full) ---

1683 || tinfo->goal.ppr_options != 0)))
1684 ahc->targ_msg_req |= devinfo->target_mask;
1685 else
1686 ahc->targ_msg_req &= ~devinfo->target_mask;
1687
1688 if (ahc->targ_msg_req != targ_msg_req_orig) {
1689 /* Update the message request bit for this target */
1690 if (!paused)
1670 pause_sequencer(ahc);
1691 ahc_pause(ahc);
1671
1672 ahc_outb(ahc, TARGET_MSG_REQUEST,
1673 ahc->targ_msg_req & 0xFF);
1674 ahc_outb(ahc, TARGET_MSG_REQUEST + 1,
1675 (ahc->targ_msg_req >> 8) & 0xFF);
1676
1677 if (!paused)
1692
1693 ahc_outb(ahc, TARGET_MSG_REQUEST,
1694 ahc->targ_msg_req & 0xFF);
1695 ahc_outb(ahc, TARGET_MSG_REQUEST + 1,
1696 (ahc->targ_msg_req >> 8) & 0xFF);
1697
1698 if (!paused)
1678 unpause_sequencer(ahc);
1699 ahc_unpause(ahc);
1679 }
1680}
1681
1682/*
1683 * Update the user/goal/current tables of synchronous negotiation
1684 * parameters as well as, in the case of a current or active update,
1685 * any data structures on the host controller. In the case of an
1686 * active update, the specified target is currently talking to us on

--- 289 unchanged lines hidden (view full) ---

1976 ahc_compile_devinfo(devinfo,
1977 our_id,
1978 SCSIID_TARGET(ahc, saved_scsiid),
1979 ahc_inb(ahc, SAVED_LUN),
1980 SCSIID_CHANNEL(ahc, saved_scsiid),
1981 role);
1982}
1983
1700 }
1701}
1702
1703/*
1704 * Update the user/goal/current tables of synchronous negotiation
1705 * parameters as well as, in the case of a current or active update,
1706 * any data structures on the host controller. In the case of an
1707 * active update, the specified target is currently talking to us on

--- 289 unchanged lines hidden (view full) ---

1997 ahc_compile_devinfo(devinfo,
1998 our_id,
1999 SCSIID_TARGET(ahc, saved_scsiid),
2000 ahc_inb(ahc, SAVED_LUN),
2001 SCSIID_CHANNEL(ahc, saved_scsiid),
2002 role);
2003}
2004
2005struct ahc_phase_table_entry*
2006ahc_lookup_phase_entry(int phase)
2007{
2008 struct ahc_phase_table_entry *entry;
2009 int i;
2010
2011 /*
2012 * num_phases doesn't include the default entry which
2013 * will be returned if the phase doesn't match.
2014 */
2015 for (i = 0, entry = ahc_phase_table; i < num_phases; i++) {
2016 if (phase == entry->phase)
2017 break;
2018 }
2019 return (entry);
2020}
2021
1984void
1985ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
1986 u_int lun, char channel, role_t role)
1987{
1988 devinfo->our_scsiid = our_id;
1989 devinfo->target = target;
1990 devinfo->lun = lun;
1991 devinfo->target_offset = target;

--- 257 unchanged lines hidden (view full) ---

2249 * Clear any active message state.
2250 */
2251static void
2252ahc_clear_msg_state(struct ahc_softc *ahc)
2253{
2254 ahc->msgout_len = 0;
2255 ahc->msgin_index = 0;
2256 ahc->msg_type = MSG_TYPE_NONE;
2022void
2023ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2024 u_int lun, char channel, role_t role)
2025{
2026 devinfo->our_scsiid = our_id;
2027 devinfo->target = target;
2028 devinfo->lun = lun;
2029 devinfo->target_offset = target;

--- 257 unchanged lines hidden (view full) ---

2287 * Clear any active message state.
2288 */
2289static void
2290ahc_clear_msg_state(struct ahc_softc *ahc)
2291{
2292 ahc->msgout_len = 0;
2293 ahc->msgin_index = 0;
2294 ahc->msg_type = MSG_TYPE_NONE;
2257 if ((ahc_inb(ahc, SCSISIGI) & ATNI) == 0) {
2295 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2258 /*
2259 * The target didn't care to respond to our
2260 * message request, so clear ATN.
2261 */
2262 ahc_outb(ahc, CLRSINT1, CLRATNO);
2263 }
2264 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2265}

--- 604 unchanged lines hidden (view full) ---

2870 }
2871 if (bootverbose) {
2872 printf("(%s:%c:%d:%d): Received PPR width %x, "
2873 "period %x, offset %x,options %x\n"
2874 "\tFiltered to width %x, period %x, "
2875 "offset %x, options %x\n",
2876 ahc_name(ahc), devinfo->channel,
2877 devinfo->target, devinfo->lun,
2296 /*
2297 * The target didn't care to respond to our
2298 * message request, so clear ATN.
2299 */
2300 ahc_outb(ahc, CLRSINT1, CLRATNO);
2301 }
2302 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2303}

--- 604 unchanged lines hidden (view full) ---

2908 }
2909 if (bootverbose) {
2910 printf("(%s:%c:%d:%d): Received PPR width %x, "
2911 "period %x, offset %x,options %x\n"
2912 "\tFiltered to width %x, period %x, "
2913 "offset %x, options %x\n",
2914 ahc_name(ahc), devinfo->channel,
2915 devinfo->target, devinfo->lun,
2878 ahc->msgin_buf[3], saved_width,
2916 saved_width, ahc->msgin_buf[3],
2879 saved_offset, saved_ppr_options,
2880 bus_width, period, offset, ppr_options);
2881 }
2882 ahc_set_width(ahc, devinfo, bus_width,
2883 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
2884 /*paused*/TRUE);
2885 ahc_set_syncrate(ahc, devinfo,
2886 syncrate, period,

--- 10 unchanged lines hidden (view full) ---

2897 }
2898 break;
2899 }
2900 case MSG_BUS_DEV_RESET:
2901 ahc_handle_devreset(ahc, devinfo,
2902 CAM_BDR_SENT,
2903 "Bus Device Reset Received",
2904 /*verbose_level*/0);
2917 saved_offset, saved_ppr_options,
2918 bus_width, period, offset, ppr_options);
2919 }
2920 ahc_set_width(ahc, devinfo, bus_width,
2921 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
2922 /*paused*/TRUE);
2923 ahc_set_syncrate(ahc, devinfo,
2924 syncrate, period,

--- 10 unchanged lines hidden (view full) ---

2935 }
2936 break;
2937 }
2938 case MSG_BUS_DEV_RESET:
2939 ahc_handle_devreset(ahc, devinfo,
2940 CAM_BDR_SENT,
2941 "Bus Device Reset Received",
2942 /*verbose_level*/0);
2905 restart_sequencer(ahc);
2943 ahc_restart(ahc);
2906 done = MSGLOOP_TERMINATED;
2907 break;
2908 case MSG_ABORT_TAG:
2909 case MSG_ABORT:
2910 case MSG_CLEAR_QUEUE:
2911#ifdef AHC_TARGET_MODE
2912 /* Target mode messages */
2913 if (devinfo->role != ROLE_TARGET) {

--- 437 unchanged lines hidden (view full) ---

3351 return (0);
3352}
3353
3354void
3355ahc_softc_insert(struct ahc_softc *ahc)
3356{
3357 struct ahc_softc *list_ahc;
3358
2944 done = MSGLOOP_TERMINATED;
2945 break;
2946 case MSG_ABORT_TAG:
2947 case MSG_ABORT:
2948 case MSG_CLEAR_QUEUE:
2949#ifdef AHC_TARGET_MODE
2950 /* Target mode messages */
2951 if (devinfo->role != ROLE_TARGET) {

--- 437 unchanged lines hidden (view full) ---

3389 return (0);
3390}
3391
3392void
3393ahc_softc_insert(struct ahc_softc *ahc)
3394{
3395 struct ahc_softc *list_ahc;
3396
3359#ifdef AHC_SUPPORT_PCI
3397#if AHC_PCI_CONFIG > 0
3360 /*
3361 * Second Function PCI devices need to inherit some
3398 /*
3399 * Second Function PCI devices need to inherit some
3362 * settings from function 0. We assume that function 0
3363 * will always be found prior to function 1.
3400 * settings from function 0.
3364 */
3365 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
3401 */
3402 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
3366 && ahc_get_pci_function(ahc->dev_softc) == 1) {
3403 && (ahc->features & AHC_MULTI_FUNC) != 0) {
3367 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3368 ahc_dev_softc_t list_pci;
3369 ahc_dev_softc_t pci;
3370
3371 list_pci = list_ahc->dev_softc;
3372 pci = ahc->dev_softc;
3404 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3405 ahc_dev_softc_t list_pci;
3406 ahc_dev_softc_t pci;
3407
3408 list_pci = list_ahc->dev_softc;
3409 pci = ahc->dev_softc;
3373 if (ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)
3374 && ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci)
3375 && ahc_get_pci_function(list_pci) == 0) {
3376 ahc->flags &= ~AHC_BIOS_ENABLED;
3377 ahc->flags |=
3378 list_ahc->flags & AHC_BIOS_ENABLED;
3379 ahc->flags &= ~AHC_CHANNEL_B_PRIMARY;
3380 ahc->flags |=
3381 list_ahc->flags & AHC_CHANNEL_B_PRIMARY;
3410 if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci)
3411 && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) {
3412 struct ahc_softc *master;
3413 struct ahc_softc *slave;
3414
3415 if (ahc_get_pci_function(list_pci) == 0) {
3416 master = list_ahc;
3417 slave = ahc;
3418 } else {
3419 master = ahc;
3420 slave = list_ahc;
3421 }
3422 slave->flags &= ~AHC_BIOS_ENABLED;
3423 slave->flags |=
3424 master->flags & AHC_BIOS_ENABLED;
3425 slave->flags &= ~AHC_PRIMARY_CHANNEL;
3426 slave->flags |=
3427 master->flags & AHC_PRIMARY_CHANNEL;
3382 break;
3383 }
3384 }
3385 }
3386#endif
3387
3388 /*
3389 * Insertion sort into our list of softcs.

--- 124 unchanged lines hidden (view full) ---

3514 u_int sxfrctl1_a, sxfrctl1_b;
3515 int wait;
3516
3517 /*
3518 * Preserve the value of the SXFRCTL1 register for all channels.
3519 * It contains settings that affect termination and we don't want
3520 * to disturb the integrity of the bus.
3521 */
3428 break;
3429 }
3430 }
3431 }
3432#endif
3433
3434 /*
3435 * Insertion sort into our list of softcs.

--- 124 unchanged lines hidden (view full) ---

3560 u_int sxfrctl1_a, sxfrctl1_b;
3561 int wait;
3562
3563 /*
3564 * Preserve the value of the SXFRCTL1 register for all channels.
3565 * It contains settings that affect termination and we don't want
3566 * to disturb the integrity of the bus.
3567 */
3522 pause_sequencer(ahc);
3568 ahc_pause(ahc);
3523 sxfrctl1_b = 0;
3524 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
3525 u_int sblkctl;
3526
3527 /*
3528 * Save channel B's settings in case this chip
3529 * is setup for TWIN channel operation.
3530 */

--- 421 unchanged lines hidden (view full) ---

3952 int len;
3953
3954 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
3955 buf += len;
3956 if ((ahc->features & AHC_TWIN) != 0)
3957 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
3958 "B SCSI Id=%d, primary %c, ",
3959 ahc->our_id, ahc->our_id_b,
3569 sxfrctl1_b = 0;
3570 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
3571 u_int sblkctl;
3572
3573 /*
3574 * Save channel B's settings in case this chip
3575 * is setup for TWIN channel operation.
3576 */

--- 421 unchanged lines hidden (view full) ---

3998 int len;
3999
4000 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4001 buf += len;
4002 if ((ahc->features & AHC_TWIN) != 0)
4003 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
4004 "B SCSI Id=%d, primary %c, ",
4005 ahc->our_id, ahc->our_id_b,
3960 ahc->flags & AHC_CHANNEL_B_PRIMARY ? 'B': 'A');
4006 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
3961 else {
3962 const char *type;
3963
3964 if ((ahc->features & AHC_WIDE) != 0) {
3965 type = "Wide";
3966 } else {
3967 type = "Single";
3968 }

--- 160 unchanged lines hidden (view full) ---

4129 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4130 printf("%s: unable to allocate tmode_tstate. "
4131 "Failing attach\n", ahc_name(ahc));
4132 return (-1);
4133 }
4134 }
4135
4136 ahc_outb(ahc, SEQ_FLAGS, 0);
4007 else {
4008 const char *type;
4009
4010 if ((ahc->features & AHC_WIDE) != 0) {
4011 type = "Wide";
4012 } else {
4013 type = "Single";
4014 }

--- 160 unchanged lines hidden (view full) ---

4175 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4176 printf("%s: unable to allocate tmode_tstate. "
4177 "Failing attach\n", ahc_name(ahc));
4178 return (-1);
4179 }
4180 }
4181
4182 ahc_outb(ahc, SEQ_FLAGS, 0);
4183 ahc_outb(ahc, SEQ_FLAGS2, 0);
4137
4138 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) {
4139 ahc->flags |= AHC_PAGESCBS;
4140 } else {
4141 ahc->flags &= ~AHC_PAGESCBS;
4142 }
4143
4144#ifdef AHC_DEBUG

--- 68 unchanged lines hidden (view full) ---

4213 ultraenb = ALL_TARGETS_MASK;
4214 } else {
4215 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
4216 | ahc_inb(ahc, DISC_DSB));
4217 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
4218 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
4219 | ahc_inb(ahc, ULTRA_ENB);
4220 }
4184
4185 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) {
4186 ahc->flags |= AHC_PAGESCBS;
4187 } else {
4188 ahc->flags &= ~AHC_PAGESCBS;
4189 }
4190
4191#ifdef AHC_DEBUG

--- 68 unchanged lines hidden (view full) ---

4260 ultraenb = ALL_TARGETS_MASK;
4261 } else {
4262 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
4263 | ahc_inb(ahc, DISC_DSB));
4264 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
4265 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
4266 | ahc_inb(ahc, ULTRA_ENB);
4267 }
4268 if ((ahc->flags & AHC_ULTRA_DISABLED) != 0)
4269 ultraenb = 0;
4221
4222 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
4223 max_targ = 7;
4224
4225 for (i = 0; i <= max_targ; i++) {
4226 struct ahc_initiator_tinfo *tinfo;
4227 struct tmode_tstate *tstate;
4228 u_int our_id;

--- 40 unchanged lines hidden (view full) ---

4269 */
4270 scsirate = (scsirate & SXFR) >> 4
4271 | (ultraenb & mask)
4272 ? 0x08 : 0x0
4273 | (scsirate & WIDEXFER);
4274 offset = MAX_OFFSET_ULTRA2;
4275 } else
4276 offset = ahc_inb(ahc, TARG_OFFSET + i);
4270
4271 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
4272 max_targ = 7;
4273
4274 for (i = 0; i <= max_targ; i++) {
4275 struct ahc_initiator_tinfo *tinfo;
4276 struct tmode_tstate *tstate;
4277 u_int our_id;

--- 40 unchanged lines hidden (view full) ---

4318 */
4319 scsirate = (scsirate & SXFR) >> 4
4320 | (ultraenb & mask)
4321 ? 0x08 : 0x0
4322 | (scsirate & WIDEXFER);
4323 offset = MAX_OFFSET_ULTRA2;
4324 } else
4325 offset = ahc_inb(ahc, TARG_OFFSET + i);
4326 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
4327 /* Set to the lowest sync rate, 5MHz */
4328 scsirate |= 0x1c;
4277 maxsync = AHC_SYNCRATE_ULTRA2;
4278 if ((ahc->features & AHC_DT) != 0)
4279 maxsync = AHC_SYNCRATE_DT;
4280 tinfo->user.period =
4281 ahc_find_period(ahc, scsirate, maxsync);
4282 if (offset == 0)
4283 tinfo->user.period = 0;
4284 else

--- 12 unchanged lines hidden (view full) ---

4297 tinfo->user.period =
4298 ahc_find_period(ahc, scsirate,
4299 (ultraenb & mask)
4300 ? AHC_SYNCRATE_ULTRA
4301 : AHC_SYNCRATE_FAST);
4302 if (tinfo->user.period != 0)
4303 tinfo->user.offset = ~0;
4304 }
4329 maxsync = AHC_SYNCRATE_ULTRA2;
4330 if ((ahc->features & AHC_DT) != 0)
4331 maxsync = AHC_SYNCRATE_DT;
4332 tinfo->user.period =
4333 ahc_find_period(ahc, scsirate, maxsync);
4334 if (offset == 0)
4335 tinfo->user.period = 0;
4336 else

--- 12 unchanged lines hidden (view full) ---

4349 tinfo->user.period =
4350 ahc_find_period(ahc, scsirate,
4351 (ultraenb & mask)
4352 ? AHC_SYNCRATE_ULTRA
4353 : AHC_SYNCRATE_FAST);
4354 if (tinfo->user.period != 0)
4355 tinfo->user.offset = ~0;
4356 }
4357 if (tinfo->user.period == 0)
4358 tinfo->user.offset = 0;
4305 if ((scsirate & WIDEXFER) != 0
4306 && (ahc->features & AHC_WIDE) != 0)
4307 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4308 tinfo->user.protocol_version = 4;
4309 if ((ahc->features & AHC_DT) != 0)
4310 tinfo->user.transport_version = 3;
4311 else
4312 tinfo->user.transport_version = 2;

--- 120 unchanged lines hidden (view full) ---

4433
4434 /*
4435 * Wait for up to 500ms for our transceivers
4436 * to settle. If the adapter does not have
4437 * a cable attached, the tranceivers may
4438 * never settle, so don't complain if we
4439 * fail here.
4440 */
4359 if ((scsirate & WIDEXFER) != 0
4360 && (ahc->features & AHC_WIDE) != 0)
4361 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4362 tinfo->user.protocol_version = 4;
4363 if ((ahc->features & AHC_DT) != 0)
4364 tinfo->user.transport_version = 3;
4365 else
4366 tinfo->user.transport_version = 2;

--- 120 unchanged lines hidden (view full) ---

4487
4488 /*
4489 * Wait for up to 500ms for our transceivers
4490 * to settle. If the adapter does not have
4491 * a cable attached, the tranceivers may
4492 * never settle, so don't complain if we
4493 * fail here.
4494 */
4441 pause_sequencer(ahc);
4495 ahc_pause(ahc);
4442 for (wait = 5000;
4443 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4444 wait--)
4445 ahc_delay(100);
4496 for (wait = 5000;
4497 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4498 wait--)
4499 ahc_delay(100);
4446 unpause_sequencer(ahc);
4500 ahc_unpause(ahc);
4447 }
4448 return (0);
4449}
4450
4451/*
4452 * Ensure that the card is paused in a location
4453 * outside of all critical sections and that all
4454 * pending work is completed prior to returning.

--- 6 unchanged lines hidden (view full) ---

4461 int intstat;
4462 int maxloops;
4463
4464 maxloops = 1000;
4465 ahc->flags |= AHC_ALL_INTERRUPTS;
4466 intstat = 0;
4467 do {
4468 ahc_intr(ahc);
4501 }
4502 return (0);
4503}
4504
4505/*
4506 * Ensure that the card is paused in a location
4507 * outside of all critical sections and that all
4508 * pending work is completed prior to returning.

--- 6 unchanged lines hidden (view full) ---

4515 int intstat;
4516 int maxloops;
4517
4518 maxloops = 1000;
4519 ahc->flags |= AHC_ALL_INTERRUPTS;
4520 intstat = 0;
4521 do {
4522 ahc_intr(ahc);
4469 pause_sequencer(ahc);
4523 ahc_pause(ahc);
4470 ahc_clear_critical_section(ahc);
4471 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0)
4472 break;
4473 maxloops--;
4474 } while (((intstat = ahc_inb(ahc, INTSTAT)) & INT_PEND) && --maxloops);
4475 if (maxloops == 0) {
4476 printf("Infinite interrupt loop, INTSTAT = %x",
4477 ahc_inb(ahc, INTSTAT));

--- 914 unchanged lines hidden (view full) ---

5392
5393 ahc->pending_device = NULL;
5394
5395 ahc_compile_devinfo(&devinfo,
5396 CAM_TARGET_WILDCARD,
5397 CAM_TARGET_WILDCARD,
5398 CAM_LUN_WILDCARD,
5399 channel, ROLE_UNKNOWN);
4524 ahc_clear_critical_section(ahc);
4525 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0)
4526 break;
4527 maxloops--;
4528 } while (((intstat = ahc_inb(ahc, INTSTAT)) & INT_PEND) && --maxloops);
4529 if (maxloops == 0) {
4530 printf("Infinite interrupt loop, INTSTAT = %x",
4531 ahc_inb(ahc, INTSTAT));

--- 914 unchanged lines hidden (view full) ---

5446
5447 ahc->pending_device = NULL;
5448
5449 ahc_compile_devinfo(&devinfo,
5450 CAM_TARGET_WILDCARD,
5451 CAM_TARGET_WILDCARD,
5452 CAM_LUN_WILDCARD,
5453 channel, ROLE_UNKNOWN);
5400 pause_sequencer(ahc);
5454 ahc_pause(ahc);
5401
5402 /* Make sure the sequencer is in a safe location. */
5403 ahc_clear_critical_section(ahc);
5404
5405 /*
5406 * Run our command complete fifos to ensure that we perform
5407 * completion processing on any commands that 'completed'
5408 * before the reset occurred.

--- 98 unchanged lines hidden (view full) ---

5507 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
5508 /*period*/0, /*offset*/0,
5509 /*ppr_options*/0, AHC_TRANS_CUR,
5510 /*paused*/TRUE);
5511 }
5512 }
5513
5514 if (restart_needed)
5455
5456 /* Make sure the sequencer is in a safe location. */
5457 ahc_clear_critical_section(ahc);
5458
5459 /*
5460 * Run our command complete fifos to ensure that we perform
5461 * completion processing on any commands that 'completed'
5462 * before the reset occurred.

--- 98 unchanged lines hidden (view full) ---

5561 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
5562 /*period*/0, /*offset*/0,
5563 /*ppr_options*/0, AHC_TRANS_CUR,
5564 /*paused*/TRUE);
5565 }
5566 }
5567
5568 if (restart_needed)
5515 restart_sequencer(ahc);
5569 ahc_restart(ahc);
5516 else
5570 else
5517 unpause_sequencer(ahc);
5571 ahc_unpause(ahc);
5518 return found;
5519}
5520
5521
5522/***************************** Residual Processing ****************************/
5523/*
5524 * Calculate the residual for a just completed SCB.
5525 */

--- 282 unchanged lines hidden (view full) ---

5808
5809 cs_count *= sizeof(struct cs);
5810 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
5811 if (ahc->critical_sections == NULL)
5812 panic("ahc_loadseq: Could not malloc");
5813 memcpy(ahc->critical_sections, cs_table, cs_count);
5814 }
5815 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
5572 return found;
5573}
5574
5575
5576/***************************** Residual Processing ****************************/
5577/*
5578 * Calculate the residual for a just completed SCB.
5579 */

--- 282 unchanged lines hidden (view full) ---

5862
5863 cs_count *= sizeof(struct cs);
5864 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
5865 if (ahc->critical_sections == NULL)
5866 panic("ahc_loadseq: Could not malloc");
5867 memcpy(ahc->critical_sections, cs_table, cs_count);
5868 }
5869 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
5816 restart_sequencer(ahc);
5870 ahc_restart(ahc);
5817
5818 if (bootverbose)
5819 printf(" %d instructions downloaded\n", downloaded);
5820}
5821
5822static int
5823ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
5824 u_int start_instr, u_int *skip_addr)

--- 385 unchanged lines hidden (view full) ---

6210 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
6211 ccb->ccb_h.status = CAM_BUSY;
6212 ahc_unlock(ahc, &s);
6213 return;
6214 }
6215 ahc->flags |= AHC_TARGETROLE;
6216 if ((ahc->features & AHC_MULTIROLE) == 0)
6217 ahc->flags &= ~AHC_INITIATORROLE;
5871
5872 if (bootverbose)
5873 printf(" %d instructions downloaded\n", downloaded);
5874}
5875
5876static int
5877ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
5878 u_int start_instr, u_int *skip_addr)

--- 385 unchanged lines hidden (view full) ---

6264 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
6265 ccb->ccb_h.status = CAM_BUSY;
6266 ahc_unlock(ahc, &s);
6267 return;
6268 }
6269 ahc->flags |= AHC_TARGETROLE;
6270 if ((ahc->features & AHC_MULTIROLE) == 0)
6271 ahc->flags &= ~AHC_INITIATORROLE;
6218 pause_sequencer(ahc);
6272 ahc_pause(ahc);
6219 ahc_loadseq(ahc);
6220 ahc_unlock(ahc, &s);
6221 }
6222 cel = &ccb->cel;
6223 target = ccb->ccb_h.target_id;
6224 lun = ccb->ccb_h.target_lun;
6225 channel = SIM_CHANNEL(ahc, sim);
6226 target_mask = 0x01 << target;

--- 52 unchanged lines hidden (view full) ---

6279 xpt_print_path(ccb->ccb_h.path);
6280 printf("Couldn't allocate path\n");
6281 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6282 return;
6283 }
6284 SLIST_INIT(&lstate->accept_tios);
6285 SLIST_INIT(&lstate->immed_notifies);
6286 ahc_lock(ahc, &s);
6273 ahc_loadseq(ahc);
6274 ahc_unlock(ahc, &s);
6275 }
6276 cel = &ccb->cel;
6277 target = ccb->ccb_h.target_id;
6278 lun = ccb->ccb_h.target_lun;
6279 channel = SIM_CHANNEL(ahc, sim);
6280 target_mask = 0x01 << target;

--- 52 unchanged lines hidden (view full) ---

6333 xpt_print_path(ccb->ccb_h.path);
6334 printf("Couldn't allocate path\n");
6335 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6336 return;
6337 }
6338 SLIST_INIT(&lstate->accept_tios);
6339 SLIST_INIT(&lstate->immed_notifies);
6340 ahc_lock(ahc, &s);
6287 pause_sequencer(ahc);
6341 ahc_pause(ahc);
6288 if (target != CAM_TARGET_WILDCARD) {
6289 tstate->enabled_luns[lun] = lstate;
6290 ahc->enabled_luns++;
6291
6292 if ((ahc->features & AHC_MULTI_TID) != 0) {
6293 u_int targid_mask;
6294
6295 targid_mask = ahc_inb(ahc, TARGID)

--- 47 unchanged lines hidden (view full) ---

6343 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
6344 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6345 scsiseq |= ENSELI;
6346 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
6347 scsiseq = ahc_inb(ahc, SCSISEQ);
6348 scsiseq |= ENSELI;
6349 ahc_outb(ahc, SCSISEQ, scsiseq);
6350 }
6342 if (target != CAM_TARGET_WILDCARD) {
6343 tstate->enabled_luns[lun] = lstate;
6344 ahc->enabled_luns++;
6345
6346 if ((ahc->features & AHC_MULTI_TID) != 0) {
6347 u_int targid_mask;
6348
6349 targid_mask = ahc_inb(ahc, TARGID)

--- 47 unchanged lines hidden (view full) ---

6397 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
6398 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6399 scsiseq |= ENSELI;
6400 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
6401 scsiseq = ahc_inb(ahc, SCSISEQ);
6402 scsiseq |= ENSELI;
6403 ahc_outb(ahc, SCSISEQ, scsiseq);
6404 }
6351 unpause_sequencer(ahc);
6405 ahc_unpause(ahc);
6352 ahc_unlock(ahc, &s);
6353 ccb->ccb_h.status = CAM_REQ_CMP;
6354 xpt_print_path(ccb->ccb_h.path);
6355 printf("Lun now enabled for target mode\n");
6356 } else {
6357 struct scb *scb;
6358 int i, empty;
6359

--- 33 unchanged lines hidden (view full) ---

6393 return;
6394 }
6395
6396 xpt_print_path(ccb->ccb_h.path);
6397 printf("Target mode disabled\n");
6398 xpt_free_path(lstate->path);
6399 free(lstate, M_DEVBUF);
6400
6406 ahc_unlock(ahc, &s);
6407 ccb->ccb_h.status = CAM_REQ_CMP;
6408 xpt_print_path(ccb->ccb_h.path);
6409 printf("Lun now enabled for target mode\n");
6410 } else {
6411 struct scb *scb;
6412 int i, empty;
6413

--- 33 unchanged lines hidden (view full) ---

6447 return;
6448 }
6449
6450 xpt_print_path(ccb->ccb_h.path);
6451 printf("Target mode disabled\n");
6452 xpt_free_path(lstate->path);
6453 free(lstate, M_DEVBUF);
6454
6401 pause_sequencer(ahc);
6455 ahc_pause(ahc);
6402 /* Can we clean up the target too? */
6403 if (target != CAM_TARGET_WILDCARD) {
6404 tstate->enabled_luns[lun] = NULL;
6405 ahc->enabled_luns--;
6406 for (empty = 1, i = 0; i < 8; i++)
6407 if (tstate->enabled_luns[i] != NULL) {
6408 empty = 0;
6409 break;

--- 36 unchanged lines hidden (view full) ---

6446 scsiseq = ahc_inb(ahc, SCSISEQ);
6447 scsiseq &= ~ENSELI;
6448 ahc_outb(ahc, SCSISEQ, scsiseq);
6449
6450 if ((ahc->features & AHC_MULTIROLE) == 0) {
6451 printf("Configuring Initiator Mode\n");
6452 ahc->flags &= ~AHC_TARGETROLE;
6453 ahc->flags |= AHC_INITIATORROLE;
6456 /* Can we clean up the target too? */
6457 if (target != CAM_TARGET_WILDCARD) {
6458 tstate->enabled_luns[lun] = NULL;
6459 ahc->enabled_luns--;
6460 for (empty = 1, i = 0; i < 8; i++)
6461 if (tstate->enabled_luns[i] != NULL) {
6462 empty = 0;
6463 break;

--- 36 unchanged lines hidden (view full) ---

6500 scsiseq = ahc_inb(ahc, SCSISEQ);
6501 scsiseq &= ~ENSELI;
6502 ahc_outb(ahc, SCSISEQ, scsiseq);
6503
6504 if ((ahc->features & AHC_MULTIROLE) == 0) {
6505 printf("Configuring Initiator Mode\n");
6506 ahc->flags &= ~AHC_TARGETROLE;
6507 ahc->flags |= AHC_INITIATORROLE;
6454 pause_sequencer(ahc);
6508 ahc_pause(ahc);
6455 ahc_loadseq(ahc);
6456 }
6457 }
6509 ahc_loadseq(ahc);
6510 }
6511 }
6458 unpause_sequencer(ahc);
6512 ahc_unpause(ahc);
6459 ahc_unlock(ahc, &s);
6460 }
6461}
6462
6463static void
6464ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
6465{
6466 u_int scsiid_mask;

--- 65 unchanged lines hidden (view full) ---

6532 u_int hs_mailbox;
6533
6534 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
6535 hs_mailbox &= ~HOST_TQINPOS;
6536 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
6537 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
6538 } else {
6539 if (!paused)
6513 ahc_unlock(ahc, &s);
6514 }
6515}
6516
6517static void
6518ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
6519{
6520 u_int scsiid_mask;

--- 65 unchanged lines hidden (view full) ---

6586 u_int hs_mailbox;
6587
6588 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
6589 hs_mailbox &= ~HOST_TQINPOS;
6590 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
6591 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
6592 } else {
6593 if (!paused)
6540 pause_sequencer(ahc);
6594 ahc_pause(ahc);
6541 ahc_outb(ahc, KERNEL_TQINPOS,
6542 ahc->tqinfifonext & HOST_TQINPOS);
6543 if (!paused)
6595 ahc_outb(ahc, KERNEL_TQINPOS,
6596 ahc->tqinfifonext & HOST_TQINPOS);
6597 if (!paused)
6544 unpause_sequencer(ahc);
6598 ahc_unpause(ahc);
6545 }
6546 }
6547 }
6548}
6549
6550static int
6551ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
6552{

--- 109 unchanged lines hidden --- 		6599 }
6600 }
6601 }
6602}
6603
6604static int
6605ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
6606{

--- 109 unchanged lines hidden ---