| aic79xx_pci.c (107440) | aic79xx_pci.c (107623) |
|---|---|
| 1/* 2 * Product specific probe and attach routines for: 3 * aic7901 and aic7902 SCSI controllers 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * Copyright (c) 2000-2002 Adaptec Inc. 7 * All rights reserved. 8 * --- 24 unchanged lines hidden (view full) --- 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * | 1/* 2 * Product specific probe and attach routines for: 3 * aic7901 and aic7902 SCSI controllers 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * Copyright (c) 2000-2002 Adaptec Inc. 7 * All rights reserved. 8 * --- 24 unchanged lines hidden (view full) --- 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * |
| 41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#54 $ | 41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#60 $ |
| 42 * | 42 * |
| 43 * $FreeBSD: head/sys/dev/aic7xxx/aic79xx_pci.c 107440 2002-12-01 07:59:01Z scottl $ | 43 * $FreeBSD: head/sys/dev/aic7xxx/aic79xx_pci.c 107623 2002-12-04 22:51:29Z scottl $ |
| 44 */ 45 46#ifdef __linux__ 47#include "aic79xx_osm.h" 48#include "aic79xx_inline.h" 49#else 50#include <dev/aic7xxx/aic79xx_osm.h> 51#include <dev/aic7xxx/aic79xx_inline.h> --- 118 unchanged lines hidden (view full) --- 170 { 171 ID_AHA_29320B, 172 ID_ALL_MASK, 173 "Adaptec 29320B Ultra320 SCSI adapter", 174 ahd_aic7902_setup 175 }, 176 /* Generic chip probes for devices we don't know 'exactly' */ 177 { | 44 */ 45 46#ifdef __linux__ 47#include "aic79xx_osm.h" 48#include "aic79xx_inline.h" 49#else 50#include <dev/aic7xxx/aic79xx_osm.h> 51#include <dev/aic7xxx/aic79xx_inline.h> --- 118 unchanged lines hidden (view full) --- 170 { 171 ID_AHA_29320B, 172 ID_ALL_MASK, 173 "Adaptec 29320B Ultra320 SCSI adapter", 174 ahd_aic7902_setup 175 }, 176 /* Generic chip probes for devices we don't know 'exactly' */ 177 { |
| 178 ID_AIC7901A & ID_ALL_MASK, 179 ID_ALL_MASK, | 178 ID_AIC7901A & ID_DEV_VENDOR_MASK, 179 ID_DEV_VENDOR_MASK, |
| 180 "Adaptec AIC7901A Ultra320 SCSI adapter", 181 ahd_aic7901A_setup 182 }, 183 { 184 ID_AIC7902 & ID_9005_GENERIC_MASK, 185 ID_9005_GENERIC_MASK, 186 "Adaptec AIC7902 Ultra320 SCSI adapter", 187 ahd_aic7902_setup --- 185 unchanged lines hidden (view full) --- 373 374/* 375 * Perform some simple tests that should catch situations where 376 * our registers are invalidly mapped. 377 */ 378int 379ahd_pci_test_register_access(struct ahd_softc *ahd) 380{ | 180 "Adaptec AIC7901A Ultra320 SCSI adapter", 181 ahd_aic7901A_setup 182 }, 183 { 184 ID_AIC7902 & ID_9005_GENERIC_MASK, 185 ID_9005_GENERIC_MASK, 186 "Adaptec AIC7902 Ultra320 SCSI adapter", 187 ahd_aic7902_setup --- 185 unchanged lines hidden (view full) --- 373 374/* 375 * Perform some simple tests that should catch situations where 376 * our registers are invalidly mapped. 377 */ 378int 379ahd_pci_test_register_access(struct ahd_softc *ahd) 380{ |
| 381 int i; | 381 ahd_mode_state saved_modes; 382 int error; 383 uint8_t seqctl; |
| 382 | 384 |
| 385 saved_modes = ahd_save_modes(ahd); 386 error = EIO; 387 388 /* Enable PCI error interrupt status */ 389 seqctl = ahd_inb(ahd, SEQCTL0); 390 ahd_outb(ahd, SEQCTL0, seqctl & ~FAILDIS); 391 |
|
| 383 /* 384 * First a simple test to see if any 385 * registers can be read. Reading 386 * HCNTRL has no side effects and has 387 * at least one bit that is guaranteed to 388 * be zero so it is a good register to 389 * use for this test. 390 */ 391 if (ahd_inb(ahd, HCNTRL) == 0xFF) | 392 /* 393 * First a simple test to see if any 394 * registers can be read. Reading 395 * HCNTRL has no side effects and has 396 * at least one bit that is guaranteed to 397 * be zero so it is a good register to 398 * use for this test. 399 */ 400 if (ahd_inb(ahd, HCNTRL) == 0xFF) |
| 392 return (EIO); | 401 goto fail; |
| 393 394 /* 395 * Next create a situation where write combining 396 * or read prefetching could be initiated by the 397 * CPU or host bridge. Our device does not support 398 * either, so look for data corruption and/or flaged 399 * PCI errors. 400 */ | 402 403 /* 404 * Next create a situation where write combining 405 * or read prefetching could be initiated by the 406 * CPU or host bridge. Our device does not support 407 * either, so look for data corruption and/or flaged 408 * PCI errors. 409 */ |
| 401 for (i = 0; i < 16; i++) 402 ahd_outb(ahd, SRAM_BASE + i, i); | 410 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 411 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 412 goto fail; |
| 403 | 413 |
| 404 for (i = 0; i < 16; i++) 405 if (ahd_inb(ahd, SRAM_BASE + i) != i) 406 return (EIO); | 414 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 415 u_int targpcistat; |
| 407 | 416 |
| 417 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 418 targpcistat = ahd_inb(ahd, TARGPCISTAT); 419 if ((targpcistat & STA) != 0) 420 goto fail; 421 } 422 423 error = 0; 424 425fail: |
|
| 408 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { | 426 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { |
| 409 ahd_mode_state saved_modes; 410 u_int targpcistat; 411 u_int pci_status1; | 427 u_int targpcistat; 428 u_int pci_status1; |
| 412 | 429 |
| 413 saved_modes = ahd_save_modes(ahd); | |
| 414 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 415 targpcistat = ahd_inb(ahd, TARGPCISTAT); 416 417 /* Silently clear any latched errors. */ 418 ahd_outb(ahd, TARGPCISTAT, targpcistat); 419 pci_status1 = ahd_pci_read_config(ahd->dev_softc, 420 PCIR_STATUS + 1, /*bytes*/1); 421 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 422 pci_status1, /*bytes*/1); | 430 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 431 targpcistat = ahd_inb(ahd, TARGPCISTAT); 432 433 /* Silently clear any latched errors. */ 434 ahd_outb(ahd, TARGPCISTAT, targpcistat); 435 pci_status1 = ahd_pci_read_config(ahd->dev_softc, 436 PCIR_STATUS + 1, /*bytes*/1); 437 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 438 pci_status1, /*bytes*/1); |
| 423 ahd_restore_modes(ahd, saved_modes); 424 425 if ((targpcistat & STA) != 0) 426 return (EIO); | 439 ahd_outb(ahd, CLRINT, CLRPCIINT); |
| 427 } 428 | 440 } 441 |
| 429 return (0); | 442 ahd_restore_modes(ahd, saved_modes); 443 ahd_outb(ahd, SEQCTL0, seqctl); 444 return (error); |
| 430} 431 432/* 433 * Check the external port logic for a serial eeprom 434 * and termination/cable detection contrls. 435 */ 436static int 437ahd_check_extport(struct ahd_softc *ahd) --- 288 unchanged lines hidden (view full) --- 726 727 for (bit = 0; bit < 8; bit++) { 728 729 if ((pci_status[i] & (0x1 << bit)) != 0) { 730 static const char *s; 731 732 s = pci_status_strings[bit]; 733 if (i == 7/*TARG*/ && bit == 3) | 445} 446 447/* 448 * Check the external port logic for a serial eeprom 449 * and termination/cable detection contrls. 450 */ 451static int 452ahd_check_extport(struct ahd_softc *ahd) --- 288 unchanged lines hidden (view full) --- 741 742 for (bit = 0; bit < 8; bit++) { 743 744 if ((pci_status[i] & (0x1 << bit)) != 0) { 745 static const char *s; 746 747 s = pci_status_strings[bit]; 748 if (i == 7/*TARG*/ && bit == 3) |
| 734 s = "%s: Signal Target Abort\n"; | 749 s = "%s: Signaled Target Abort\n"; |
| 735 printf(s, ahd_name(ahd), pci_status_source[i]); 736 } 737 } 738 } 739 pci_status1 = ahd_pci_read_config(ahd->dev_softc, 740 PCIR_STATUS + 1, /*bytes*/1); 741 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 742 pci_status1, /*bytes*/1); 743 ahd_restore_modes(ahd, saved_modes); | 750 printf(s, ahd_name(ahd), pci_status_source[i]); 751 } 752 } 753 } 754 pci_status1 = ahd_pci_read_config(ahd->dev_softc, 755 PCIR_STATUS + 1, /*bytes*/1); 756 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 757 pci_status1, /*bytes*/1); 758 ahd_restore_modes(ahd, saved_modes); |
| 759 ahd_outb(ahd, CLRINT, CLRPCIINT); |
|
| 744 ahd_unpause(ahd); 745} 746 747static void 748ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 749{ 750 uint8_t split_status[4]; 751 uint8_t split_status1[4]; --- 53 unchanged lines hidden (view full) --- 805 } 806 } 807 } 808 /* 809 * Clear PCI-X status bits. 810 */ 811 ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS, 812 pcix_status, /*bytes*/2); | 760 ahd_unpause(ahd); 761} 762 763static void 764ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 765{ 766 uint8_t split_status[4]; 767 uint8_t split_status1[4]; --- 53 unchanged lines hidden (view full) --- 821 } 822 } 823 } 824 /* 825 * Clear PCI-X status bits. 826 */ 827 ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS, 828 pcix_status, /*bytes*/2); |
| 829 ahd_outb(ahd, CLRINT, CLRSPLTINT); |
|
| 813 ahd_restore_modes(ahd, saved_modes); 814} 815 816static int 817ahd_aic7901A_setup(struct ahd_softc *ahd) 818{ 819 int error; 820 --- 75 unchanged lines hidden --- | 830 ahd_restore_modes(ahd, saved_modes); 831} 832 833static int 834ahd_aic7901A_setup(struct ahd_softc *ahd) 835{ 836 int error; 837 --- 75 unchanged lines hidden --- |