1/*-
2 * Copyright (c) 2000 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
| 1/*-
2 * Copyright (c) 2000 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
|
27 */
28
29#ifndef _PCI_AGPREG_H_
30#define _PCI_AGPREG_H_
31
32/*
33 * Offsets for various AGP configuration registers.
34 */
35#define AGP_APBASE 0x10
36#define AGP_CAPPTR 0x34
37
38/*
39 * Offsets from the AGP Capability pointer.
40 */
41#define AGP_CAPID 0x0
42#define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20)
43#define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16)
44#define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8)
45#define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0)
46
47#define AGP_STATUS 0x4
48#define AGP_COMMAND 0x8
49
50/*
51 * Config offsets for Intel AGP chipsets.
52 */
53#define AGP_INTEL_NBXCFG 0x50
54#define AGP_INTEL_ERRSTS 0x91
55#define AGP_INTEL_AGPCTRL 0xb0
56#define AGP_INTEL_APSIZE 0xb4
57#define AGP_INTEL_ATTBASE 0xb8
58
59/*
60 * Config offsets for VIA AGP chipsets.
61 */
62#define AGP_VIA_GARTCTRL 0x80
63#define AGP_VIA_APSIZE 0x84
64#define AGP_VIA_ATTBASE 0x88
65
66/*
67 * Config offsets for SiS AGP chipsets.
68 */
69#define AGP_SIS_ATTBASE 0x90
70#define AGP_SIS_WINCTRL 0x94
71#define AGP_SIS_TLBCTRL 0x97
72#define AGP_SIS_TLBFLUSH 0x98
73
74/*
75 * Config offsets for Ali AGP chipsets.
76 */
77#define AGP_ALI_AGPCTRL 0xb8
78#define AGP_ALI_ATTBASE 0xbc
79#define AGP_ALI_TLBCTRL 0xc0
80
81/*
82 * Config offsets for the AMD 751 chipset.
83 */
84#define AGP_AMD751_REGISTERS 0x14
85#define AGP_AMD751_APCTRL 0xac
86#define AGP_AMD751_MODECTRL 0xb0
| 27 */
28
29#ifndef _PCI_AGPREG_H_
30#define _PCI_AGPREG_H_
31
32/*
33 * Offsets for various AGP configuration registers.
34 */
35#define AGP_APBASE 0x10
36#define AGP_CAPPTR 0x34
37
38/*
39 * Offsets from the AGP Capability pointer.
40 */
41#define AGP_CAPID 0x0
42#define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20)
43#define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16)
44#define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8)
45#define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0)
46
47#define AGP_STATUS 0x4
48#define AGP_COMMAND 0x8
49
50/*
51 * Config offsets for Intel AGP chipsets.
52 */
53#define AGP_INTEL_NBXCFG 0x50
54#define AGP_INTEL_ERRSTS 0x91
55#define AGP_INTEL_AGPCTRL 0xb0
56#define AGP_INTEL_APSIZE 0xb4
57#define AGP_INTEL_ATTBASE 0xb8
58
59/*
60 * Config offsets for VIA AGP chipsets.
61 */
62#define AGP_VIA_GARTCTRL 0x80
63#define AGP_VIA_APSIZE 0x84
64#define AGP_VIA_ATTBASE 0x88
65
66/*
67 * Config offsets for SiS AGP chipsets.
68 */
69#define AGP_SIS_ATTBASE 0x90
70#define AGP_SIS_WINCTRL 0x94
71#define AGP_SIS_TLBCTRL 0x97
72#define AGP_SIS_TLBFLUSH 0x98
73
74/*
75 * Config offsets for Ali AGP chipsets.
76 */
77#define AGP_ALI_AGPCTRL 0xb8
78#define AGP_ALI_ATTBASE 0xbc
79#define AGP_ALI_TLBCTRL 0xc0
80
81/*
82 * Config offsets for the AMD 751 chipset.
83 */
84#define AGP_AMD751_REGISTERS 0x14
85#define AGP_AMD751_APCTRL 0xac
86#define AGP_AMD751_MODECTRL 0xb0
|
87
88/*
89 * Memory mapped register offsets for AMD 751 chipset.
90 */
91#define AGP_AMD751_CAPS 0x00
92#define AGP_AMD751_CAPS_EHI 0x0800
93#define AGP_AMD751_CAPS_P2P 0x0400
94#define AGP_AMD751_CAPS_MPC 0x0200
95#define AGP_AMD751_CAPS_VBE 0x0100
96#define AGP_AMD751_CAPS_REV 0x00ff
97#define AGP_AMD751_STATUS 0x02
98#define AGP_AMD751_STATUS_P2PS 0x0800
99#define AGP_AMD751_STATUS_GCS 0x0400
100#define AGP_AMD751_STATUS_MPS 0x0200
101#define AGP_AMD751_STATUS_VBES 0x0100
102#define AGP_AMD751_STATUS_P2PE 0x0008
103#define AGP_AMD751_STATUS_GCE 0x0004
104#define AGP_AMD751_STATUS_VBEE 0x0001
105#define AGP_AMD751_ATTBASE 0x04
106#define AGP_AMD751_TLBCTRL 0x0c
107
108
109#endif /* !_PCI_AGPREG_H_ */
| 92
93/*
94 * Memory mapped register offsets for AMD 751 chipset.
95 */
96#define AGP_AMD751_CAPS 0x00
97#define AGP_AMD751_CAPS_EHI 0x0800
98#define AGP_AMD751_CAPS_P2P 0x0400
99#define AGP_AMD751_CAPS_MPC 0x0200
100#define AGP_AMD751_CAPS_VBE 0x0100
101#define AGP_AMD751_CAPS_REV 0x00ff
102#define AGP_AMD751_STATUS 0x02
103#define AGP_AMD751_STATUS_P2PS 0x0800
104#define AGP_AMD751_STATUS_GCS 0x0400
105#define AGP_AMD751_STATUS_MPS 0x0200
106#define AGP_AMD751_STATUS_VBES 0x0100
107#define AGP_AMD751_STATUS_P2PE 0x0008
108#define AGP_AMD751_STATUS_GCE 0x0004
109#define AGP_AMD751_STATUS_VBEE 0x0001
110#define AGP_AMD751_ATTBASE 0x04
111#define AGP_AMD751_TLBCTRL 0x0c
112
113
114#endif /* !_PCI_AGPREG_H_ */
|