| NOTES (61467) | NOTES (61616) |
|---|---|
| 1# 2# LINT -- config file for checking all the sources, tries to pull in 3# as much of the source tree as it can. 4# | 1# 2# LINT -- config file for checking all the sources, tries to pull in 3# as much of the source tree as it can. 4# |
| 5# $FreeBSD: head/sys/conf/NOTES 61467 2000-06-09 23:47:30Z jhb $ | 5# $FreeBSD: head/sys/conf/NOTES 61616 2000-06-13 09:10:37Z kato $ |
| 6# 7# NB: You probably don't want to try running a kernel built from this 8# file. Instead, you should start from GENERIC, and add options from 9# this file as required. 10# 11 12# 13# This directive is mandatory; it defines the architecture to be --- 162 unchanged lines hidden (view full) --- 176# 177# CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products 178# for i386 machines. 179# 180# CPU_IORT defines I/O clock delay time (NOTE 1). Default values of 181# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively 182# (no clock delay). 183# | 6# 7# NB: You probably don't want to try running a kernel built from this 8# file. Instead, you should start from GENERIC, and add options from 9# this file as required. 10# 11 12# 13# This directive is mandatory; it defines the architecture to be --- 162 unchanged lines hidden (view full) --- 176# 177# CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products 178# for i386 machines. 179# 180# CPU_IORT defines I/O clock delay time (NOTE 1). Default values of 181# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively 182# (no clock delay). 183# |
| 184# CPU_L2_LATENCY specifed the L2 cache latency value. This option is used 185# only when CPU_PPRO2CELERON is defined and Mendocino Celeron is detected. 186# The default value is 5. 187# |
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| 184# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination 185# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE 186# 1). 187# | 188# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination 189# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE 190# 1). 191# |
| 192# CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs. This option 193# is useful when you use Socket 8 to Socket 370 converter, because most Pentium 194# Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs. 195# |
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| 188# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1). 189# 190# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU 191# enters suspend mode following execution of HALT instruction. 192# 193# CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD 194# K5/K6/K6-2 cpus. 195# --- 27 unchanged lines hidden (view full) --- 223options CPU_BLUELIGHTNING_FPU_OP_CACHE 224options CPU_BLUELIGHTNING_3X 225options CPU_BTB_EN 226options CPU_DIRECT_MAPPED_CACHE 227options CPU_DISABLE_5X86_LSSER 228options CPU_FASTER_5X86_FPU 229options CPU_I486_ON_386 230options CPU_IORT | 196# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1). 197# 198# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU 199# enters suspend mode following execution of HALT instruction. 200# 201# CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD 202# K5/K6/K6-2 cpus. 203# --- 27 unchanged lines hidden (view full) --- 231options CPU_BLUELIGHTNING_FPU_OP_CACHE 232options CPU_BLUELIGHTNING_3X 233options CPU_BTB_EN 234options CPU_DIRECT_MAPPED_CACHE 235options CPU_DISABLE_5X86_LSSER 236options CPU_FASTER_5X86_FPU 237options CPU_I486_ON_386 238options CPU_IORT |
| 239options CPU_L2_LATENCY=5 |
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| 231options CPU_LOOP_EN | 240options CPU_LOOP_EN |
| 241options CPU_PPRO2CELERON |
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| 232options CPU_RSTK_EN 233options CPU_SUSP_HLT 234options CPU_WT_ALLOC 235options CYRIX_CACHE_WORKS 236options CYRIX_CACHE_REALLY_WORKS 237#options NO_F00F_HACK 238 239# --- 2136 unchanged lines hidden --- | 242options CPU_RSTK_EN 243options CPU_SUSP_HLT 244options CPU_WT_ALLOC 245options CYRIX_CACHE_WORKS 246options CYRIX_CACHE_REALLY_WORKS 247#options NO_F00F_HACK 248 249# --- 2136 unchanged lines hidden --- |