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dis_tables.c (265273) dis_tables.c (270186)
1/*
2 *
3 * CDDL HEADER START
4 *
5 * The contents of this file are subject to the terms of the
6 * Common Development and Distribution License (the "License").
7 * You may not use this file except in compliance with the License.
8 *

--- 7 unchanged lines hidden (view full) ---

16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22/*
23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
1/*
2 *
3 * CDDL HEADER START
4 *
5 * The contents of this file are subject to the terms of the
6 * Common Development and Distribution License (the "License").
7 * You may not use this file except in compliance with the License.
8 *

--- 7 unchanged lines hidden (view full) ---

16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22/*
23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright (c) 2012, Joyent, Inc. All rights reserved.
24 */
25
26/*
27 * Copyright (c) 2010, Intel Corporation.
28 * All rights reserved.
29 */
30
31/* Copyright (c) 1988 AT&T */
32/* All Rights Reserved */
33
34/*
25 */
26
27/*
28 * Copyright (c) 2010, Intel Corporation.
29 * All rights reserved.
30 */
31
32/* Copyright (c) 1988 AT&T */
33/* All Rights Reserved */
34
35/*
35 * $FreeBSD: stable/10/sys/cddl/dev/dtrace/x86/dis_tables.c 262542 2014-02-27 01:04:35Z markj $
36 * $FreeBSD: stable/10/sys/cddl/dev/dtrace/x86/dis_tables.c 270186 2014-08-19 23:15:47Z grehan $
36 */
37
38#include "dis_tables.h"
39
40/* BEGIN CSTYLED */
41
42/*
43 * Disassembly begins in dis_distable, which is equivalent to the One-byte

--- 55 unchanged lines hidden (view full) ---

99 IR,
100 OA,
101 AO,
102 MS,
103 SM,
104 Mv,
105 Mw,
106 M, /* register or memory */
37 */
38
39#include "dis_tables.h"
40
41/* BEGIN CSTYLED */
42
43/*
44 * Disassembly begins in dis_distable, which is equivalent to the One-byte

--- 55 unchanged lines hidden (view full) ---

100 IR,
101 OA,
102 AO,
103 MS,
104 SM,
105 Mv,
106 Mw,
107 M, /* register or memory */
108 MG9, /* register or memory in group 9 (prefix optional) */
107 Mb, /* register or memory, always byte sized */
108 MO, /* memory only (no registers) */
109 PREF,
109 Mb, /* register or memory, always byte sized */
110 MO, /* memory only (no registers) */
111 PREF,
110 SWAPGS,
112 SWAPGS_RDTSCP,
111 MONITOR_MWAIT,
112 R,
113 RA,
114 SEG,
115 MR,
116 RM,
113 MONITOR_MWAIT,
114 R,
115 RA,
116 SEG,
117 MR,
118 RM,
119 RM_66r, /* RM, but with a required 0x66 prefix */
117 IA,
118 MA,
119 SD,
120 AD,
121 SA,
122 D,
123 INM,
124 SO,

--- 98 unchanged lines hidden (view full) ---

223 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */
224 VEX_MR, /* VEX mod_rm -> mod_reg */
225 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */
226 VEX_RX, /* VEX mod_reg -> mod_rm */
227 VEX_RR, /* VEX mod_rm -> mod_reg */
228 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */
229 VEX_RM, /* VEX mod_reg -> mod_rm */
230 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */
120 IA,
121 MA,
122 SD,
123 AD,
124 SA,
125 D,
126 INM,
127 SO,

--- 98 unchanged lines hidden (view full) ---

226 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */
227 VEX_MR, /* VEX mod_rm -> mod_reg */
228 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */
229 VEX_RX, /* VEX mod_reg -> mod_rm */
230 VEX_RR, /* VEX mod_rm -> mod_reg */
231 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */
232 VEX_RM, /* VEX mod_reg -> mod_rm */
233 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */
231 VEX_RMX /* VEX VEX.vvvv, mod_rm -> mod_reg */
234 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
235 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */
236 VMxo, /* VMx instruction with optional prefix */
237 SVM /* AMD SVM instructions */
232};
233
234/*
235 * VEX prefixes
236 */
237#define VEX_2bytes 0xC5 /* the first byte of two-byte form */
238#define VEX_3bytes 0xC4 /* the first byte of three-byte form */
239

--- 251 unchanged lines hidden (view full) ---

491};
492
493
494/*
495 * Decode table for 0x0F01 opcodes
496 */
497const instable_t dis_op0F01[8] = {
498
238};
239
240/*
241 * VEX prefixes
242 */
243#define VEX_2bytes 0xC5 /* the first byte of two-byte form */
244#define VEX_3bytes 0xC4 /* the first byte of three-byte form */
245

--- 251 unchanged lines hidden (view full) ---

497};
498
499
500/*
501 * Decode table for 0x0F01 opcodes
502 */
503const instable_t dis_op0F01[8] = {
504
499/* [0] */ TNSZ("sgdt",MO,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",MO,6),
500/* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS),
505/* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6),
506/* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP),
501};
502
503/*
504 * Decode table for 0x0F18 opcodes -- SIMD prefetch
505 */
506const instable_t dis_op0F18[8] = {
507
508/* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF),

--- 14 unchanged lines hidden (view full) ---

523
524const instable_t dis_op0FBA[8] = {
525
526/* [0] */ INVALID, INVALID, INVALID, INVALID,
527/* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb),
528};
529
530/*
507};
508
509/*
510 * Decode table for 0x0F18 opcodes -- SIMD prefetch
511 */
512const instable_t dis_op0F18[8] = {
513
514/* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF),

--- 14 unchanged lines hidden (view full) ---

529
530const instable_t dis_op0FBA[8] = {
531
532/* [0] */ INVALID, INVALID, INVALID, INVALID,
533/* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb),
534};
535
536/*
531 * Decode table for 0x0FC7 opcode
537 * Decode table for 0x0FC7 opcode (group 9)
532 */
533
534const instable_t dis_op0FC7[8] = {
535
536/* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, INVALID,
538 */
539
540const instable_t dis_op0FC7[8] = {
541
542/* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, INVALID,
537/* [4] */ INVALID, INVALID, INVALID, INVALID,
543/* [4] */ INVALID, INVALID, TNS("vmptrld",MG9), TNS("vmptrst",MG9),
538};
539
544};
545
546/*
547 * Decode table for 0x0FC7 opcode (group 9) mode 3
548 */
540
549
550const instable_t dis_op0FC7m3[8] = {
551
552/* [0] */ INVALID, INVALID, INVALID, INVALID,
553/* [4] */ INVALID, INVALID, TNS("rdrand",MG9), INVALID,
554};
555
541/*
556/*
557 * Decode table for 0x0FC7 opcode with 0x66 prefix
558 */
559
560const instable_t dis_op660FC7[8] = {
561
562/* [0] */ INVALID, INVALID, INVALID, INVALID,
563/* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID,
564};
565
566/*
567 * Decode table for 0x0FC7 opcode with 0xF3 prefix
568 */
569
570const instable_t dis_opF30FC7[8] = {
571
572/* [0] */ INVALID, INVALID, INVALID, INVALID,
573/* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID,
574};
575
576/*
542 * Decode table for 0x0FC8 opcode -- 486 bswap instruction
543 *
544 *bit pattern: 0000 1111 1100 1reg
545 */
546const instable_t dis_op0FC8[4] = {
547/* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID,
548};
549

--- 592 unchanged lines hidden (view full) ---

1142/* [68] */ INVALID, INVALID, INVALID, INVALID,
1143/* [6C] */ INVALID, INVALID, INVALID, INVALID,
1144
1145/* [70] */ INVALID, INVALID, INVALID, INVALID,
1146/* [74] */ INVALID, INVALID, INVALID, INVALID,
1147/* [78] */ INVALID, INVALID, INVALID, INVALID,
1148/* [7C] */ INVALID, INVALID, INVALID, INVALID,
1149
577 * Decode table for 0x0FC8 opcode -- 486 bswap instruction
578 *
579 *bit pattern: 0000 1111 1100 1reg
580 */
581const instable_t dis_op0FC8[4] = {
582/* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID,
583};
584

--- 592 unchanged lines hidden (view full) ---

1177/* [68] */ INVALID, INVALID, INVALID, INVALID,
1178/* [6C] */ INVALID, INVALID, INVALID, INVALID,
1179
1180/* [70] */ INVALID, INVALID, INVALID, INVALID,
1181/* [74] */ INVALID, INVALID, INVALID, INVALID,
1182/* [78] */ INVALID, INVALID, INVALID, INVALID,
1183/* [7C] */ INVALID, INVALID, INVALID, INVALID,
1184
1150/* [80] */ INVALID, INVALID, INVALID, INVALID,
1185/* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),INVALID, INVALID,
1151/* [84] */ INVALID, INVALID, INVALID, INVALID,
1152/* [88] */ INVALID, INVALID, INVALID, INVALID,
1153/* [8C] */ INVALID, INVALID, INVALID, INVALID,
1154
1155/* [90] */ INVALID, INVALID, INVALID, INVALID,
1156/* [94] */ INVALID, INVALID, INVALID, INVALID,
1157/* [98] */ INVALID, INVALID, INVALID, INVALID,
1158/* [9C] */ INVALID, INVALID, INVALID, INVALID,

--- 29 unchanged lines hidden (view full) ---

1188};
1189
1190const instable_t dis_opAVX660F38[256] = {
1191/* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
1192/* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
1193/* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
1194/* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16),
1195
1186/* [84] */ INVALID, INVALID, INVALID, INVALID,
1187/* [88] */ INVALID, INVALID, INVALID, INVALID,
1188/* [8C] */ INVALID, INVALID, INVALID, INVALID,
1189
1190/* [90] */ INVALID, INVALID, INVALID, INVALID,
1191/* [94] */ INVALID, INVALID, INVALID, INVALID,
1192/* [98] */ INVALID, INVALID, INVALID, INVALID,
1193/* [9C] */ INVALID, INVALID, INVALID, INVALID,

--- 29 unchanged lines hidden (view full) ---

1223};
1224
1225const instable_t dis_opAVX660F38[256] = {
1226/* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
1227/* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
1228/* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
1229/* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16),
1230
1196/* [10] */ INVALID, INVALID, INVALID, INVALID,
1231/* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16),
1197/* [14] */ INVALID, INVALID, INVALID, TNSZ("vptest",VEX_RRI,16),
1198/* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
1199/* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID,
1200
1201/* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
1202/* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID,
1203/* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
1204/* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),

--- 149 unchanged lines hidden (view full) ---

1354/* [00] */ INVALID, INVALID, INVALID, INVALID,
1355/* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
1356/* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
1357/* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
1358
1359/* [10] */ INVALID, INVALID, INVALID, INVALID,
1360/* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
1361/* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID,
1232/* [14] */ INVALID, INVALID, INVALID, TNSZ("vptest",VEX_RRI,16),
1233/* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
1234/* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID,
1235
1236/* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
1237/* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID,
1238/* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
1239/* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),

--- 149 unchanged lines hidden (view full) ---

1389/* [00] */ INVALID, INVALID, INVALID, INVALID,
1390/* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
1391/* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
1392/* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
1393
1394/* [10] */ INVALID, INVALID, INVALID, INVALID,
1395/* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
1396/* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID,
1362/* [1C] */ INVALID, INVALID, INVALID, INVALID,
1397/* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID,
1363
1364/* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
1365/* [24] */ INVALID, INVALID, INVALID, INVALID,
1366/* [28] */ INVALID, INVALID, INVALID, INVALID,
1367/* [2C] */ INVALID, INVALID, INVALID, INVALID,
1368
1369/* [30] */ INVALID, INVALID, INVALID, INVALID,
1370/* [34] */ INVALID, INVALID, INVALID, INVALID,

--- 70 unchanged lines hidden (view full) ---

1441/* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR),
1442/* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM),
1443/* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM),
1444/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1445}, {
1446/* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8),
1447/* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
1448/* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID,
1398
1399/* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
1400/* [24] */ INVALID, INVALID, INVALID, INVALID,
1401/* [28] */ INVALID, INVALID, INVALID, INVALID,
1402/* [2C] */ INVALID, INVALID, INVALID, INVALID,
1403
1404/* [30] */ INVALID, INVALID, INVALID, INVALID,
1405/* [34] */ INVALID, INVALID, INVALID, INVALID,

--- 70 unchanged lines hidden (view full) ---

1476/* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR),
1477/* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM),
1478/* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM),
1479/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1480}, {
1481/* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8),
1482/* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
1483/* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID,
1449/* [1C] */ INVALID, INVALID, INVALID, TS("nopw", Mw),
1484/* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw),
1450}, {
1451/* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG),
1452/* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID,
1453/* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
1454/* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
1455}, {
1456/* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM),
1457/* [34] */ TNSx("sysenter",NORM), TNSx("sysexit",NORM), INVALID, INVALID,

--- 12 unchanged lines hidden (view full) ---

1470}, {
1471/* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
1472/* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8),
1473/* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
1474/* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8),
1475}, {
1476/* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR),
1477/* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM),
1485}, {
1486/* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG),
1487/* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID,
1488/* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
1489/* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
1490}, {
1491/* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM),
1492/* [34] */ TNSx("sysenter",NORM), TNSx("sysexit",NORM), INVALID, INVALID,

--- 12 unchanged lines hidden (view full) ---

1505}, {
1506/* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
1507/* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8),
1508/* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
1509/* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8),
1510}, {
1511/* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR),
1512/* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM),
1478/* [78] */ TNS("INVALID",XMMO), TNS("INVALID",XMMO), INVALID, INVALID,
1513/* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID,
1479/* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8),
1480}, {
1481/* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D),
1482/* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D),
1483/* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D),
1484/* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D),
1485}, {
1486/* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb),

--- 367 unchanged lines hidden (view full) ---

1854/* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F),
1855}, {
1856/* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw),
1857/* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG),
1858/* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw),
1859/* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG),
1860}, {
1861/* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw),
1514/* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8),
1515}, {
1516/* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D),
1517/* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D),
1518/* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D),
1519/* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D),
1520}, {
1521/* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb),

--- 367 unchanged lines hidden (view full) ---

1889/* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F),
1890}, {
1891/* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw),
1892/* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG),
1893/* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw),
1894/* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG),
1895}, {
1896/* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw),
1862/* [2,4] */ TNS("andb",IA), TS("and",IA), TNS("%es:",OVERRIDE), TNSx("daa",NORM),
1897/* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM),
1863/* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw),
1864/* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM),
1865}, {
1866/* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw),
1898/* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw),
1899/* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM),
1900}, {
1901/* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw),
1867/* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNS("%ss:",OVERRIDE), TNSx("aaa",NORM),
1902/* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM),
1868/* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw),
1903/* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw),
1869/* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNS("%ds:",OVERRIDE), TNSx("aas",NORM),
1904/* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM),
1870}, {
1871/* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
1872/* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
1873/* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
1874/* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
1875}, {
1876/* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),
1877/* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),

--- 1022 unchanged lines hidden (view full) ---

2900 dp++;
2901 }
2902 }
2903#ifdef DIS_TEXT
2904 if (strcmp(dp->it_name, "INVALID") == 0)
2905 goto error;
2906#endif
2907 switch (dp->it_adrmode) {
1905}, {
1906/* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
1907/* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
1908/* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
1909/* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
1910}, {
1911/* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),
1912/* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),

--- 1022 unchanged lines hidden (view full) ---

2935 dp++;
2936 }
2937 }
2938#ifdef DIS_TEXT
2939 if (strcmp(dp->it_name, "INVALID") == 0)
2940 goto error;
2941#endif
2942 switch (dp->it_adrmode) {
2943 case RM_66r:
2908 case XMM_66r:
2909 case XMMM_66r:
2910 if (opnd_size_prefix == 0) {
2911 goto error;
2912 }
2913 break;
2914 case XMM_66o:
2915 if (opnd_size_prefix == 0) {

--- 133 unchanged lines hidden (view full) ---

3049 } else if (opnd_size_prefix) {
3050 dp = (instable_t *)&dis_opSIMDdata16[off];
3051 opnd_size_prefix = 0;
3052 if (opnd_size == SIZE16)
3053 opnd_size = SIZE32;
3054 }
3055 break;
3056
2944 case XMM_66r:
2945 case XMMM_66r:
2946 if (opnd_size_prefix == 0) {
2947 goto error;
2948 }
2949 break;
2950 case XMM_66o:
2951 if (opnd_size_prefix == 0) {

--- 133 unchanged lines hidden (view full) ---

3085 } else if (opnd_size_prefix) {
3086 dp = (instable_t *)&dis_opSIMDdata16[off];
3087 opnd_size_prefix = 0;
3088 if (opnd_size == SIZE16)
3089 opnd_size = SIZE32;
3090 }
3091 break;
3092
3093 case MG9:
3094 /*
3095 * More horribleness: the group 9 (0xF0 0xC7) instructions are
3096 * allowed an optional prefix of 0x66 or 0xF3. This is similar
3097 * to the SIMD business described above, but with a different
3098 * addressing mode (and an indirect table), so we deal with it
3099 * separately (if similarly).
3100 *
3101 * Intel further complicated this with the release of Ivy Bridge
3102 * where they overloaded these instructions based on the ModR/M
3103 * bytes. The VMX instructions have a mode of 0 since they are
3104 * memory instructions but rdrand instructions have a mode of
3105 * 0b11 (REG_ONLY) because they only operate on registers. While
3106 * there are different prefix formats, for now it is sufficient
3107 * to use a single different table.
3108 */
3109
3110 /*
3111 * Calculate our offset in dis_op0FC7 (the group 9 table)
3112 */
3113 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7))
3114 goto error;
3115
3116 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) /
3117 sizeof (instable_t);
3118
3119 /*
3120 * If we have a mode of 0b11 then we have to rewrite this.
3121 */
3122 dtrace_get_modrm(x, &mode, &reg, &r_m);
3123 if (mode == REG_ONLY) {
3124 dp = (instable_t *)&dis_op0FC7m3[off];
3125 break;
3126 }
3127
3128 /*
3129 * Rewrite if this instruction used one of the magic prefixes.
3130 */
3131 if (rep_prefix) {
3132 if (rep_prefix == 0xf3)
3133 dp = (instable_t *)&dis_opF30FC7[off];
3134 else
3135 goto error;
3136 rep_prefix = 0;
3137 } else if (opnd_size_prefix) {
3138 dp = (instable_t *)&dis_op660FC7[off];
3139 opnd_size_prefix = 0;
3140 if (opnd_size == SIZE16)
3141 opnd_size = SIZE32;
3142 }
3143 break;
3144
3145
3057 case MMOSH:
3058 /*
3059 * As with the "normal" SIMD instructions, the MMX
3060 * shuffle instructions are overloaded. These
3061 * instructions, however, are special in that they use
3062 * an extra byte, and thus an extra table. As of this
3063 * writing, they only use the opnd_size prefix.
3064 */

--- 364 unchanged lines hidden (view full) ---

3429 case Mw:
3430 wbit = WBIT(opcode2);
3431just_mem:
3432 dtrace_get_modrm(x, &mode, &reg, &r_m);
3433 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3434 dtrace_get_operand(x, mode, r_m, wbit, 0);
3435 break;
3436
3146 case MMOSH:
3147 /*
3148 * As with the "normal" SIMD instructions, the MMX
3149 * shuffle instructions are overloaded. These
3150 * instructions, however, are special in that they use
3151 * an extra byte, and thus an extra table. As of this
3152 * writing, they only use the opnd_size prefix.
3153 */

--- 364 unchanged lines hidden (view full) ---

3518 case Mw:
3519 wbit = WBIT(opcode2);
3520just_mem:
3521 dtrace_get_modrm(x, &mode, &reg, &r_m);
3522 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3523 dtrace_get_operand(x, mode, r_m, wbit, 0);
3524 break;
3525
3437 case SWAPGS:
3526 case SWAPGS_RDTSCP:
3438 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) {
3439#ifdef DIS_TEXT
3440 (void) strncpy(x->d86_mnem, "swapgs", OPLEN);
3441#endif
3442 NOMEM;
3443 break;
3527 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) {
3528#ifdef DIS_TEXT
3529 (void) strncpy(x->d86_mnem, "swapgs", OPLEN);
3530#endif
3531 NOMEM;
3532 break;
3533 } else if (mode == 3 && r_m == 1) {
3534#ifdef DIS_TEXT
3535 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN);
3536#endif
3537 NOMEM;
3538 break;
3444 }
3539 }
3540
3445 /*FALLTHROUGH*/
3446
3447 /* prefetch instruction - memory operand, but no memory acess */
3448 case PREF:
3449 NOMEM;
3450 /*FALLTHROUGH*/
3451
3452 /* single memory or register operand */
3453 case M:
3541 /*FALLTHROUGH*/
3542
3543 /* prefetch instruction - memory operand, but no memory acess */
3544 case PREF:
3545 NOMEM;
3546 /*FALLTHROUGH*/
3547
3548 /* single memory or register operand */
3549 case M:
3550 case MG9:
3454 wbit = LONG_OPND;
3455 goto just_mem;
3456
3457 /* single memory or register byte operand */
3458 case Mb:
3459 wbit = BYTE_OPND;
3460 goto just_mem;
3461
3551 wbit = LONG_OPND;
3552 goto just_mem;
3553
3554 /* single memory or register byte operand */
3555 case Mb:
3556 wbit = BYTE_OPND;
3557 goto just_mem;
3558
3559 case VMx:
3560 if (mode == 3) {
3561#ifdef DIS_TEXT
3562 char *vminstr;
3563
3564 switch (r_m) {
3565 case 1:
3566 vminstr = "vmcall";
3567 break;
3568 case 2:
3569 vminstr = "vmlaunch";
3570 break;
3571 case 3:
3572 vminstr = "vmresume";
3573 break;
3574 case 4:
3575 vminstr = "vmxoff";
3576 break;
3577 default:
3578 goto error;
3579 }
3580
3581 (void) strncpy(x->d86_mnem, vminstr, OPLEN);
3582#else
3583 if (r_m < 1 || r_m > 4)
3584 goto error;
3585#endif
3586
3587 NOMEM;
3588 break;
3589 }
3590 /*FALLTHROUGH*/
3591 case SVM:
3592 if (mode == 3) {
3593#ifdef DIS_TEXT
3594 char *vinstr;
3595
3596 switch (r_m) {
3597 case 0:
3598 vinstr = "vmrun";
3599 break;
3600 case 1:
3601 vinstr = "vmmcall";
3602 break;
3603 case 2:
3604 vinstr = "vmload";
3605 break;
3606 case 3:
3607 vinstr = "vmsave";
3608 break;
3609 case 4:
3610 vinstr = "stgi";
3611 break;
3612 case 5:
3613 vinstr = "clgi";
3614 break;
3615 case 6:
3616 vinstr = "skinit";
3617 break;
3618 case 7:
3619 vinstr = "invlpga";
3620 break;
3621 }
3622
3623 (void) strncpy(x->d86_mnem, vinstr, OPLEN);
3624#endif
3625 NOMEM;
3626 break;
3627 }
3628 /*FALLTHROUGH*/
3462 case MONITOR_MWAIT:
3463 if (mode == 3) {
3464 if (r_m == 0) {
3465#ifdef DIS_TEXT
3466 (void) strncpy(x->d86_mnem, "monitor", OPLEN);
3467#endif
3468 NOMEM;
3469 break;

--- 122 unchanged lines hidden (view full) ---

3592 case MR:
3593 if (vex_prefetch)
3594 x->d86_got_modrm = 1;
3595 wbit = LONG_OPND;
3596 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
3597 break;
3598
3599 case RM:
3629 case MONITOR_MWAIT:
3630 if (mode == 3) {
3631 if (r_m == 0) {
3632#ifdef DIS_TEXT
3633 (void) strncpy(x->d86_mnem, "monitor", OPLEN);
3634#endif
3635 NOMEM;
3636 break;

--- 122 unchanged lines hidden (view full) ---

3759 case MR:
3760 if (vex_prefetch)
3761 x->d86_got_modrm = 1;
3762 wbit = LONG_OPND;
3763 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
3764 break;
3765
3766 case RM:
3767 case RM_66r:
3600 wbit = LONG_OPND;
3601 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3602 break;
3603
3604 /* MMX/SIMD-Int memory or mm reg to mm reg */
3605 case MM:
3606 case MMO:
3607#ifdef DIS_TEXT

--- 687 unchanged lines hidden (view full) ---

4295 (dp == &dis_opAVX660F[0x5A]) ||
4296 (dp == &dis_opAVX660F[0xE6])) {
4297 /* vcvtpd2dq <ymm>, <xmm> */
4298 /* or vcvtpd2ps <ymm>, <xmm> */
4299 /* or vcvttpd2dq <ymm>, <xmm> */
4300 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1);
4301 dtrace_get_operand(x, mode, r_m, wbit, 0);
4302 } else if ((dp == &dis_opAVXF30F[0xE6]) ||
3768 wbit = LONG_OPND;
3769 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3770 break;
3771
3772 /* MMX/SIMD-Int memory or mm reg to mm reg */
3773 case MM:
3774 case MMO:
3775#ifdef DIS_TEXT

--- 687 unchanged lines hidden (view full) ---

4463 (dp == &dis_opAVX660F[0x5A]) ||
4464 (dp == &dis_opAVX660F[0xE6])) {
4465 /* vcvtpd2dq <ymm>, <xmm> */
4466 /* or vcvtpd2ps <ymm>, <xmm> */
4467 /* or vcvttpd2dq <ymm>, <xmm> */
4468 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1);
4469 dtrace_get_operand(x, mode, r_m, wbit, 0);
4470 } else if ((dp == &dis_opAVXF30F[0xE6]) ||
4303 (dp == &dis_opAVX0F[0x5][0xA])) {
4471 (dp == &dis_opAVX0F[0x5][0xA]) ||
4472 (dp == &dis_opAVX660F38[0x13])) {
4304 /* vcvtdq2pd <xmm>, <ymm> */
4305 /* or vcvtps2pd <xmm>, <ymm> */
4306 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4307 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
4308 } else if (dp == &dis_opAVX660F[0x6E]) {
4309 /* vmovd/q <reg/mem 32/64>, <xmm> */
4310#ifdef DIS_TEXT
4311 if (vex_W)

--- 68 unchanged lines hidden (view full) ---

4380 dtrace_get_modrm(x, &mode, &reg, &r_m);
4381 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4382 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4383 dtrace_get_operand(x, mode, r_m, wbit, 0);
4384 break;
4385
4386 case VEX_RX:
4387 /* ModR/M.rm := op(ModR/M.reg) */
4473 /* vcvtdq2pd <xmm>, <ymm> */
4474 /* or vcvtps2pd <xmm>, <ymm> */
4475 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4476 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
4477 } else if (dp == &dis_opAVX660F[0x6E]) {
4478 /* vmovd/q <reg/mem 32/64>, <xmm> */
4479#ifdef DIS_TEXT
4480 if (vex_W)

--- 68 unchanged lines hidden (view full) ---

4549 dtrace_get_modrm(x, &mode, &reg, &r_m);
4550 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4551 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4552 dtrace_get_operand(x, mode, r_m, wbit, 0);
4553 break;
4554
4555 case VEX_RX:
4556 /* ModR/M.rm := op(ModR/M.reg) */
4388 if (dp == &dis_opAVX660F3A[0x19]) { /* vextractf128 */
4557 /* vextractf128 || vcvtps2ph */
4558 if (dp == &dis_opAVX660F3A[0x19] ||
4559 dp == &dis_opAVX660F3A[0x1d]) {
4389 x->d86_numopnds = 3;
4390
4391 dtrace_get_modrm(x, &mode, &reg, &r_m);
4392 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4393
4394 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
4395 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4396

--- 445 unchanged lines hidden --- 		4560 x->d86_numopnds = 3;
4561
4562 dtrace_get_modrm(x, &mode, &reg, &r_m);
4563 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4564
4565 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
4566 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4567

--- 445 unchanged lines hidden ---