1/*
2 *
3 * CDDL HEADER START
4 *
5 * The contents of this file are subject to the terms of the
6 * Common Development and Distribution License (the "License").
7 * You may not use this file except in compliance with the License.
8 *

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16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22/*
23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26/*
27 * Copyright (c) 2010, Intel Corporation.
28 * All rights reserved.
29 */
30
31/* Copyright (c) 1988 AT&T */
32/* All Rights Reserved */
33
34/*
35 * $FreeBSD: stable/10/sys/cddl/dev/dtrace/x86/dis_tables.c 262542 2014-02-27 01:04:35Z markj $
36 */
37
38#include "dis_tables.h"
39
40/* BEGIN CSTYLED */
41
42/*
43 * Disassembly begins in dis_distable, which is equivalent to the One-byte

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99 IR,
100 OA,
101 AO,
102 MS,
103 SM,
104 Mv,
105 Mw,
106 M, /* register or memory */
107 Mb, /* register or memory, always byte sized */
108 MO, /* memory only (no registers) */
109 PREF,
110 SWAPGS,
111 MONITOR_MWAIT,
112 R,
113 RA,
114 SEG,
115 MR,
116 RM,
117 IA,
118 MA,
119 SD,
120 AD,
121 SA,
122 D,
123 INM,
124 SO,

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223 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */
224 VEX_MR, /* VEX mod_rm -> mod_reg */
225 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */
226 VEX_RX, /* VEX mod_reg -> mod_rm */
227 VEX_RR, /* VEX mod_rm -> mod_reg */
228 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */
229 VEX_RM, /* VEX mod_reg -> mod_rm */
230 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */
231 VEX_RMX /* VEX VEX.vvvv, mod_rm -> mod_reg */
232};
233
234/*
235 * VEX prefixes
236 */
237#define VEX_2bytes 0xC5 /* the first byte of two-byte form */
238#define VEX_3bytes 0xC4 /* the first byte of three-byte form */
239

--- 251 unchanged lines hidden (view full) ---

491};
492
493
494/*
495 * Decode table for 0x0F01 opcodes
496 */
497const instable_t dis_op0F01[8] = {
498
499/* [0] */ TNSZ("sgdt",MO,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",MO,6),
500/* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS),
501};
502
503/*
504 * Decode table for 0x0F18 opcodes -- SIMD prefetch
505 */
506const instable_t dis_op0F18[8] = {
507
508/* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF),

--- 14 unchanged lines hidden (view full) ---

523
524const instable_t dis_op0FBA[8] = {
525
526/* [0] */ INVALID, INVALID, INVALID, INVALID,
527/* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb),
528};
529
530/*
531 * Decode table for 0x0FC7 opcode
532 */
533
534const instable_t dis_op0FC7[8] = {
535
536/* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, INVALID,
537/* [4] */ INVALID, INVALID, INVALID, INVALID,
538};
539
540
541/*
542 * Decode table for 0x0FC8 opcode -- 486 bswap instruction
543 *
544 *bit pattern: 0000 1111 1100 1reg
545 */
546const instable_t dis_op0FC8[4] = {
547/* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID,
548};
549

--- 592 unchanged lines hidden (view full) ---

1142/* [68] */ INVALID, INVALID, INVALID, INVALID,
1143/* [6C] */ INVALID, INVALID, INVALID, INVALID,
1144
1145/* [70] */ INVALID, INVALID, INVALID, INVALID,
1146/* [74] */ INVALID, INVALID, INVALID, INVALID,
1147/* [78] */ INVALID, INVALID, INVALID, INVALID,
1148/* [7C] */ INVALID, INVALID, INVALID, INVALID,
1149
1150/* [80] */ INVALID, INVALID, INVALID, INVALID,
1151/* [84] */ INVALID, INVALID, INVALID, INVALID,
1152/* [88] */ INVALID, INVALID, INVALID, INVALID,
1153/* [8C] */ INVALID, INVALID, INVALID, INVALID,
1154
1155/* [90] */ INVALID, INVALID, INVALID, INVALID,
1156/* [94] */ INVALID, INVALID, INVALID, INVALID,
1157/* [98] */ INVALID, INVALID, INVALID, INVALID,
1158/* [9C] */ INVALID, INVALID, INVALID, INVALID,

--- 29 unchanged lines hidden (view full) ---

1188};
1189
1190const instable_t dis_opAVX660F38[256] = {
1191/* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
1192/* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
1193/* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
1194/* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16),
1195
1196/* [10] */ INVALID, INVALID, INVALID, INVALID,
1197/* [14] */ INVALID, INVALID, INVALID, TNSZ("vptest",VEX_RRI,16),
1198/* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
1199/* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID,
1200
1201/* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
1202/* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID,
1203/* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
1204/* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),

--- 149 unchanged lines hidden (view full) ---

1354/* [00] */ INVALID, INVALID, INVALID, INVALID,
1355/* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
1356/* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
1357/* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
1358
1359/* [10] */ INVALID, INVALID, INVALID, INVALID,
1360/* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
1361/* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID,
1362/* [1C] */ INVALID, INVALID, INVALID, INVALID,
1363
1364/* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
1365/* [24] */ INVALID, INVALID, INVALID, INVALID,
1366/* [28] */ INVALID, INVALID, INVALID, INVALID,
1367/* [2C] */ INVALID, INVALID, INVALID, INVALID,
1368
1369/* [30] */ INVALID, INVALID, INVALID, INVALID,
1370/* [34] */ INVALID, INVALID, INVALID, INVALID,

--- 70 unchanged lines hidden (view full) ---

1441/* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR),
1442/* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM),
1443/* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM),
1444/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1445}, {
1446/* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8),
1447/* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
1448/* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID,
1449/* [1C] */ INVALID, INVALID, INVALID, TS("nopw", Mw),
1450}, {
1451/* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG),
1452/* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID,
1453/* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
1454/* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
1455}, {
1456/* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM),
1457/* [34] */ TNSx("sysenter",NORM), TNSx("sysexit",NORM), INVALID, INVALID,

--- 12 unchanged lines hidden (view full) ---

1470}, {
1471/* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
1472/* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8),
1473/* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
1474/* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8),
1475}, {
1476/* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR),
1477/* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM),
1478/* [78] */ TNS("INVALID",XMMO), TNS("INVALID",XMMO), INVALID, INVALID,
1479/* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8),
1480}, {
1481/* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D),
1482/* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D),
1483/* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D),
1484/* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D),
1485}, {
1486/* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb),

--- 367 unchanged lines hidden (view full) ---

1854/* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F),
1855}, {
1856/* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw),
1857/* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG),
1858/* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw),
1859/* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG),
1860}, {
1861/* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw),
1862/* [2,4] */ TNS("andb",IA), TS("and",IA), TNS("%es:",OVERRIDE), TNSx("daa",NORM),
1863/* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw),
1864/* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM),
1865}, {
1866/* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw),
1867/* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNS("%ss:",OVERRIDE), TNSx("aaa",NORM),
1868/* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw),
1869/* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNS("%ds:",OVERRIDE), TNSx("aas",NORM),
1870}, {
1871/* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
1872/* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
1873/* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
1874/* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
1875}, {
1876/* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),
1877/* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),

--- 1022 unchanged lines hidden (view full) ---

2900 dp++;
2901 }
2902 }
2903#ifdef DIS_TEXT
2904 if (strcmp(dp->it_name, "INVALID") == 0)
2905 goto error;
2906#endif
2907 switch (dp->it_adrmode) {
2908 case XMM_66r:
2909 case XMMM_66r:
2910 if (opnd_size_prefix == 0) {
2911 goto error;
2912 }
2913 break;
2914 case XMM_66o:
2915 if (opnd_size_prefix == 0) {

--- 133 unchanged lines hidden (view full) ---

3049 } else if (opnd_size_prefix) {
3050 dp = (instable_t *)&dis_opSIMDdata16[off];
3051 opnd_size_prefix = 0;
3052 if (opnd_size == SIZE16)
3053 opnd_size = SIZE32;
3054 }
3055 break;
3056
3057 case MMOSH:
3058 /*
3059 * As with the "normal" SIMD instructions, the MMX
3060 * shuffle instructions are overloaded. These
3061 * instructions, however, are special in that they use
3062 * an extra byte, and thus an extra table. As of this
3063 * writing, they only use the opnd_size prefix.
3064 */

--- 364 unchanged lines hidden (view full) ---

3429 case Mw:
3430 wbit = WBIT(opcode2);
3431just_mem:
3432 dtrace_get_modrm(x, &mode, &reg, &r_m);
3433 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3434 dtrace_get_operand(x, mode, r_m, wbit, 0);
3435 break;
3436
3437 case SWAPGS:
3438 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) {
3439#ifdef DIS_TEXT
3440 (void) strncpy(x->d86_mnem, "swapgs", OPLEN);
3441#endif
3442 NOMEM;
3443 break;
3444 }
3445 /*FALLTHROUGH*/
3446
3447 /* prefetch instruction - memory operand, but no memory acess */
3448 case PREF:
3449 NOMEM;
3450 /*FALLTHROUGH*/
3451
3452 /* single memory or register operand */
3453 case M:
3454 wbit = LONG_OPND;
3455 goto just_mem;
3456
3457 /* single memory or register byte operand */
3458 case Mb:
3459 wbit = BYTE_OPND;
3460 goto just_mem;
3461
3462 case MONITOR_MWAIT:
3463 if (mode == 3) {
3464 if (r_m == 0) {
3465#ifdef DIS_TEXT
3466 (void) strncpy(x->d86_mnem, "monitor", OPLEN);
3467#endif
3468 NOMEM;
3469 break;

--- 122 unchanged lines hidden (view full) ---

3592 case MR:
3593 if (vex_prefetch)
3594 x->d86_got_modrm = 1;
3595 wbit = LONG_OPND;
3596 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
3597 break;
3598
3599 case RM:
3600 wbit = LONG_OPND;
3601 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3602 break;
3603
3604 /* MMX/SIMD-Int memory or mm reg to mm reg */
3605 case MM:
3606 case MMO:
3607#ifdef DIS_TEXT

--- 687 unchanged lines hidden (view full) ---

4295 (dp == &dis_opAVX660F[0x5A]) ||
4296 (dp == &dis_opAVX660F[0xE6])) {
4297 /* vcvtpd2dq <ymm>, <xmm> */
4298 /* or vcvtpd2ps <ymm>, <xmm> */
4299 /* or vcvttpd2dq <ymm>, <xmm> */
4300 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1);
4301 dtrace_get_operand(x, mode, r_m, wbit, 0);
4302 } else if ((dp == &dis_opAVXF30F[0xE6]) ||
4303 (dp == &dis_opAVX0F[0x5][0xA])) {
4304 /* vcvtdq2pd <xmm>, <ymm> */
4305 /* or vcvtps2pd <xmm>, <ymm> */
4306 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4307 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
4308 } else if (dp == &dis_opAVX660F[0x6E]) {
4309 /* vmovd/q <reg/mem 32/64>, <xmm> */
4310#ifdef DIS_TEXT
4311 if (vex_W)

--- 68 unchanged lines hidden (view full) ---

4380 dtrace_get_modrm(x, &mode, &reg, &r_m);
4381 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4382 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4383 dtrace_get_operand(x, mode, r_m, wbit, 0);
4384 break;
4385
4386 case VEX_RX:
4387 /* ModR/M.rm := op(ModR/M.reg) */
4388 if (dp == &dis_opAVX660F3A[0x19]) { /* vextractf128 */
4389 x->d86_numopnds = 3;
4390
4391 dtrace_get_modrm(x, &mode, &reg, &r_m);
4392 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4393
4394 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
4395 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4396

--- 445 unchanged lines hidden ---