1/*
2 * Copyright (c) 2010 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Semihalf under sponsorship from
6 * the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * Marvell SheevaPlug Device Tree Source.
30 *
| 1/*
2 * Copyright (c) 2010 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Semihalf under sponsorship from
6 * the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * Marvell SheevaPlug Device Tree Source.
30 *
|
31 * $FreeBSD: head/sys/boot/fdt/dts/sheevaplug.dts 227730 2011-11-19 16:30:06Z raj $
| 31 * $FreeBSD: head/sys/boot/fdt/dts/sheevaplug.dts 235609 2012-05-18 14:41:14Z gber $
|
32 */
33
34/dts-v1/;
35
36/ {
37 model = "mrvl,SheevaPlug";
38 compatible = "SheevaPlug";
39 #address-cells = <1>;
40 #size-cells = <1>;
41
42 aliases {
43 ethernet0 = &enet0;
44 mpp = &MPP;
45 serial0 = &serial0;
46 serial1 = &serial1;
47 soc = &SOC;
48 sram = &SRAM;
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 cpu@0 {
56 device_type = "cpu";
57 compatible = "ARM,88FR131";
58 reg = <0x0>;
59 d-cache-line-size = <32>; // 32 bytes
60 i-cache-line-size = <32>; // 32 bytes
61 d-cache-size = <0x4000>; // L1, 16K
62 i-cache-size = <0x4000>; // L1, 16K
63 timebase-frequency = <0>;
64 bus-frequency = <0>;
65 clock-frequency = <0>;
66 };
67 };
68
69 memory {
70 device_type = "memory";
71 reg = <0x0 0x20000000>; // 512M at 0x0
72 };
73
| 32 */
33
34/dts-v1/;
35
36/ {
37 model = "mrvl,SheevaPlug";
38 compatible = "SheevaPlug";
39 #address-cells = <1>;
40 #size-cells = <1>;
41
42 aliases {
43 ethernet0 = &enet0;
44 mpp = &MPP;
45 serial0 = &serial0;
46 serial1 = &serial1;
47 soc = &SOC;
48 sram = &SRAM;
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 cpu@0 {
56 device_type = "cpu";
57 compatible = "ARM,88FR131";
58 reg = <0x0>;
59 d-cache-line-size = <32>; // 32 bytes
60 i-cache-line-size = <32>; // 32 bytes
61 d-cache-size = <0x4000>; // L1, 16K
62 i-cache-size = <0x4000>; // L1, 16K
63 timebase-frequency = <0>;
64 bus-frequency = <0>;
65 clock-frequency = <0>;
66 };
67 };
68
69 memory {
70 device_type = "memory";
71 reg = <0x0 0x20000000>; // 512M at 0x0
72 };
73
|
74 localbus@f1000000 {
| 74 localbus@0 {
|
75 #address-cells = <2>;
76 #size-cells = <1>;
77 compatible = "mrvl,lbc";
| 75 #address-cells = <2>;
76 #size-cells = <1>;
77 compatible = "mrvl,lbc";
|
| 78 bank-count = <3>;
|
78
79 /* This reflects CPU decode windows setup. */
| 79
80 /* This reflects CPU decode windows setup. */
|
80 ranges = <0x0 0x0f 0xf9300000 0x00100000
81 0x1 0x1e 0xfa000000 0x00100000
82 0x2 0x1d 0xfa100000 0x02000000
83 0x3 0x1b 0xfc100000 0x00000400>;
| 81 ranges = <0x0 0x2f 0xf9300000 0x00100000>;
|
84
| 82
|
85 nor@0,0 {
| 83 nand@0,0 {
|
86 #address-cells = <1>;
87 #size-cells = <1>;
| 84 #address-cells = <1>;
85 #size-cells = <1>;
|
88 compatible = "cfi-flash";
| 86 compatible = "mrvl,nfc";
|
89 reg = <0x0 0x0 0x00100000>;
90 bank-width = <2>;
91 device-width = <1>;
| 87 reg = <0x0 0x0 0x00100000>;
88 bank-width = <2>;
89 device-width = <1>;
|
92 };
| |
93
| 90
|
94 led@1,0 {
95 #address-cells = <1>;
96 #size-cells = <1>;
97 compatible = "led";
98 reg = <0x1 0x0 0x00100000>;
99 };
| |
100
| 91
|
101 nor@2,0 {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 compatible = "cfi-flash";
105 reg = <0x2 0x0 0x02000000>;
106 bank-width = <2>;
107 device-width = <1>;
| |
108 };
| 92 };
|
109
110 nand@3,0 {
111 #address-cells = <1>;
112 #size-cells = <1>;
113 reg = <0x3 0x0 0x00100000>;
114 bank-width = <2>;
115 device-width = <1>;
116 };
| |
117 };
118
119 SOC: soc88f6281@f1000000 {
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "simple-bus";
123 ranges = <0x0 0xf1000000 0x00100000>;
124 bus-frequency = <0>;
125
126 PIC: pic@20200 {
127 interrupt-controller;
128 #address-cells = <0>;
129 #interrupt-cells = <1>;
130 reg = <0x20200 0x3c>;
131 compatible = "mrvl,pic";
132 };
133
134 timer@20300 {
135 compatible = "mrvl,timer";
136 reg = <0x20300 0x30>;
137 interrupts = <1>;
138 interrupt-parent = <&PIC>;
139 mrvl,has-wdt;
140 };
141
142 MPP: mpp@10000 {
143 #pin-cells = <2>;
144 compatible = "mrvl,mpp";
145 reg = <0x10000 0x34>;
146 pin-count = <50>;
147 pin-map = <
148 0 1 /* MPP[0]: NF_IO[2] */
149 1 1 /* MPP[1]: NF_IO[3] */
150 2 1 /* MPP[2]: NF_IO[4] */
151 3 1 /* MPP[3]: NF_IO[5] */
152 4 1 /* MPP[4]: NF_IO[6] */
153 5 1 /* MPP[5]: NF_IO[7] */
154 6 1 /* MPP[6]: SYSRST_OUTn */
155 8 2 /* MPP[8]: UA0_RTS */
156 9 2 /* MPP[9]: UA0_CTS */
157 10 3 /* MPP[10]: UA0_TXD */
158 11 3 /* MPP[11]: UA0_RXD */
159 12 1 /* MPP[12]: SD_CLK */
160 13 1 /* MPP[13]: SD_CMD */
161 14 1 /* MPP[14]: SD_D[0] */
162 15 1 /* MPP[15]: SD_D[1] */
163 16 1 /* MPP[16]: SD_D[2] */
164 17 1 /* MPP[17]: SD_D[3] */
165 18 1 /* MPP[18]: NF_IO[0] */
166 19 1 /* MPP[19]: NF_IO[1] */
167 29 1 >; /* MPP[29]: TSMP[9] */
168 };
169
170 GPIO: gpio@10100 {
171 #gpio-cells = <3>;
172 compatible = "mrvl,gpio";
173 reg = <0x10100 0x20>;
174 gpio-controller;
175 interrupts = <35 36 37 38 39 40 41>;
176 interrupt-parent = <&PIC>;
177 };
178
179 rtc@10300 {
180 compatible = "mrvl,rtc";
181 reg = <0x10300 0x08>;
182 };
183
184 twsi@11000 {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 compatible = "mrvl,twsi";
188 reg = <0x11000 0x20>;
189 interrupts = <43>;
190 interrupt-parent = <&PIC>;
191 };
192
193 enet0: ethernet@72000 {
194 #address-cells = <1>;
195 #size-cells = <1>;
196 model = "V2";
197 compatible = "mrvl,ge";
198 reg = <0x72000 0x2000>;
199 ranges = <0x0 0x72000 0x2000>;
200 local-mac-address = [ 00 00 00 00 00 00 ];
201 interrupts = <12 13 14 11 46>;
202 interrupt-parent = <&PIC>;
203 phy-handle = <&phy0>;
204
205 mdio@0 {
206 #address-cells = <1>;
207 #size-cells = <0>;
208 compatible = "mrvl,mdio";
209
210 phy0: ethernet-phy@0 {
211 reg = <0x0>;
212 };
213 };
214 };
215
216 serial0: serial@12000 {
217 compatible = "ns16550";
218 reg = <0x12000 0x20>;
219 reg-shift = <2>;
220 clock-frequency = <0>;
221 interrupts = <33>;
222 interrupt-parent = <&PIC>;
223 };
224
225 serial1: serial@12100 {
226 compatible = "ns16550";
227 reg = <0x12100 0x20>;
228 reg-shift = <2>;
229 clock-frequency = <0>;
230 interrupts = <34>;
231 interrupt-parent = <&PIC>;
232 };
233
234 crypto@30000 {
235 compatible = "mrvl,cesa";
236 reg = <0x30000 0x10000>;
237 interrupts = <22>;
238 interrupt-parent = <&PIC>;
239
240 sram-handle = <&SRAM>;
241 };
242
243 usb@50000 {
244 compatible = "mrvl,usb-ehci", "usb-ehci";
245 reg = <0x50000 0x1000>;
246 interrupts = <48 19>;
247 interrupt-parent = <&PIC>;
248 };
249
250 xor@60000 {
251 compatible = "mrvl,xor";
252 reg = <0x60000 0x1000>;
253 interrupts = <5 6 7 8>;
254 interrupt-parent = <&PIC>;
255 };
256 };
257
258 SRAM: sram@fd000000 {
259 compatible = "mrvl,cesa-sram";
260 reg = <0xfd000000 0x00100000>;
261 };
262
263 chosen {
264 stdin = "serial0";
265 stdout = "serial0";
266 };
267};
| 93 };
94
95 SOC: soc88f6281@f1000000 {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 compatible = "simple-bus";
99 ranges = <0x0 0xf1000000 0x00100000>;
100 bus-frequency = <0>;
101
102 PIC: pic@20200 {
103 interrupt-controller;
104 #address-cells = <0>;
105 #interrupt-cells = <1>;
106 reg = <0x20200 0x3c>;
107 compatible = "mrvl,pic";
108 };
109
110 timer@20300 {
111 compatible = "mrvl,timer";
112 reg = <0x20300 0x30>;
113 interrupts = <1>;
114 interrupt-parent = <&PIC>;
115 mrvl,has-wdt;
116 };
117
118 MPP: mpp@10000 {
119 #pin-cells = <2>;
120 compatible = "mrvl,mpp";
121 reg = <0x10000 0x34>;
122 pin-count = <50>;
123 pin-map = <
124 0 1 /* MPP[0]: NF_IO[2] */
125 1 1 /* MPP[1]: NF_IO[3] */
126 2 1 /* MPP[2]: NF_IO[4] */
127 3 1 /* MPP[3]: NF_IO[5] */
128 4 1 /* MPP[4]: NF_IO[6] */
129 5 1 /* MPP[5]: NF_IO[7] */
130 6 1 /* MPP[6]: SYSRST_OUTn */
131 8 2 /* MPP[8]: UA0_RTS */
132 9 2 /* MPP[9]: UA0_CTS */
133 10 3 /* MPP[10]: UA0_TXD */
134 11 3 /* MPP[11]: UA0_RXD */
135 12 1 /* MPP[12]: SD_CLK */
136 13 1 /* MPP[13]: SD_CMD */
137 14 1 /* MPP[14]: SD_D[0] */
138 15 1 /* MPP[15]: SD_D[1] */
139 16 1 /* MPP[16]: SD_D[2] */
140 17 1 /* MPP[17]: SD_D[3] */
141 18 1 /* MPP[18]: NF_IO[0] */
142 19 1 /* MPP[19]: NF_IO[1] */
143 29 1 >; /* MPP[29]: TSMP[9] */
144 };
145
146 GPIO: gpio@10100 {
147 #gpio-cells = <3>;
148 compatible = "mrvl,gpio";
149 reg = <0x10100 0x20>;
150 gpio-controller;
151 interrupts = <35 36 37 38 39 40 41>;
152 interrupt-parent = <&PIC>;
153 };
154
155 rtc@10300 {
156 compatible = "mrvl,rtc";
157 reg = <0x10300 0x08>;
158 };
159
160 twsi@11000 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "mrvl,twsi";
164 reg = <0x11000 0x20>;
165 interrupts = <43>;
166 interrupt-parent = <&PIC>;
167 };
168
169 enet0: ethernet@72000 {
170 #address-cells = <1>;
171 #size-cells = <1>;
172 model = "V2";
173 compatible = "mrvl,ge";
174 reg = <0x72000 0x2000>;
175 ranges = <0x0 0x72000 0x2000>;
176 local-mac-address = [ 00 00 00 00 00 00 ];
177 interrupts = <12 13 14 11 46>;
178 interrupt-parent = <&PIC>;
179 phy-handle = <&phy0>;
180
181 mdio@0 {
182 #address-cells = <1>;
183 #size-cells = <0>;
184 compatible = "mrvl,mdio";
185
186 phy0: ethernet-phy@0 {
187 reg = <0x0>;
188 };
189 };
190 };
191
192 serial0: serial@12000 {
193 compatible = "ns16550";
194 reg = <0x12000 0x20>;
195 reg-shift = <2>;
196 clock-frequency = <0>;
197 interrupts = <33>;
198 interrupt-parent = <&PIC>;
199 };
200
201 serial1: serial@12100 {
202 compatible = "ns16550";
203 reg = <0x12100 0x20>;
204 reg-shift = <2>;
205 clock-frequency = <0>;
206 interrupts = <34>;
207 interrupt-parent = <&PIC>;
208 };
209
210 crypto@30000 {
211 compatible = "mrvl,cesa";
212 reg = <0x30000 0x10000>;
213 interrupts = <22>;
214 interrupt-parent = <&PIC>;
215
216 sram-handle = <&SRAM>;
217 };
218
219 usb@50000 {
220 compatible = "mrvl,usb-ehci", "usb-ehci";
221 reg = <0x50000 0x1000>;
222 interrupts = <48 19>;
223 interrupt-parent = <&PIC>;
224 };
225
226 xor@60000 {
227 compatible = "mrvl,xor";
228 reg = <0x60000 0x1000>;
229 interrupts = <5 6 7 8>;
230 interrupt-parent = <&PIC>;
231 };
232 };
233
234 SRAM: sram@fd000000 {
235 compatible = "mrvl,cesa-sram";
236 reg = <0xfd000000 0x00100000>;
237 };
238
239 chosen {
240 stdin = "serial0";
241 stdout = "serial0";
242 };
243};
|