p3041ds.dts (227506) | p3041ds.dts (236024) |
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1/* 2 * P3041DS Device Tree Source 3 * 4 * Copyright 2010-2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ | 1/* 2 * P3041DS Device Tree Source 3 * 4 * Copyright 2010-2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ |
34/* $FreeBSD: head/sys/boot/fdt/dts/p3041ds.dts 227506 2011-11-14 18:51:39Z marcel $ */ | 34/* $FreeBSD: head/sys/boot/fdt/dts/p3041ds.dts 236024 2012-05-25 20:43:38Z raj $ */ |
35 | 35 |
36/dts-v1/; | 36/include/ "p3041si.dtsi" |
37 38/ { 39 model = "fsl,P3041DS"; 40 compatible = "fsl,P3041DS"; 41 #address-cells = <2>; 42 #size-cells = <2>; 43 interrupt-parent = <&mpic>; 44 45 aliases { | 37 38/ { 39 model = "fsl,P3041DS"; 40 compatible = "fsl,P3041DS"; 41 #address-cells = <2>; 42 #size-cells = <2>; 43 interrupt-parent = <&mpic>; 44 45 aliases { |
46 ccsr = &soc; | 46 phy_rgmii_0 = &phy_rgmii_0; 47 phy_rgmii_1 = &phy_rgmii_1; 48 phy_sgmii_1c = &phy_sgmii_1c; 49 phy_sgmii_1d = &phy_sgmii_1d; 50 phy_sgmii_1e = &phy_sgmii_1e; 51 phy_sgmii_1f = &phy_sgmii_1f; 52 phy_xgmii_1 = &phy_xgmii_1; 53 phy_xgmii_2 = &phy_xgmii_2; 54 emi1_rgmii = &hydra_mdio_rgmii; 55 emi1_sgmii = &hydra_mdio_sgmii; 56 emi2_xgmii = &hydra_mdio_xgmii; 57 }; |
47 | 58 |
48 serial0 = &serial0; 49 serial1 = &serial1; 50 serial2 = &serial2; 51 serial3 = &serial3; 52 pci0 = &pci0; 53 pci1 = &pci1; 54 pci2 = &pci2; 55 pci3 = &pci3; 56 usb0 = &usb0; 57 usb1 = &usb1; 58 dma0 = &dma0; 59 dma1 = &dma1; 60 sdhc = &sdhc; 61 msi0 = &msi0; 62 msi1 = &msi1; 63 msi2 = &msi2; | 59 memory { 60 device_type = "memory"; 61 reg = <0x00000000 0x00000000 0x00000000 0x80000000>; 62 }; |
64 | 63 |
65 crypto = &crypto; 66 sec_jr0 = &sec_jr0; 67 sec_jr1 = &sec_jr1; 68 sec_jr2 = &sec_jr2; 69 sec_jr3 = &sec_jr3; 70 rtic_a = &rtic_a; 71 rtic_b = &rtic_b; 72 rtic_c = &rtic_c; 73 rtic_d = &rtic_d; 74 sec_mon = &sec_mon; | 64 dcsr: dcsr@f00000000 { 65 ranges = <0x00000000 0xf 0x00000000 0x01008000>; |
75 }; 76 | 66 }; 67 |
77 cpus { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 81 cpu0: PowerPC,e500mc@0 { 82 device_type = "cpu"; 83 reg = <0>; 84 next-level-cache = <&L2_0>; 85 L2_0: l2-cache { 86 next-level-cache = <&cpc>; 87 }; | 68 bman-portals@ff4000000 { 69 bman-portal@0 { 70 cpu-handle = <&cpu0>; |
88 }; | 71 }; |
89 cpu1: PowerPC,e500mc@1 { 90 device_type = "cpu"; 91 reg = <1>; 92 next-level-cache = <&L2_1>; 93 L2_1: l2-cache { 94 next-level-cache = <&cpc>; 95 }; | 72 bman-portal@4000 { 73 cpu-handle = <&cpu1>; |
96 }; | 74 }; |
97 cpu2: PowerPC,e500mc@2 { 98 device_type = "cpu"; 99 reg = <2>; 100 next-level-cache = <&L2_2>; 101 L2_2: l2-cache { 102 next-level-cache = <&cpc>; 103 }; | 75 bman-portal@8000 { 76 cpu-handle = <&cpu2>; |
104 }; | 77 }; |
105 cpu3: PowerPC,e500mc@3 { 106 device_type = "cpu"; 107 reg = <3>; 108 next-level-cache = <&L2_3>; 109 L2_3: l2-cache { 110 next-level-cache = <&cpc>; 111 }; | 78 bman-portal@c000 { 79 cpu-handle = <&cpu3>; |
112 }; | 80 }; |
113 }; 114 115 memory { 116 device_type = "memory"; 117 }; 118 119 soc: soc@ffe000000 { 120 #address-cells = <1>; 121 #size-cells = <1>; 122 device_type = "soc"; 123 compatible = "simple-bus"; 124 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 125 reg = <0xf 0xfe000000 0 0x00001000>; 126 127 soc-sram-error { 128 compatible = "fsl,soc-sram-error"; 129 interrupts = <16 2 1 29>; | 81 bman-portal@10000 { |
130 }; | 82 }; |
131 132 corenet-law@0 { 133 compatible = "fsl,corenet-law"; 134 reg = <0x0 0x1000>; 135 fsl,num-laws = <32>; | 83 bman-portal@14000 { |
136 }; | 84 }; |
137 138 memory-controller@8000 { 139 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; 140 reg = <0x8000 0x1000>; 141 interrupts = <16 2 1 23>; | 85 bman-portal@18000 { |
142 }; | 86 }; |
143 144 cpc: l3-cache-controller@10000 { 145 compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache"; 146 reg = <0x10000 0x1000>; 147 interrupts = <16 2 1 27>; | 87 bman-portal@1c000 { |
148 }; | 88 }; |
149 150 corenet-cf@18000 { 151 compatible = "fsl,corenet-cf"; 152 reg = <0x18000 0x1000>; 153 interrupts = <16 2 1 31>; 154 fsl,ccf-num-csdids = <32>; 155 fsl,ccf-num-snoopids = <32>; | 89 bman-portal@20000 { |
156 }; | 90 }; |
157 158 iommu@20000 { 159 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 160 reg = <0x20000 0x4000>; 161 interrupts = < 162 24 2 0 0 163 16 2 1 30>; | 91 bman-portal@24000 { |
164 }; 165 | 92 }; 93 |
166 mpic: pic@40000 { 167 clock-frequency = <0>; 168 interrupt-controller; 169 #address-cells = <0>; 170 #interrupt-cells = <4>; 171 reg = <0x40000 0x40000>; 172 compatible = "fsl,mpic", "chrp,open-pic"; 173 device_type = "open-pic"; | 94 buffer-pool@0 { 95 compatible = "fsl,p3041-bpool", "fsl,bpool"; 96 fsl,bpid = <0>; 97 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>; |
174 }; | 98 }; |
99 }; |
|
175 | 100 |
176 msi0: msi@41600 { 177 compatible = "fsl,mpic-msi"; 178 reg = <0x41600 0x200>; 179 msi-available-ranges = <0 0x100>; 180 interrupts = < 181 0xe0 0 0 0 182 0xe1 0 0 0 183 0xe2 0 0 0 184 0xe3 0 0 0 185 0xe4 0 0 0 186 0xe5 0 0 0 187 0xe6 0 0 0 188 0xe7 0 0 0>; | 101 qman-portals@ff4200000 { 102 qportal0: qman-portal@0 { 103 cpu-handle = <&cpu0>; 104 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 105 &qpool4 &qpool5 &qpool6 106 &qpool7 &qpool8 &qpool9 107 &qpool10 &qpool11 &qpool12 108 &qpool13 &qpool14 &qpool15>; |
189 }; 190 | 109 }; 110 |
191 msi1: msi@41800 { 192 compatible = "fsl,mpic-msi"; 193 reg = <0x41800 0x200>; 194 msi-available-ranges = <0 0x100>; 195 interrupts = < 196 0xe8 0 0 0 197 0xe9 0 0 0 198 0xea 0 0 0 199 0xeb 0 0 0 200 0xec 0 0 0 201 0xed 0 0 0 202 0xee 0 0 0 203 0xef 0 0 0>; | 111 qportal1: qman-portal@4000 { 112 cpu-handle = <&cpu1>; 113 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 114 &qpool4 &qpool5 &qpool6 115 &qpool7 &qpool8 &qpool9 116 &qpool10 &qpool11 &qpool12 117 &qpool13 &qpool14 &qpool15>; |
204 }; 205 | 118 }; 119 |
206 msi2: msi@41a00 { 207 compatible = "fsl,mpic-msi"; 208 reg = <0x41a00 0x200>; 209 msi-available-ranges = <0 0x100>; 210 interrupts = < 211 0xf0 0 0 0 212 0xf1 0 0 0 213 0xf2 0 0 0 214 0xf3 0 0 0 215 0xf4 0 0 0 216 0xf5 0 0 0 217 0xf6 0 0 0 218 0xf7 0 0 0>; | 120 qportal2: qman-portal@8000 { 121 cpu-handle = <&cpu2>; 122 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 123 &qpool4 &qpool5 &qpool6 124 &qpool7 &qpool8 &qpool9 125 &qpool10 &qpool11 &qpool12 126 &qpool13 &qpool14 &qpool15>; |
219 }; 220 | 127 }; 128 |
221 guts: global-utilities@e0000 { 222 compatible = "fsl,qoriq-device-config-1.0"; 223 reg = <0xe0000 0xe00>; 224 fsl,has-rstcr; 225 #sleep-cells = <1>; 226 fsl,liodn-bits = <12>; | 129 qportal3: qman-portal@c000 { 130 cpu-handle = <&cpu3>; 131 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 132 &qpool4 &qpool5 &qpool6 133 &qpool7 &qpool8 &qpool9 134 &qpool10 &qpool11 &qpool12 135 &qpool13 &qpool14 &qpool15>; |
227 }; 228 | 136 }; 137 |
229 pins: global-utilities@e0e00 { 230 compatible = "fsl,qoriq-pin-control-1.0"; 231 reg = <0xe0e00 0x200>; 232 #sleep-cells = <2>; | 138 qportal4: qman-portal@10000 { 139 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 140 &qpool4 &qpool5 &qpool6 141 &qpool7 &qpool8 &qpool9 142 &qpool10 &qpool11 &qpool12 143 &qpool13 &qpool14 &qpool15>; |
233 }; 234 | 144 }; 145 |
235 clockgen: global-utilities@e1000 { 236 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0"; 237 reg = <0xe1000 0x1000>; 238 clock-frequency = <0>; | 146 qportal5: qman-portal@14000 { 147 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 148 &qpool4 &qpool5 &qpool6 149 &qpool7 &qpool8 &qpool9 150 &qpool10 &qpool11 &qpool12 151 &qpool13 &qpool14 &qpool15>; |
239 }; 240 | 152 }; 153 |
241 rcpm: global-utilities@e2000 { 242 compatible = "fsl,qoriq-rcpm-1.0"; 243 reg = <0xe2000 0x1000>; 244 #sleep-cells = <1>; | 154 qportal6: qman-portal@18000 { 155 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 156 &qpool4 &qpool5 &qpool6 157 &qpool7 &qpool8 &qpool9 158 &qpool10 &qpool11 &qpool12 159 &qpool13 &qpool14 &qpool15>; |
245 }; 246 | 160 }; 161 |
247 sfp: sfp@e8000 { 248 compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0"; 249 reg = <0xe8000 0x1000>; | 162 qportal7: qman-portal@1c000 { 163 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 164 &qpool4 &qpool5 &qpool6 165 &qpool7 &qpool8 &qpool9 166 &qpool10 &qpool11 &qpool12 167 &qpool13 &qpool14 &qpool15>; |
250 }; 251 | 168 }; 169 |
252 serdes: serdes@ea000 { 253 compatible = "fsl,p3041-serdes"; 254 reg = <0xea000 0x1000>; | 170 qportal8: qman-portal@20000 { 171 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 172 &qpool4 &qpool5 &qpool6 173 &qpool7 &qpool8 &qpool9 174 &qpool10 &qpool11 &qpool12 175 &qpool13 &qpool14 &qpool15>; |
255 }; 256 | 176 }; 177 |
257 dma0: dma@100300 { 258 #address-cells = <1>; 259 #size-cells = <1>; 260 compatible = "fsl,p3041-dma", "fsl,eloplus-dma"; 261 reg = <0x100300 0x4>; 262 ranges = <0x0 0x100100 0x200>; 263 cell-index = <0>; 264 dma-channel@0 { 265 compatible = "fsl,p3041-dma-channel", 266 "fsl,eloplus-dma-channel"; 267 reg = <0x0 0x80>; 268 cell-index = <0>; 269 interrupts = <28 2 0 0>; 270 }; 271 dma-channel@80 { 272 compatible = "fsl,p3041-dma-channel", 273 "fsl,eloplus-dma-channel"; 274 reg = <0x80 0x80>; 275 cell-index = <1>; 276 interrupts = <29 2 0 0>; 277 }; 278 dma-channel@100 { 279 compatible = "fsl,p3041-dma-channel", 280 "fsl,eloplus-dma-channel"; 281 reg = <0x100 0x80>; 282 cell-index = <2>; 283 interrupts = <30 2 0 0>; 284 }; 285 dma-channel@180 { 286 compatible = "fsl,p3041-dma-channel", 287 "fsl,eloplus-dma-channel"; 288 reg = <0x180 0x80>; 289 cell-index = <3>; 290 interrupts = <31 2 0 0>; 291 }; | 178 qportal9: qman-portal@24000 { 179 fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3 180 &qpool4 &qpool5 &qpool6 181 &qpool7 &qpool8 &qpool9 182 &qpool10 &qpool11 &qpool12 183 &qpool13 &qpool14 &qpool15>; |
292 }; | 184 }; |
185 }; |
|
293 | 186 |
294 dma1: dma@101300 { 295 #address-cells = <1>; 296 #size-cells = <1>; 297 compatible = "fsl,p3041-dma", "fsl,eloplus-dma"; 298 reg = <0x101300 0x4>; 299 ranges = <0x0 0x101100 0x200>; 300 cell-index = <1>; 301 dma-channel@0 { 302 compatible = "fsl,p3041-dma-channel", 303 "fsl,eloplus-dma-channel"; 304 reg = <0x0 0x80>; 305 cell-index = <0>; 306 interrupts = <32 2 0 0>; 307 }; 308 dma-channel@80 { 309 compatible = "fsl,p3041-dma-channel", 310 "fsl,eloplus-dma-channel"; 311 reg = <0x80 0x80>; 312 cell-index = <1>; 313 interrupts = <33 2 0 0>; 314 }; 315 dma-channel@100 { 316 compatible = "fsl,p3041-dma-channel", 317 "fsl,eloplus-dma-channel"; 318 reg = <0x100 0x80>; 319 cell-index = <2>; 320 interrupts = <34 2 0 0>; 321 }; 322 dma-channel@180 { 323 compatible = "fsl,p3041-dma-channel", 324 "fsl,eloplus-dma-channel"; 325 reg = <0x180 0x80>; 326 cell-index = <3>; 327 interrupts = <35 2 0 0>; 328 }; 329 }; 330 | 187 soc: soc@ffe000000 { |
331 spi@110000 { | 188 spi@110000 { |
332 #address-cells = <1>; 333 #size-cells = <0>; 334 compatible = "fsl,p3041-espi", "fsl,mpc8536-espi"; 335 reg = <0x110000 0x1000>; 336 interrupts = <53 0x2 0 0>; 337 fsl,espi-num-chipselects = <4>; 338 | |
339 flash@0 { 340 #address-cells = <1>; 341 #size-cells = <1>; 342 compatible = "spansion,s25sl12801"; 343 reg = <0>; | 189 flash@0 { 190 #address-cells = <1>; 191 #size-cells = <1>; 192 compatible = "spansion,s25sl12801"; 193 reg = <0>; |
344 spi-max-frequency = <40000000>; /* input clock */ | 194 spi-max-frequency = <35000000>; /* input clock */ |
345 partition@u-boot { 346 label = "u-boot"; 347 reg = <0x00000000 0x00100000>; 348 read-only; 349 }; 350 partition@kernel { 351 label = "kernel"; 352 reg = <0x00100000 0x00500000>; --- 6 unchanged lines hidden (view full) --- 359 }; 360 partition@fs { 361 label = "file system"; 362 reg = <0x00700000 0x00900000>; 363 }; 364 }; 365 }; 366 | 195 partition@u-boot { 196 label = "u-boot"; 197 reg = <0x00000000 0x00100000>; 198 read-only; 199 }; 200 partition@kernel { 201 label = "kernel"; 202 reg = <0x00100000 0x00500000>; --- 6 unchanged lines hidden (view full) --- 209 }; 210 partition@fs { 211 label = "file system"; 212 reg = <0x00700000 0x00900000>; 213 }; 214 }; 215 }; 216 |
367 sdhc: sdhc@114000 { 368 compatible = "fsl,p3041-esdhc", "fsl,esdhc"; 369 reg = <0x114000 0x1000>; 370 interrupts = <48 2 0 0>; 371 sdhci,auto-cmd12; 372 clock-frequency = <0>; 373 }; 374 375 i2c@118000 { 376 #address-cells = <1>; 377 #size-cells = <0>; 378 cell-index = <0>; 379 compatible = "fsl-i2c"; 380 reg = <0x118000 0x100>; 381 interrupts = <38 2 0 0>; 382 dfsrr; 383 }; 384 | |
385 i2c@118100 { | 217 i2c@118100 { |
386 #address-cells = <1>; 387 #size-cells = <0>; 388 cell-index = <1>; 389 compatible = "fsl-i2c"; 390 reg = <0x118100 0x100>; 391 interrupts = <38 2 0 0>; 392 dfsrr; | |
393 eeprom@51 { 394 compatible = "at24,24c256"; 395 reg = <0x51>; 396 }; 397 eeprom@52 { 398 compatible = "at24,24c256"; 399 reg = <0x52>; 400 }; 401 }; 402 | 218 eeprom@51 { 219 compatible = "at24,24c256"; 220 reg = <0x51>; 221 }; 222 eeprom@52 { 223 compatible = "at24,24c256"; 224 reg = <0x52>; 225 }; 226 }; 227 |
403 i2c@119000 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 cell-index = <2>; 407 compatible = "fsl-i2c"; 408 reg = <0x119000 0x100>; 409 interrupts = <39 2 0 0>; 410 dfsrr; 411 }; 412 | |
413 i2c@119100 { | 228 i2c@119100 { |
414 #address-cells = <1>; 415 #size-cells = <0>; 416 cell-index = <3>; 417 compatible = "fsl-i2c"; 418 reg = <0x119100 0x100>; 419 interrupts = <39 2 0 0>; 420 dfsrr; | |
421 rtc@68 { 422 compatible = "dallas,ds3232"; 423 reg = <0x68>; 424 interrupts = <0x1 0x1 0 0>; 425 }; 426 }; 427 | 229 rtc@68 { 230 compatible = "dallas,ds3232"; 231 reg = <0x68>; 232 interrupts = <0x1 0x1 0 0>; 233 }; 234 }; 235 |
428 serial0: serial@11c500 { 429 cell-index = <0>; 430 device_type = "serial"; 431 compatible = "ns16550"; 432 reg = <0x11c500 0x100>; 433 clock-frequency = <0>; 434 interrupts = <36 2 0 0>; | 236 pme: pme@316000 { 237 /* Commented out, use default allocation */ 238 /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */ 239 /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */ |
435 }; 436 | 240 }; 241 |
437 serial1: serial@11c600 { 438 cell-index = <1>; 439 device_type = "serial"; 440 compatible = "ns16550"; 441 reg = <0x11c600 0x100>; 442 clock-frequency = <0>; 443 interrupts = <36 2 0 0>; | 242 qman: qman@318000 { 243 /* Commented out, use default allocation */ 244 /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */ 245 /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */ |
444 }; 445 | 246 }; 247 |
446 serial2: serial@11d500 { 447 cell-index = <2>; 448 device_type = "serial"; 449 compatible = "ns16550"; 450 reg = <0x11d500 0x100>; 451 clock-frequency = <0>; 452 interrupts = <37 2 0 0>; | 248 bman: bman@31a000 { 249 /* Same as fsl,qman-*, use default allocation */ 250 /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */ |
453 }; 454 | 251 }; 252 |
455 serial3: serial@11d600 { 456 cell-index = <3>; 457 device_type = "serial"; 458 compatible = "ns16550"; 459 reg = <0x11d600 0x100>; 460 clock-frequency = <0>; 461 interrupts = <37 2 0 0>; 462 }; | 253 fman0: fman@400000 { 254 enet0: ethernet@e0000 { 255 tbi-handle = <&tbi0>; 256 phy-handle = <&phy_rgmii_0>; 257 phy-connection-type = "rgmii"; 258 }; |
463 | 259 |
464 gpio0: gpio@130000 { 465 compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio"; 466 reg = <0x130000 0x1000>; 467 interrupts = <55 2 0 0>; 468 #gpio-cells = <2>; 469 gpio-controller; 470 }; | 260 mdio0: mdio@e1120 { 261 tbi0: tbi-phy@8 { 262 reg = <0x8>; 263 device_type = "tbi-phy"; 264 }; |
471 | 265 |
472 usb0: usb@210000 { 473 compatible = "fsl,p3041-usb2-mph", 474 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; 475 reg = <0x210000 0x1000>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 interrupts = <44 0x2 0 0>; 479 phy_type = "utmi"; 480 port0; 481 }; | 266 /* 267 * Virtual MDIO for the two on-board RGMII 268 * ports. The fsl,hydra-mdio-muxval property 269 * is already correct. 270 */ 271 hydra_mdio_rgmii: hydra-mdio-rgmii { 272 #address-cells = <1>; 273 #size-cells = <0>; 274 compatible = "fsl,hydra-mdio"; 275 fsl,mdio-handle = <&mdio0>; 276 fsl,hydra-mdio-muxval = <0x00>; 277 status = "disabled"; |
482 | 278 |
483 usb1: usb@211000 { 484 compatible = "fsl,p3041-usb2-dr", 485 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; 486 reg = <0x211000 0x1000>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 interrupts = <45 0x2 0 0>; 490 dr_mode = "host"; 491 phy_type = "utmi"; 492 }; | 279 phy_rgmii_0: ethernet-phy@0 { 280 reg = <0x0>; 281 }; 282 phy_rgmii_1: ethernet-phy@1 { 283 reg = <0x1>; 284 }; 285 }; |
493 | 286 |
494 sata@220000 { 495 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2"; 496 reg = <0x220000 0x1000>; 497 interrupts = <68 0x2 0 0>; 498 }; | 287 /* 288 * Virtual MDIO for the four-port SGMII card. 289 * The fsl,hydra-mdio-muxval property will be 290 * fixed-up by U-Boot based on the slot that 291 * the SGMII card is in. 292 * 293 * Note: we do not support DTSEC5 connected to 294 * SGMII, so this is the only SGMII node. 295 */ 296 hydra_mdio_sgmii: hydra-mdio-sgmii { 297 #address-cells = <1>; 298 #size-cells = <0>; 299 compatible = "fsl,hydra-mdio"; 300 fsl,mdio-handle = <&mdio0>; 301 fsl,hydra-mdio-muxval = <0x00>; 302 status = "disabled"; |
499 | 303 |
500 sata@221000 { 501 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2"; 502 reg = <0x221000 0x1000>; 503 interrupts = <69 0x2 0 0>; 504 }; | 304 phy_sgmii_1c: ethernet-phy@1c { 305 reg = <0x1c>; 306 }; 307 phy_sgmii_1d: ethernet-phy@1d { 308 reg = <0x1d>; 309 }; 310 phy_sgmii_1e: ethernet-phy@1e { 311 reg = <0x1e>; 312 }; 313 phy_sgmii_1f: ethernet-phy@1f { 314 reg = <0x1f>; 315 }; 316 }; 317 }; |
505 | 318 |
506 crypto: crypto@300000 { 507 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0"; 508 #address-cells = <1>; 509 #size-cells = <1>; 510 reg = <0x300000 0x10000>; 511 ranges = <0 0x300000 0x10000>; 512 interrupts = <92 2 0 0>; | 319 enet1: ethernet@e2000 { 320 tbi-handle = <&tbi1>; 321 phy-handle = <&phy_sgmii_1d>; 322 phy-connection-type = "sgmii"; 323 }; |
513 | 324 |
514 sec_jr0: jr@1000 { 515 compatible = "fsl,sec-v4.2-job-ring", 516 "fsl,sec-v4.0-job-ring"; 517 reg = <0x1000 0x1000>; 518 interrupts = <88 2 0 0>; | 325 mdio@e3120 { 326 tbi1: tbi-phy@8 { 327 reg = <8>; 328 device_type = "tbi-phy"; 329 }; |
519 }; 520 | 330 }; 331 |
521 sec_jr1: jr@2000 { 522 compatible = "fsl,sec-v4.2-job-ring", 523 "fsl,sec-v4.0-job-ring"; 524 reg = <0x2000 0x1000>; 525 interrupts = <89 2 0 0>; | 332 enet2: ethernet@e4000 { 333 tbi-handle = <&tbi2>; 334 phy-handle = <&phy_sgmii_1e>; 335 phy-connection-type = "sgmii"; |
526 }; 527 | 336 }; 337 |
528 sec_jr2: jr@3000 { 529 compatible = "fsl,sec-v4.2-job-ring", 530 "fsl,sec-v4.0-job-ring"; 531 reg = <0x3000 0x1000>; 532 interrupts = <90 2 0 0>; | 338 mdio@e5120 { 339 tbi2: tbi-phy@8 { 340 reg = <8>; 341 device_type = "tbi-phy"; 342 }; |
533 }; 534 | 343 }; 344 |
535 sec_jr3: jr@4000 { 536 compatible = "fsl,sec-v4.2-job-ring", 537 "fsl,sec-v4.0-job-ring"; 538 reg = <0x4000 0x1000>; 539 interrupts = <91 2 0 0>; | 345 enet3: ethernet@e6000 { 346 tbi-handle = <&tbi3>; 347 phy-handle = <&phy_sgmii_1f>; 348 phy-connection-type = "sgmii"; |
540 }; 541 | 349 }; 350 |
542 rtic@6000 { 543 compatible = "fsl,sec-v4.2-rtic", 544 "fsl,sec-v4.0-rtic"; | 351 mdio@e7120 { |
545 #address-cells = <1>; | 352 #address-cells = <1>; |
546 #size-cells = <1>; 547 reg = <0x6000 0x100>; 548 ranges = <0x0 0x6100 0xe00>; | 353 #size-cells = <0>; 354 compatible = "fsl,fman-tbi"; 355 reg = <0xe7120 0xee0>; 356 interrupts = <100 1 0 0>; |
549 | 357 |
550 rtic_a: rtic-a@0 { 551 compatible = "fsl,sec-v4.2-rtic-memory", 552 "fsl,sec-v4.0-rtic-memory"; 553 reg = <0x00 0x20 0x100 0x80>; | 358 tbi3: tbi-phy@8 { 359 reg = <8>; 360 device_type = "tbi-phy"; |
554 }; | 361 }; |
362 }; |
|
555 | 363 |
556 rtic_b: rtic-b@20 { 557 compatible = "fsl,sec-v4.2-rtic-memory", 558 "fsl,sec-v4.0-rtic-memory"; 559 reg = <0x20 0x20 0x200 0x80>; | 364 enet4: ethernet@e8000 { 365 tbi-handle = <&tbi4>; 366 phy-handle = <&phy_rgmii_1>; 367 phy-connection-type = "rgmii"; 368 }; 369 370 mdio@e9120 { 371 tbi4: tbi-phy@8 { 372 reg = <8>; 373 device_type = "tbi-phy"; |
560 }; | 374 }; |
375 }; |
|
561 | 376 |
562 rtic_c: rtic-c@40 { 563 compatible = "fsl,sec-v4.2-rtic-memory", 564 "fsl,sec-v4.0-rtic-memory"; 565 reg = <0x40 0x20 0x300 0x80>; | 377 enet5: ethernet@f0000 { 378 /* 379 * phy-handle will be updated by U-Boot to 380 * reflect the actual slot the XAUI card is in. 381 */ 382 phy-handle = <&phy_xgmii_1>; 383 phy-connection-type = "xgmii"; 384 }; 385 386 /* 387 * We only support one XAUI card, so the MDIO muxing 388 * is set by U-Boot, and Linux never touches it. 389 * Therefore, we don't need a virtual MDIO node. 390 * However, the phy address depends on the slot, so 391 * only one of the ethernet-phy nodes below will be 392 * used. 393 */ 394 hydra_mdio_xgmii: mdio@f1000 { 395 status = "disabled"; 396 397 /* XAUI card in slot 1 */ 398 phy_xgmii_1: ethernet-phy@4 { 399 reg = <0x4>; |
566 }; 567 | 400 }; 401 |
568 rtic_d: rtic-d@60 { 569 compatible = "fsl,sec-v4.2-rtic-memory", 570 "fsl,sec-v4.0-rtic-memory"; 571 reg = <0x60 0x20 0x500 0x80>; | 402 /* XAUI card in slot 2 */ 403 phy_xgmii_2: ethernet-phy@0 { 404 reg = <0x0>; |
572 }; 573 }; 574 }; | 405 }; 406 }; 407 }; |
408 }; |
|
575 | 409 |
576 sec_mon: sec_mon@314000 { 577 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon"; 578 reg = <0x314000 0x1000>; 579 interrupts = <93 2 0 0>; | 410 rapidio@ffe0c0000 { 411 reg = <0xf 0xfe0c0000 0 0x11000>; 412 413 port1 { 414 ranges = <0 0 0xc 0x20000000 0 0x10000000>; |
580 }; | 415 }; |
416 port2 { 417 ranges = <0 0 0xc 0x30000000 0 0x10000000>; 418 }; |
|
581 }; 582 583 localbus@ffe124000 { | 419 }; 420 421 localbus@ffe124000 { |
584 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus"; | |
585 reg = <0xf 0xfe124000 0 0x1000>; | 422 reg = <0xf 0xfe124000 0 0x1000>; |
586 interrupts = <25 2 0 0>; 587 #address-cells = <2>; 588 #size-cells = <1>; | 423 ranges = <0 0 0xf 0xb8000000 0x04000000>; |
589 | 424 |
590 ranges = <0 0 0xf 0xe8000000 0x08000000 591 3 0 0xf 0xffdf0000 0x00008000>; 592 | |
593 flash@0,0 { 594 compatible = "cfi-flash"; | 425 flash@0,0 { 426 compatible = "cfi-flash"; |
595 reg = <0 0 0x08000000>; | 427 /* 428 * Map 64Mb of 128MB NOR flash memory. Since highest 429 * line of address of NOR flash memory are set by 430 * FPGA, memory are divided into two pages equal to 431 * 64MB. One of the pages can be accessed at once. 432 */ 433 reg = <0 0 0x04000000>; |
596 bank-width = <2>; 597 device-width = <2>; 598 }; 599 | 434 bank-width = <2>; 435 device-width = <2>; 436 }; 437 |
438 nand@2,0 { 439 #address-cells = <1>; 440 #size-cells = <1>; 441 compatible = "fsl,elbc-fcm-nand"; 442 reg = <0x2 0x0 0x40000>; 443 444 partition@0 { 445 label = "NAND U-Boot Image"; 446 reg = <0x0 0x02000000>; 447 read-only; 448 }; 449 450 partition@2000000 { 451 label = "NAND Root File System"; 452 reg = <0x02000000 0x10000000>; 453 }; 454 455 partition@12000000 { 456 label = "NAND Compressed RFS Image"; 457 reg = <0x12000000 0x08000000>; 458 }; 459 460 partition@1a000000 { 461 label = "NAND Linux Kernel Image"; 462 reg = <0x1a000000 0x04000000>; 463 }; 464 465 partition@1e000000 { 466 label = "NAND DTB Image"; 467 reg = <0x1e000000 0x01000000>; 468 }; 469 470 partition@1f000000 { 471 label = "NAND Writable User area"; 472 reg = <0x1f000000 0x21000000>; 473 }; 474 }; 475 |
|
600 board-control@3,0 { | 476 board-control@3,0 { |
601 compatible = "fsl,p3041ds-pixis"; 602 reg = <3 0 0x20>; | 477 compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis"; 478 reg = <3 0 0x30>; |
603 }; 604 }; 605 606 pci0: pcie@ffe200000 { | 479 }; 480 }; 481 482 pci0: pcie@ffe200000 { |
607 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; 608 device_type = "pci"; 609 #size-cells = <2>; 610 #address-cells = <3>; | |
611 reg = <0xf 0xfe200000 0 0x1000>; | 483 reg = <0xf 0xfe200000 0 0x1000>; |
612 bus-range = <0x0 0xff>; 613 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 614 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 615 clock-frequency = <0x1fca055>; 616 fsl,msi = <&msi0>; 617 interrupts = <16 2 1 15>; | 484 ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000 485 0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>; |
618 pcie@0 { | 486 pcie@0 { |
619 reg = <0 0 0 0 0>; 620 #interrupt-cells = <1>; 621 #size-cells = <2>; 622 #address-cells = <3>; 623 device_type = "pci"; 624 interrupts = <16 2 1 15>; 625 interrupt-map-mask = <0xf800 0 0 7>; 626 interrupt-map = < 627 /* IDSEL 0x0 */ 628 0000 0 0 1 &mpic 40 1 0 0 629 0000 0 0 2 &mpic 1 1 0 0 630 0000 0 0 3 &mpic 2 1 0 0 631 0000 0 0 4 &mpic 3 1 0 0 632 >; 633 ranges = <0x02000000 0 0xe0000000 634 0x02000000 0 0xe0000000 635 0 0x20000000 | 487 ranges = <0x02000000 0 0x80000000 488 0x02000000 0 0x80000000 489 0 0x10000000 |
636 637 0x01000000 0 0x00000000 | 490 491 0x01000000 0 0x00000000 |
638 0x01000000 0 0x00000000 | 492 0x01000000 0 0xff000000 |
639 0 0x00010000>; 640 }; 641 }; 642 643 pci1: pcie@ffe201000 { | 493 0 0x00010000>; 494 }; 495 }; 496 497 pci1: pcie@ffe201000 { |
644 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; 645 device_type = "pci"; 646 #size-cells = <2>; 647 #address-cells = <3>; | |
648 reg = <0xf 0xfe201000 0 0x1000>; | 498 reg = <0xf 0xfe201000 0 0x1000>; |
649 bus-range = <0 0xff>; 650 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 651 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 652 clock-frequency = <0x1fca055>; 653 fsl,msi = <&msi1>; 654 interrupts = <16 2 1 14>; | 499 ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000 500 0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>; |
655 pcie@0 { | 501 pcie@0 { |
656 reg = <0 0 0 0 0>; 657 #interrupt-cells = <1>; 658 #size-cells = <2>; 659 #address-cells = <3>; 660 device_type = "pci"; 661 interrupts = <16 2 1 14>; 662 interrupt-map-mask = <0xf800 0 0 7>; 663 interrupt-map = < 664 /* IDSEL 0x0 */ 665 0000 0 0 1 &mpic 41 1 0 0 666 0000 0 0 2 &mpic 5 1 0 0 667 0000 0 0 3 &mpic 6 1 0 0 668 0000 0 0 4 &mpic 7 1 0 0 669 >; 670 ranges = <0x02000000 0 0xe0000000 671 0x02000000 0 0xe0000000 672 0 0x20000000 | 502 ranges = <0x02000000 0 0x90000000 503 0x02000000 0 0x90000000 504 0 0x10000000 |
673 674 0x01000000 0 0x00000000 | 505 506 0x01000000 0 0x00000000 |
675 0x01000000 0 0x00000000 | 507 0x01000000 0 0xff010000 |
676 0 0x00010000>; 677 }; 678 }; 679 680 pci2: pcie@ffe202000 { | 508 0 0x00010000>; 509 }; 510 }; 511 512 pci2: pcie@ffe202000 { |
681 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; 682 device_type = "pci"; 683 #size-cells = <2>; 684 #address-cells = <3>; | |
685 reg = <0xf 0xfe202000 0 0x1000>; | 513 reg = <0xf 0xfe202000 0 0x1000>; |
686 bus-range = <0x0 0xff>; 687 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 688 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 689 clock-frequency = <0x1fca055>; 690 fsl,msi = <&msi2>; 691 interrupts = <16 2 1 13>; | 514 ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000 515 0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>; |
692 pcie@0 { | 516 pcie@0 { |
693 reg = <0 0 0 0 0>; 694 #interrupt-cells = <1>; 695 #size-cells = <2>; 696 #address-cells = <3>; 697 device_type = "pci"; 698 interrupts = <16 2 1 13>; 699 interrupt-map-mask = <0xf800 0 0 7>; 700 interrupt-map = < 701 /* IDSEL 0x0 */ 702 0000 0 0 1 &mpic 42 1 0 0 703 0000 0 0 2 &mpic 9 1 0 0 704 0000 0 0 3 &mpic 10 1 0 0 705 0000 0 0 4 &mpic 11 1 0 0 706 >; 707 ranges = <0x02000000 0 0xe0000000 708 0x02000000 0 0xe0000000 709 0 0x20000000 | 517 ranges = <0x02000000 0 0xa0000000 518 0x02000000 0 0xa0000000 519 0 0x10000000 |
710 711 0x01000000 0 0x00000000 | 520 521 0x01000000 0 0x00000000 |
712 0x01000000 0 0x00000000 | 522 0x01000000 0 0xff020000 |
713 0 0x00010000>; 714 }; 715 }; 716 717 pci3: pcie@ffe203000 { | 523 0 0x00010000>; 524 }; 525 }; 526 527 pci3: pcie@ffe203000 { |
718 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; 719 device_type = "pci"; 720 #size-cells = <2>; 721 #address-cells = <3>; | |
722 reg = <0xf 0xfe203000 0 0x1000>; | 528 reg = <0xf 0xfe203000 0 0x1000>; |
723 bus-range = <0x0 0xff>; 724 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 725 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 726 clock-frequency = <0x1fca055>; 727 fsl,msi = <&msi2>; 728 interrupts = <16 2 1 12>; | 529 ranges = <0x02000000 0 0xb0000000 0x0 0xb0000000 0 0x08000000 530 0x01000000 0 0x00000000 0x0 0xff030000 0 0x00010000>; |
729 pcie@0 { | 531 pcie@0 { |
730 reg = <0 0 0 0 0>; 731 #interrupt-cells = <1>; 732 #size-cells = <2>; 733 #address-cells = <3>; 734 device_type = "pci"; 735 interrupts = <16 2 1 12>; 736 interrupt-map-mask = <0xf800 0 0 7>; 737 interrupt-map = < 738 /* IDSEL 0x0 */ 739 0000 0 0 1 &mpic 43 1 0 0 740 0000 0 0 2 &mpic 0 1 0 0 741 0000 0 0 3 &mpic 4 1 0 0 742 0000 0 0 4 &mpic 8 1 0 0 743 >; 744 ranges = <0x02000000 0 0xe0000000 745 0x02000000 0 0xe0000000 746 0 0x20000000 | 532 ranges = <0x02000000 0 0xb0000000 533 0x02000000 0 0xb0000000 534 0 0x08000000 |
747 748 0x01000000 0 0x00000000 | 535 536 0x01000000 0 0x00000000 |
749 0x01000000 0 0x00000000 | 537 0x01000000 0 0xff030000 |
750 0 0x00010000>; 751 }; 752 }; | 538 0 0x00010000>; 539 }; 540 }; |
541 542 fsl,dpaa { 543 compatible = "fsl,p3041-dpaa", "fsl,dpaa"; 544 545 ethernet@0 { 546 compatible = "fsl,p3041-dpa-ethernet", "fsl,dpa-ethernet"; 547 fsl,qman-channel = <&qpool1>; 548 fsl,fman-mac = <&enet0>; 549 status="okay"; 550 }; 551 ethernet@1 { 552 compatible = "fsl,p3041-dpa-ethernet", "fsl,dpa-ethernet"; 553 fsl,qman-channel = <&qpool1>; 554 fsl,fman-mac = <&enet1>; 555 status = "disabled"; 556 }; 557 ethernet@2 { 558 compatible = "fsl,p3041-dpa-ethernet", "fsl,dpa-ethernet"; 559 fsl,qman-channel = <&qpool1>; 560 fsl,fman-mac = <&enet2>; 561 status = "disabled"; 562 }; 563 ethernet@3 { 564 compatible = "fsl,p3041-dpa-ethernet", "fsl,dpa-ethernet"; 565 fsl,qman-channel = <&qpool1>; 566 fsl,fman-mac = <&enet3>; 567 status = "disabled"; 568 }; 569 ethernet@4 { 570 compatible = "fsl,p3041-dpa-ethernet", "fsl,dpa-ethernet"; 571 fsl,qman-channel = <&qpool1>; 572 fsl,fman-mac = <&enet4>; 573 status = "okay"; 574 }; 575 ethernet@5 { 576 compatible = "fsl,p3041-dpa-ethernet", "fsl,dpa-ethernet"; 577 fsl,qman-channel = <&qpool1>; 578 fsl,fman-mac = <&enet5>; 579 status = "disabled"; 580 }; 581 }; 582 583 chosen { 584 stdin = "serial0"; 585 stdout = "serial0"; 586 }; |
|
753}; | 587}; |