| at91rm9200_lowlevel.c (157873) | at91rm9200_lowlevel.c (157924) |
|---|---|
| 1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 10 unchanged lines hidden (view full) --- 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 * This software is derived from software provide by Kwikbyte who specifically 25 * disclaimed copyright on the code. 26 * | 1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 10 unchanged lines hidden (view full) --- 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 * This software is derived from software provide by Kwikbyte who specifically 25 * disclaimed copyright on the code. 26 * |
| 27 * $FreeBSD: head/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.c 157873 2006-04-19 17:16:49Z imp $ | 27 * $FreeBSD: head/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.c 157924 2006-04-21 07:29:14Z imp $ |
| 28 */ 29 30#include "at91rm9200.h" 31#include "at91rm9200_lowlevel.h" 32 33#define BAUD 115200 34#define AT91C_US_ASYNC_MODE (AT91C_US_USMODE_NORMAL | AT91C_US_NBSTOP_1_BIT | \ 35 AT91C_US_PAR_NONE | AT91C_US_CHRL_8_BITS | AT91C_US_CLKS_CLOCK) --- 52 unchanged lines hidden (view full) --- 88 value &= ~AT91C_PMC_CSS; 89 value |= AT91C_PMC_CSS_PLLA_CLK; 90 AT91C_BASE_PMC->PMC_MCKR = value; 91 92 // wait for update 93 while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) 94 continue; 95 | 28 */ 29 30#include "at91rm9200.h" 31#include "at91rm9200_lowlevel.h" 32 33#define BAUD 115200 34#define AT91C_US_ASYNC_MODE (AT91C_US_USMODE_NORMAL | AT91C_US_NBSTOP_1_BIT | \ 35 AT91C_US_PAR_NONE | AT91C_US_CHRL_8_BITS | AT91C_US_CLKS_CLOCK) --- 52 unchanged lines hidden (view full) --- 88 value &= ~AT91C_PMC_CSS; 89 value |= AT91C_PMC_CSS_PLLA_CLK; 90 AT91C_BASE_PMC->PMC_MCKR = value; 91 92 // wait for update 93 while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) 94 continue; 95 |
| 96#ifdef BOOT_KB9202 97 // setup flash access (allow ample margin) 98 // 9 wait states, 1 setup, 1 hold, 1 float for 8-bit device 99 ((AT91PS_SMC2)AT91C_BASE_SMC2)->SMC2_CSR[0] = 100 AT91C_SMC2_WSEN | 101 (9 & AT91C_SMC2_NWS) | 102 ((1 << 8) & AT91C_SMC2_TDF) | 103 AT91C_SMC2_DBW_8 | 104 ((1 << 24) & AT91C_SMC2_RWSETUP) | 105 ((1 << 29) & AT91C_SMC2_RWHOLD); 106#endif 107 |
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| 96 // setup SDRAM access 97 // EBI chip-select register (CS1 = SDRAM controller) 98 // 9 col, 13row, 4 bank, CAS2 99 // write recovery = 2 (Twr) 100 // row cycle = 5 (Trc) 101 // precharge delay = 2 (Trp) 102 // row to col delay 2 (Trcd) 103 // active to precharge = 4 (Tras) --- 51 unchanged lines hidden (view full) --- 155 AT91C_BASE_PIOC->PIO_ASR = 0xffff0000; 156 AT91C_BASE_PIOC->PIO_PDR = 0xffff0000; 157#endif 158 // Configure DBGU -use local routine optimized for space 159 AT91C_BASE_PIOA->PIO_ASR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; 160 AT91C_BASE_PIOA->PIO_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; 161 pUSART->US_IDR = (unsigned int) -1; 162 pUSART->US_CR = | 108 // setup SDRAM access 109 // EBI chip-select register (CS1 = SDRAM controller) 110 // 9 col, 13row, 4 bank, CAS2 111 // write recovery = 2 (Twr) 112 // row cycle = 5 (Trc) 113 // precharge delay = 2 (Trp) 114 // row to col delay 2 (Trcd) 115 // active to precharge = 4 (Tras) --- 51 unchanged lines hidden (view full) --- 167 AT91C_BASE_PIOC->PIO_ASR = 0xffff0000; 168 AT91C_BASE_PIOC->PIO_PDR = 0xffff0000; 169#endif 170 // Configure DBGU -use local routine optimized for space 171 AT91C_BASE_PIOA->PIO_ASR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; 172 AT91C_BASE_PIOA->PIO_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; 173 pUSART->US_IDR = (unsigned int) -1; 174 pUSART->US_CR = |
| 163 AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS; | 175 AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS; |
| 164 pUSART->US_BRGR = ((((AT91C_MASTER_CLOCK*10)/(BAUD*16))+5)/10); 165 pUSART->US_TTGR = 0; 166 pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; 167 pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; 168 pPDC->PDC_TNPR = 0; 169 pPDC->PDC_TNCR = 0; 170 171 pPDC->PDC_RNPR = 0; --- 15 unchanged lines hidden --- | 176 pUSART->US_BRGR = ((((AT91C_MASTER_CLOCK*10)/(BAUD*16))+5)/10); 177 pUSART->US_TTGR = 0; 178 pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; 179 pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; 180 pPDC->PDC_TNPR = 0; 181 pPDC->PDC_TNCR = 0; 182 183 pPDC->PDC_RNPR = 0; --- 15 unchanged lines hidden --- |