| ixp425_pci.c (172394) | ixp425_pci.c (186352) |
|---|---|
| 1/* $NetBSD: ixp425_pci.c,v 1.5 2006/04/10 03:36:03 simonb Exp $ */ 2 3/* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro@ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 20 unchanged lines hidden (view full) --- 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36#include <sys/cdefs.h> | 1/* $NetBSD: ixp425_pci.c,v 1.5 2006/04/10 03:36:03 simonb Exp $ */ 2 3/* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro@ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 20 unchanged lines hidden (view full) --- 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36#include <sys/cdefs.h> |
| 37__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/ixp425_pci.c 172394 2007-09-30 11:05:18Z marius $"); | 37__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/ixp425_pci.c 186352 2008-12-20 03:26:09Z sam $"); |
| 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/malloc.h> 42#define _ARM32_BUS_DMA_PRIVATE 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/module.h> --- 38 unchanged lines hidden (view full) --- 84static pcib_maxslots_t ixppcib_maxslots; 85static pcib_read_config_t ixppcib_read_config; 86static pcib_write_config_t ixppcib_write_config; 87static pcib_route_interrupt_t ixppcib_route_interrupt; 88 89static int 90ixppcib_probe(device_t dev) 91{ | 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/malloc.h> 42#define _ARM32_BUS_DMA_PRIVATE 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/module.h> --- 38 unchanged lines hidden (view full) --- 84static pcib_maxslots_t ixppcib_maxslots; 85static pcib_read_config_t ixppcib_read_config; 86static pcib_write_config_t ixppcib_write_config; 87static pcib_route_interrupt_t ixppcib_route_interrupt; 88 89static int 90ixppcib_probe(device_t dev) 91{ |
| 92 93 device_set_desc(dev, "IXP425 PCI Bus"); | 92 device_set_desc(dev, "IXP4XX PCI Bus"); |
| 94 return (0); 95} 96 97static void 98ixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg, 99 uint32_t data) 100{ 101 PCI_CSR_WRITE_4(sc, --- 23 unchanged lines hidden (view full) --- 125 126 rid = 0; 127 sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 128 IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE, 129 IXP425_PCI_MEM_SIZE, RF_ACTIVE); 130 if (sc->sc_mem == NULL) 131 panic("cannot allocate PCI MEM space"); 132 | 93 return (0); 94} 95 96static void 97ixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg, 98 uint32_t data) 99{ 100 PCI_CSR_WRITE_4(sc, --- 23 unchanged lines hidden (view full) --- 124 125 rid = 0; 126 sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 127 IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE, 128 IXP425_PCI_MEM_SIZE, RF_ACTIVE); 129 if (sc->sc_mem == NULL) 130 panic("cannot allocate PCI MEM space"); 131 |
| 133#define AHB_OFFSET 0x10000000UL 134 if (bus_dma_tag_create(NULL, 1, 0, AHB_OFFSET + 64 * 1024 * 1024, | 132 /* NB: PCI dma window is 64M so anything above must be bounced */ 133 if (bus_dma_tag_create(NULL, 1, 0, IXP425_AHB_OFFSET + 64 * 1024 * 1024, |
| 135 BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0, 136 NULL, NULL, &sc->sc_dmat)) 137 panic("couldn't create the PCI dma tag !"); 138 /* 139 * The PCI bus can only address 64MB. However, due to the way our 140 * implementation of busdma works, busdma can't tell if a device 141 * is a PCI device or not. So defaults to the PCI dma tag, which 142 * restrict the DMA'able memory to the first 64MB, and explicitely --- 5 unchanged lines hidden (view full) --- 148 */ 149 ixp425_io_bs_init(&sc->sc_pci_iot, sc); 150 ixp425_mem_bs_init(&sc->sc_pci_memt, sc); 151 152 sc->sc_dev = dev; 153 154 /* Initialize memory and i/o rmans. */ 155 sc->sc_io_rman.rm_type = RMAN_ARRAY; | 134 BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0, 135 NULL, NULL, &sc->sc_dmat)) 136 panic("couldn't create the PCI dma tag !"); 137 /* 138 * The PCI bus can only address 64MB. However, due to the way our 139 * implementation of busdma works, busdma can't tell if a device 140 * is a PCI device or not. So defaults to the PCI dma tag, which 141 * restrict the DMA'able memory to the first 64MB, and explicitely --- 5 unchanged lines hidden (view full) --- 147 */ 148 ixp425_io_bs_init(&sc->sc_pci_iot, sc); 149 ixp425_mem_bs_init(&sc->sc_pci_memt, sc); 150 151 sc->sc_dev = dev; 152 153 /* Initialize memory and i/o rmans. */ 154 sc->sc_io_rman.rm_type = RMAN_ARRAY; |
| 156 sc->sc_io_rman.rm_descr = "IXP425 PCI I/O Ports"; | 155 sc->sc_io_rman.rm_descr = "IXP4XX PCI I/O Ports"; |
| 157 if (rman_init(&sc->sc_io_rman) != 0 || 158 rman_manage_region(&sc->sc_io_rman, 0, 159 IXP425_PCI_IO_SIZE) != 0) { 160 panic("ixppcib_probe: failed to set up I/O rman"); 161 } 162 163 sc->sc_mem_rman.rm_type = RMAN_ARRAY; | 156 if (rman_init(&sc->sc_io_rman) != 0 || 157 rman_manage_region(&sc->sc_io_rman, 0, 158 IXP425_PCI_IO_SIZE) != 0) { 159 panic("ixppcib_probe: failed to set up I/O rman"); 160 } 161 162 sc->sc_mem_rman.rm_type = RMAN_ARRAY; |
| 164 sc->sc_mem_rman.rm_descr = "IXP425 PCI Memory"; | 163 sc->sc_mem_rman.rm_descr = "IXP4XX PCI Memory"; |
| 165 if (rman_init(&sc->sc_mem_rman) != 0 || 166 rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE, 167 IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) { 168 panic("ixppcib_probe: failed to set up memory rman"); 169 } 170 171 /* 172 * PCI->AHB address translation 173 * begin at the physical memory start + OFFSET 174 */ 175 PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, | 164 if (rman_init(&sc->sc_mem_rman) != 0 || 165 rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE, 166 IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) { 167 panic("ixppcib_probe: failed to set up memory rman"); 168 } 169 170 /* 171 * PCI->AHB address translation 172 * begin at the physical memory start + OFFSET 173 */ 174 PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, |
| 176 (AHB_OFFSET & 0xFF000000) + 177 ((AHB_OFFSET & 0xFF000000) >> 8) + 178 ((AHB_OFFSET & 0xFF000000) >> 16) + 179 ((AHB_OFFSET & 0xFF000000) >> 24) + | 175 (IXP425_AHB_OFFSET & 0xFF000000) + 176 ((IXP425_AHB_OFFSET & 0xFF000000) >> 8) + 177 ((IXP425_AHB_OFFSET & 0xFF000000) >> 16) + 178 ((IXP425_AHB_OFFSET & 0xFF000000) >> 24) + |
| 180 0x00010203); 181 182#define IXPPCIB_WRITE_CONF(sc, reg, val) \ 183 ixp425_pci_conf_reg_write(sc, reg, val) 184 /* Write Mapping registers PCI Configuration Registers */ 185 /* Base Address 0 - 3 */ | 179 0x00010203); 180 181#define IXPPCIB_WRITE_CONF(sc, reg, val) \ 182 ixp425_pci_conf_reg_write(sc, reg, val) 183 /* Write Mapping registers PCI Configuration Registers */ 184 /* Base Address 0 - 3 */ |
| 186 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, AHB_OFFSET + 0x00000000); 187 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, AHB_OFFSET + 0x01000000); 188 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, AHB_OFFSET + 0x02000000); 189 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, AHB_OFFSET + 0x03000000); | 185 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, IXP425_AHB_OFFSET + 0x00000000); 186 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, IXP425_AHB_OFFSET + 0x01000000); 187 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, IXP425_AHB_OFFSET + 0x02000000); 188 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, IXP425_AHB_OFFSET + 0x03000000); |
| 190 191 /* Base Address 4 */ 192 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff); 193 194 /* Base Address 5 */ 195 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000); 196 197 /* Assert some PCI errors */ --- 277 unchanged lines hidden --- | 189 190 /* Base Address 4 */ 191 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff); 192 193 /* Base Address 5 */ 194 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000); 195 196 /* Assert some PCI errors */ --- 277 unchanged lines hidden --- |