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zy7_slcr.c (266152) zy7_slcr.c (273645)
1/*-
2 * Copyright (c) 2013 Thomas Skibo
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
1/*-
2 * Copyright (c) 2013 Thomas Skibo
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/10/sys/arm/xilinx/zy7_slcr.c 266152 2014-05-15 16:11:06Z ian $
26 * $FreeBSD: stable/10/sys/arm/xilinx/zy7_slcr.c 273645 2014-10-25 20:34:10Z ian $
27 */
28
29/*
30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.
31 * In the future, maybe MIO control, clock control, etc. could go here.
32 *
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
34 * (v1.4) November 16, 2012. Xilinx doc UG585.
35 */
36
37#include <sys/cdefs.h>
27 */
28
29/*
30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.
31 * In the future, maybe MIO control, clock control, etc. could go here.
32 *
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
34 * (v1.4) November 16, 2012. Xilinx doc UG585.
35 */
36
37#include <sys/cdefs.h>
38__FBSDID("$FreeBSD: stable/10/sys/arm/xilinx/zy7_slcr.c 266152 2014-05-15 16:11:06Z ian $");
38__FBSDID("$FreeBSD: stable/10/sys/arm/xilinx/zy7_slcr.c 273645 2014-10-25 20:34:10Z ian $");
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/conf.h>
43#include <sys/kernel.h>
44#include <sys/module.h>
45#include <sys/lock.h>
46#include <sys/mutex.h>

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66
67static struct zy7_slcr_softc *zy7_slcr_softc_p;
68extern void (*zynq7_cpu_reset);
69
70#define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
71#define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
72#define ZSLCR_LOCK_INIT(sc) \
73 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/conf.h>
43#include <sys/kernel.h>
44#include <sys/module.h>
45#include <sys/lock.h>
46#include <sys/mutex.h>

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66
67static struct zy7_slcr_softc *zy7_slcr_softc_p;
68extern void (*zynq7_cpu_reset);
69
70#define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
71#define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
72#define ZSLCR_LOCK_INIT(sc) \
73 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
74 "zy7_slcr", MTX_SPIN)
74 "zy7_slcr", MTX_DEF)
75#define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
76
77#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
78#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
79
75#define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
76
77#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
78#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
79
80#define ZYNQ_DEFAULT_PS_CLK_FREQUENCY 33333333 /* 33.3 Mhz */
80
81
82
81SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000");
82
83static char zynq_bootmode[64];
84SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0,
85 "Zynq boot mode");
86
83SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000");
84
85static char zynq_bootmode[64];
86SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0,
87 "Zynq boot mode");
88
87static char zynq_pssid[80];
89static char zynq_pssid[100];
88SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0,
89 "Zynq PSS IDCODE");
90
91static uint32_t zynq_reboot_status;
92SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status,
93 0, "Zynq REBOOT_STATUS register");
94
90SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0,
91 "Zynq PSS IDCODE");
92
93static uint32_t zynq_reboot_status;
94SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status,
95 0, "Zynq REBOOT_STATUS register");
96
97static int ps_clk_frequency;
98SYSCTL_INT(_hw_zynq, OID_AUTO, ps_clk_frequency, CTLFLAG_RD, &ps_clk_frequency,
99 0, "Zynq PS_CLK Frequency");
100
101static int io_pll_frequency;
102SYSCTL_INT(_hw_zynq, OID_AUTO, io_pll_frequency, CTLFLAG_RD, &io_pll_frequency,
103 0, "Zynq IO PLL Frequency");
104
105static int arm_pll_frequency;
106SYSCTL_INT(_hw_zynq, OID_AUTO, arm_pll_frequency, CTLFLAG_RD,
107 &arm_pll_frequency, 0, "Zynq ARM PLL Frequency");
108
109static int ddr_pll_frequency;
110SYSCTL_INT(_hw_zynq, OID_AUTO, ddr_pll_frequency, CTLFLAG_RD,
111 &ddr_pll_frequency, 0, "Zynq DDR PLL Frequency");
112
95static void
96zy7_slcr_unlock(struct zy7_slcr_softc *sc)
97{
98
99 /* Unlock SLCR with magic number. */
100 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC);
101}
102

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184 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0);
185
186 /* Lock SLCR registers. */
187 zy7_slcr_lock(sc);
188
189 ZSLCR_UNLOCK(sc);
190}
191
113static void
114zy7_slcr_unlock(struct zy7_slcr_softc *sc)
115{
116
117 /* Unlock SLCR with magic number. */
118 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC);
119}
120

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202 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0);
203
204 /* Lock SLCR registers. */
205 zy7_slcr_lock(sc);
206
207 ZSLCR_UNLOCK(sc);
208}
209
210/* Override cgem_set_refclk() in gigabit ethernet driver
211 * (sys/dev/cadence/if_cgem.c). This function is called to
212 * request a change in the gem's reference clock speed.
213 */
214int
215cgem_set_ref_clk(int unit, int frequency)
216{
217 struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
218 int div0, div1;
219
220 if (!sc)
221 return (-1);
222
223 /* Find suitable divisor pairs. Round result to nearest khz
224 * to test for match.
225 */
226 for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) {
227 div0 = (io_pll_frequency + div1 * frequency / 2) /
228 div1 / frequency;
229 if (div0 > 0 && div0 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX &&
230 ((io_pll_frequency / div0 / div1) + 500) / 1000 ==
231 (frequency + 500) / 1000)
232 break;
233 }
234
235 if (div1 > ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX)
236 return (-1);
237
238 ZSLCR_LOCK(sc);
239
240 /* Unlock SLCR registers. */
241 zy7_slcr_unlock(sc);
242
243 /* Modify GEM reference clock. */
244 WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL,
245 (div1 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT) |
246 (div0 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT) |
247 ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL |
248 ZY7_SLCR_GEM_CLK_CTRL_CLKACT);
249
250 /* Lock SLCR registers. */
251 zy7_slcr_lock(sc);
252
253 ZSLCR_UNLOCK(sc);
254
255 return (0);
256}
257
192static int
193zy7_slcr_probe(device_t dev)
194{
195
196 if (!ofw_bus_status_okay(dev))
197 return (ENXIO);
198
199 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_slcr"))
200 return (ENXIO);
201
202 device_set_desc(dev, "Zynq-7000 slcr block");
203 return (0);
204}
205
206static int
207zy7_slcr_attach(device_t dev)
208{
209 struct zy7_slcr_softc *sc = device_get_softc(dev);
210 int rid;
258static int
259zy7_slcr_probe(device_t dev)
260{
261
262 if (!ofw_bus_status_okay(dev))
263 return (ENXIO);
264
265 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_slcr"))
266 return (ENXIO);
267
268 device_set_desc(dev, "Zynq-7000 slcr block");
269 return (0);
270}
271
272static int
273zy7_slcr_attach(device_t dev)
274{
275 struct zy7_slcr_softc *sc = device_get_softc(dev);
276 int rid;
277 phandle_t node;
278 pcell_t cell;
211 uint32_t bootmode;
212 uint32_t pss_idcode;
279 uint32_t bootmode;
280 uint32_t pss_idcode;
281 uint32_t arm_pll_ctrl;
282 uint32_t ddr_pll_ctrl;
283 uint32_t io_pll_ctrl;
213 static char *bootdev_names[] = {
214 "JTAG", "Quad-SPI", "NOR", "(3?)",
215 "NAND", "SD Card", "(6?)", "(7?)"
216 };
217
218 /* Allow only one attach. */
219 if (zy7_slcr_softc_p != NULL)
220 return (ENXIO);

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255 ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT,
256 (pss_idcode & ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK) >>
257 ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT,
258 (pss_idcode & ZY7_SLCR_PSS_IDCODE_REVISION_MASK) >>
259 ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT);
260
261 zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT);
262
284 static char *bootdev_names[] = {
285 "JTAG", "Quad-SPI", "NOR", "(3?)",
286 "NAND", "SD Card", "(6?)", "(7?)"
287 };
288
289 /* Allow only one attach. */
290 if (zy7_slcr_softc_p != NULL)
291 return (ENXIO);

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326 ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT,
327 (pss_idcode & ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK) >>
328 ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT,
329 (pss_idcode & ZY7_SLCR_PSS_IDCODE_REVISION_MASK) >>
330 ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT);
331
332 zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT);
333
334 /* Derive PLL frequencies from PS_CLK. */
335 node = ofw_bus_get_node(dev);
336 if (OF_getprop(node, "clock-frequency", &cell, sizeof(cell)) > 0)
337 ps_clk_frequency = fdt32_to_cpu(cell);
338 else
339 ps_clk_frequency = ZYNQ_DEFAULT_PS_CLK_FREQUENCY;
340
341 arm_pll_ctrl = RD4(sc, ZY7_SLCR_ARM_PLL_CTRL);
342 ddr_pll_ctrl = RD4(sc, ZY7_SLCR_DDR_PLL_CTRL);
343 io_pll_ctrl = RD4(sc, ZY7_SLCR_IO_PLL_CTRL);
344
345 /* Determine ARM PLL frequency. */
346 if (((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
347 (arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
348 ((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
349 (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
350 /* PLL is bypassed. */
351 arm_pll_frequency = ps_clk_frequency;
352 else
353 arm_pll_frequency = ps_clk_frequency *
354 ((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
355 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
356
357 /* Determine DDR PLL frequency. */
358 if (((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
359 (ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
360 ((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
361 (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
362 /* PLL is bypassed. */
363 ddr_pll_frequency = ps_clk_frequency;
364 else
365 ddr_pll_frequency = ps_clk_frequency *
366 ((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
367 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
368
369 /* Determine IO PLL frequency. */
370 if (((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
371 (io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
372 ((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
373 (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
374 /* PLL is bypassed. */
375 io_pll_frequency = ps_clk_frequency;
376 else
377 io_pll_frequency = ps_clk_frequency *
378 ((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
379 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
380
263 /* Lock SLCR registers. */
264 zy7_slcr_lock(sc);
265
266 return (0);
267}
268
269static int
270zy7_slcr_detach(device_t dev)

--- 36 unchanged lines hidden --- 		381 /* Lock SLCR registers. */
382 zy7_slcr_lock(sc);
383
384 return (0);
385}
386
387static int
388zy7_slcr_detach(device_t dev)

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