1/*-
2 * Copyright (c) 2013 Thomas Skibo
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/10/sys/arm/xilinx/zy7_slcr.c 266152 2014-05-15 16:11:06Z ian $
27 */
28
29/*
30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.
31 * In the future, maybe MIO control, clock control, etc. could go here.
32 *
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
34 * (v1.4) November 16, 2012. Xilinx doc UG585.
35 */
36
37#include <sys/cdefs.h>
38__FBSDID("$FreeBSD: stable/10/sys/arm/xilinx/zy7_slcr.c 266152 2014-05-15 16:11:06Z ian $");
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/conf.h>
43#include <sys/kernel.h>
44#include <sys/module.h>
45#include <sys/lock.h>
46#include <sys/mutex.h>

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66
67static struct zy7_slcr_softc *zy7_slcr_softc_p;
68extern void (*zynq7_cpu_reset);
69
70#define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
71#define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
72#define ZSLCR_LOCK_INIT(sc) \
73 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
74 "zy7_slcr", MTX_SPIN)
75#define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
76
77#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
78#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
79
80
81SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000");
82
83static char zynq_bootmode[64];
84SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0,
85 "Zynq boot mode");
86
87static char zynq_pssid[80];
88SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0,
89 "Zynq PSS IDCODE");
90
91static uint32_t zynq_reboot_status;
92SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status,
93 0, "Zynq REBOOT_STATUS register");
94
95static void
96zy7_slcr_unlock(struct zy7_slcr_softc *sc)
97{
98
99 /* Unlock SLCR with magic number. */
100 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC);
101}
102

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184 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0);
185
186 /* Lock SLCR registers. */
187 zy7_slcr_lock(sc);
188
189 ZSLCR_UNLOCK(sc);
190}
191
192static int
193zy7_slcr_probe(device_t dev)
194{
195
196 if (!ofw_bus_status_okay(dev))
197 return (ENXIO);
198
199 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_slcr"))
200 return (ENXIO);
201
202 device_set_desc(dev, "Zynq-7000 slcr block");
203 return (0);
204}
205
206static int
207zy7_slcr_attach(device_t dev)
208{
209 struct zy7_slcr_softc *sc = device_get_softc(dev);
210 int rid;
211 uint32_t bootmode;
212 uint32_t pss_idcode;
213 static char *bootdev_names[] = {
214 "JTAG", "Quad-SPI", "NOR", "(3?)",
215 "NAND", "SD Card", "(6?)", "(7?)"
216 };
217
218 /* Allow only one attach. */
219 if (zy7_slcr_softc_p != NULL)
220 return (ENXIO);

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255 ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT,
256 (pss_idcode & ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK) >>
257 ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT,
258 (pss_idcode & ZY7_SLCR_PSS_IDCODE_REVISION_MASK) >>
259 ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT);
260
261 zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT);
262
263 /* Lock SLCR registers. */
264 zy7_slcr_lock(sc);
265
266 return (0);
267}
268
269static int
270zy7_slcr_detach(device_t dev)

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