zy7_devcfg.c (266152) | zy7_devcfg.c (266379) |
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1/*- 2 * Copyright (c) 2013 Thomas Skibo 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2013 Thomas Skibo 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
26 * $FreeBSD: stable/10/sys/arm/xilinx/zy7_devcfg.c 266152 2014-05-15 16:11:06Z ian $ | 26 * $FreeBSD: stable/10/sys/arm/xilinx/zy7_devcfg.c 266379 2014-05-17 23:25:20Z ian $ |
27 */ 28 29/* 30 * Zynq-7000 Devcfg driver. This allows programming the PL (FPGA) section 31 * of Zynq. 32 * 33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 34 * (v1.4) November 16, 2012. Xilinx doc UG585. PL Configuration is 35 * covered in section 6.4.5. 36 */ 37 38#include <sys/cdefs.h> | 27 */ 28 29/* 30 * Zynq-7000 Devcfg driver. This allows programming the PL (FPGA) section 31 * of Zynq. 32 * 33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 34 * (v1.4) November 16, 2012. Xilinx doc UG585. PL Configuration is 35 * covered in section 6.4.5. 36 */ 37 38#include <sys/cdefs.h> |
39__FBSDID("$FreeBSD: stable/10/sys/arm/xilinx/zy7_devcfg.c 266152 2014-05-15 16:11:06Z ian $"); | 39__FBSDID("$FreeBSD: stable/10/sys/arm/xilinx/zy7_devcfg.c 266379 2014-05-17 23:25:20Z ian $"); |
40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/conf.h> 44#include <sys/kernel.h> 45#include <sys/module.h> 46#include <sys/sysctl.h> 47#include <sys/lock.h> --- 214 unchanged lines hidden (view full) --- 262{ 263 uint32_t devcfg_ctl; 264 int tries, err; 265 266 DEVCFG_SC_ASSERT_LOCKED(sc); 267 268 devcfg_ctl = RD4(sc, ZY7_DEVCFG_CTRL); 269 | 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/conf.h> 44#include <sys/kernel.h> 45#include <sys/module.h> 46#include <sys/sysctl.h> 47#include <sys/lock.h> --- 214 unchanged lines hidden (view full) --- 262{ 263 uint32_t devcfg_ctl; 264 int tries, err; 265 266 DEVCFG_SC_ASSERT_LOCKED(sc); 267 268 devcfg_ctl = RD4(sc, ZY7_DEVCFG_CTRL); 269 |
270 /* Clear sticky bits and set up INIT signal positive edge interrupt. */ 271 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 272 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE); 273 |
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270 /* Deassert PROG_B (active low). */ 271 devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B; 272 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 273 | 274 /* Deassert PROG_B (active low). */ 275 devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B; 276 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 277 |
274 /* Wait for INIT_B deasserted (active low). */ 275 tries = 0; 276 while ((RD4(sc, ZY7_DEVCFG_STATUS) & 277 ZY7_DEVCFG_STATUS_PCFG_INIT) == 0) { 278 if (++tries >= 100) 279 return (EIO); 280 DELAY(5); | 278 /* 279 * Wait for INIT to assert. If it is already asserted, we may not get 280 * an edge interrupt so cancel it and continue. 281 */ 282 if ((RD4(sc, ZY7_DEVCFG_STATUS) & 283 ZY7_DEVCFG_STATUS_PCFG_INIT) != 0) { 284 /* Already asserted. Cancel interrupt. */ 285 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0); |
281 } | 286 } |
282 283 /* Reassert PROG_B. */ | 287 else { 288 /* Wait for positive edge interrupt. */ 289 err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7i1", hz); 290 if (err != 0) 291 return (err); 292 } 293 294 /* Reassert PROG_B (active low). */ |
284 devcfg_ctl &= ~ZY7_DEVCFG_CTRL_PCFG_PROG_B; 285 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 286 | 295 devcfg_ctl &= ~ZY7_DEVCFG_CTRL_PCFG_PROG_B; 296 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 297 |
287 /* Wait for INIT_B asserted. */ | 298 /* Wait for INIT deasserted. This happens almost instantly. */ |
288 tries = 0; 289 while ((RD4(sc, ZY7_DEVCFG_STATUS) & 290 ZY7_DEVCFG_STATUS_PCFG_INIT) != 0) { 291 if (++tries >= 100) 292 return (EIO); 293 DELAY(5); 294 } 295 | 299 tries = 0; 300 while ((RD4(sc, ZY7_DEVCFG_STATUS) & 301 ZY7_DEVCFG_STATUS_PCFG_INIT) != 0) { 302 if (++tries >= 100) 303 return (EIO); 304 DELAY(5); 305 } 306 |
296 /* Clear sticky bits and set up INIT_B positive edge interrupt. */ | 307 /* Clear sticky bits and set up INIT positive edge interrupt. */ |
297 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 298 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE); 299 300 /* Deassert PROG_B again. */ 301 devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B; 302 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 303 | 308 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 309 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE); 310 311 /* Deassert PROG_B again. */ 312 devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B; 313 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 314 |
304 /* Wait for INIT_B deasserted indicating FPGA internal initialization 305 * is complete. This takes much longer than the previous waits for 306 * INIT_B transition (on the order of 700us). | 315 /* 316 * Wait for INIT asserted indicating FPGA internal initialization 317 * is complete. |
307 */ | 318 */ |
308 err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7in", hz); | 319 err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7i2", hz); |
309 if (err != 0) 310 return (err); 311 312 /* Clear sticky DONE bit in interrupt status. */ 313 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 314 315 return (0); 316} --- 82 unchanged lines hidden (view full) --- 399 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) & 400 ZY7_DEVCFG_INT_PCFG_DONE) != 0) { 401 err = EIO; 402 break; 403 } 404 405 /* uiomove the data from user buffer to our dma map. */ 406 segsz = MIN(PAGE_SIZE, uio->uio_resid); | 320 if (err != 0) 321 return (err); 322 323 /* Clear sticky DONE bit in interrupt status. */ 324 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 325 326 return (0); 327} --- 82 unchanged lines hidden (view full) --- 410 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) & 411 ZY7_DEVCFG_INT_PCFG_DONE) != 0) { 412 err = EIO; 413 break; 414 } 415 416 /* uiomove the data from user buffer to our dma map. */ 417 segsz = MIN(PAGE_SIZE, uio->uio_resid); |
418 DEVCFG_SC_UNLOCK(sc); |
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407 err = uiomove(dma_mem, segsz, uio); | 419 err = uiomove(dma_mem, segsz, uio); |
420 DEVCFG_SC_LOCK(sc); |
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408 if (err != 0) 409 break; 410 411 /* Flush the cache to memory. */ 412 bus_dmamap_sync(sc->dma_tag, sc->dma_map, 413 BUS_DMASYNC_PREWRITE); 414 415 /* Program devcfg's DMA engine. The ordering of these --- 240 unchanged lines hidden --- | 421 if (err != 0) 422 break; 423 424 /* Flush the cache to memory. */ 425 bus_dmamap_sync(sc->dma_tag, sc->dma_map, 426 BUS_DMASYNC_PREWRITE); 427 428 /* Program devcfg's DMA engine. The ordering of these --- 240 unchanged lines hidden --- |