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< * $FreeBSD: stable/10/sys/arm/xilinx/zy7_devcfg.c 266152 2014-05-15 16:11:06Z ian $
---
> * $FreeBSD: stable/10/sys/arm/xilinx/zy7_devcfg.c 266379 2014-05-17 23:25:20Z ian $
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< __FBSDID("$FreeBSD: stable/10/sys/arm/xilinx/zy7_devcfg.c 266152 2014-05-15 16:11:06Z ian $");
---
> __FBSDID("$FreeBSD: stable/10/sys/arm/xilinx/zy7_devcfg.c 266379 2014-05-17 23:25:20Z ian $");
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> /* Clear sticky bits and set up INIT signal positive edge interrupt. */
> WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
> WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE);
>
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< /* Wait for INIT_B deasserted (active low). */
< tries = 0;
< while ((RD4(sc, ZY7_DEVCFG_STATUS) &
< ZY7_DEVCFG_STATUS_PCFG_INIT) == 0) {
< if (++tries >= 100)
< return (EIO);
< DELAY(5);
---
> /*
> * Wait for INIT to assert. If it is already asserted, we may not get
> * an edge interrupt so cancel it and continue.
> */
> if ((RD4(sc, ZY7_DEVCFG_STATUS) &
> ZY7_DEVCFG_STATUS_PCFG_INIT) != 0) {
> /* Already asserted. Cancel interrupt. */
> WR4(sc, ZY7_DEVCFG_INT_MASK, ~0);
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<
< /* Reassert PROG_B. */
---
> else {
> /* Wait for positive edge interrupt. */
> err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7i1", hz);
> if (err != 0)
> return (err);
> }
>
> /* Reassert PROG_B (active low). */
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< /* Wait for INIT_B asserted. */
---
> /* Wait for INIT deasserted. This happens almost instantly. */
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< /* Clear sticky bits and set up INIT_B positive edge interrupt. */
---
> /* Clear sticky bits and set up INIT positive edge interrupt. */
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< /* Wait for INIT_B deasserted indicating FPGA internal initialization
< * is complete. This takes much longer than the previous waits for
< * INIT_B transition (on the order of 700us).
---
> /*
> * Wait for INIT asserted indicating FPGA internal initialization
> * is complete.
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< err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7in", hz);
---
> err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7i2", hz);
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> DEVCFG_SC_UNLOCK(sc);
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> DEVCFG_SC_LOCK(sc);