1/*-
2 * Copyright (c) 2013 Thomas Skibo
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/10/sys/arm/xilinx/zy7_devcfg.c 266152 2014-05-15 16:11:06Z ian $
27 */
28
29/*
30 * Zynq-7000 Devcfg driver. This allows programming the PL (FPGA) section
31 * of Zynq.
32 *
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
34 * (v1.4) November 16, 2012. Xilinx doc UG585. PL Configuration is
35 * covered in section 6.4.5.
36 */
37
38#include <sys/cdefs.h>
39__FBSDID("$FreeBSD: stable/10/sys/arm/xilinx/zy7_devcfg.c 266152 2014-05-15 16:11:06Z ian $");
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/conf.h>
44#include <sys/kernel.h>
45#include <sys/module.h>
46#include <sys/sysctl.h>
47#include <sys/lock.h>

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262{
263 uint32_t devcfg_ctl;
264 int tries, err;
265
266 DEVCFG_SC_ASSERT_LOCKED(sc);
267
268 devcfg_ctl = RD4(sc, ZY7_DEVCFG_CTRL);
269
270 /* Deassert PROG_B (active low). */
271 devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B;
272 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
273
274 /* Wait for INIT_B deasserted (active low). */
275 tries = 0;
276 while ((RD4(sc, ZY7_DEVCFG_STATUS) &
277 ZY7_DEVCFG_STATUS_PCFG_INIT) == 0) {
278 if (++tries >= 100)
279 return (EIO);
280 DELAY(5);
281 }
282
283 /* Reassert PROG_B. */
284 devcfg_ctl &= ~ZY7_DEVCFG_CTRL_PCFG_PROG_B;
285 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
286
287 /* Wait for INIT_B asserted. */
288 tries = 0;
289 while ((RD4(sc, ZY7_DEVCFG_STATUS) &
290 ZY7_DEVCFG_STATUS_PCFG_INIT) != 0) {
291 if (++tries >= 100)
292 return (EIO);
293 DELAY(5);
294 }
295
296 /* Clear sticky bits and set up INIT_B positive edge interrupt. */
297 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
298 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE);
299
300 /* Deassert PROG_B again. */
301 devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B;
302 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
303
304 /* Wait for INIT_B deasserted indicating FPGA internal initialization
305 * is complete. This takes much longer than the previous waits for
306 * INIT_B transition (on the order of 700us).
307 */
308 err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7in", hz);
309 if (err != 0)
310 return (err);
311
312 /* Clear sticky DONE bit in interrupt status. */
313 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
314
315 return (0);
316}

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399 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
400 ZY7_DEVCFG_INT_PCFG_DONE) != 0) {
401 err = EIO;
402 break;
403 }
404
405 /* uiomove the data from user buffer to our dma map. */
406 segsz = MIN(PAGE_SIZE, uio->uio_resid);
407 err = uiomove(dma_mem, segsz, uio);
408 if (err != 0)
409 break;
410
411 /* Flush the cache to memory. */
412 bus_dmamap_sync(sc->dma_tag, sc->dma_map,
413 BUS_DMASYNC_PREWRITE);
414
415 /* Program devcfg's DMA engine. The ordering of these

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