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exynos5_fimd.c (263426) exynos5_fimd.c (266332)
1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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25 */
26
27/*
28 * Samsung Exynos 5 Display Controller
29 * Chapter 15, Exynos 5 Dual User's Manual Public Rev 1.00
30 */
31
32#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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25 */
26
27/*
28 * Samsung Exynos 5 Display Controller
29 * Chapter 15, Exynos 5 Dual User's Manual Public Rev 1.00
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/arm/samsung/exynos/exynos5_fimd.c 263426 2014-03-20 17:07:14Z br $");
33__FBSDID("$FreeBSD: stable/10/sys/arm/samsung/exynos/exynos5_fimd.c 266332 2014-05-17 17:54:38Z ian $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38#include <sys/kernel.h>
39#include <sys/module.h>
40#include <sys/malloc.h>
41#include <sys/rman.h>

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251 int reg;
252
253 panel = sc->panel;
254
255 /* fb_init */
256 reg = panel->ivclk | panel->fixvclk;
257 DWRITE4(sc,VIDCON1,reg);
258
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38#include <sys/kernel.h>
39#include <sys/module.h>
40#include <sys/malloc.h>
41#include <sys/rman.h>

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251 int reg;
252
253 panel = sc->panel;
254
255 /* fb_init */
256 reg = panel->ivclk | panel->fixvclk;
257 DWRITE4(sc,VIDCON1,reg);
258
259 printf("print to VIDCON0\n");
260 reg = (VIDCON0_ENVID | VIDCON0_ENVID_F);
261 reg |= (panel->clkval_f << CLKVAL_F_OFFSET);
262 WRITE4(sc,VIDCON0,reg);
263
259 reg = (VIDCON0_ENVID | VIDCON0_ENVID_F);
260 reg |= (panel->clkval_f << CLKVAL_F_OFFSET);
261 WRITE4(sc,VIDCON0,reg);
262
264 printf("print to VIDCON0 2nd\n");
265 reg = (panel->v_pulse_width << VSYNC_PULSE_WIDTH_OFFSET);
266 reg |= (panel->v_front_porch << V_FRONT_PORCH_OFFSET);
267 reg |= (panel->v_back_porch << V_BACK_PORCH_OFFSET);
268 DWRITE4(sc,VIDTCON0,reg);
269
270 reg = (panel->h_pulse_width << HSYNC_PULSE_WIDTH_OFFSET);
271 reg |= (panel->h_front_porch << H_FRONT_PORCH_OFFSET);
272 reg |= (panel->h_back_porch << H_BACK_PORCH_OFFSET);
273 DWRITE4(sc,VIDTCON1,reg);
274
275 reg = ((panel->width - 1) << HOZVAL_OFFSET);
276 reg |= ((panel->height - 1) << LINEVAL_OFFSET);
277 DWRITE4(sc,VIDTCON2,reg);
278
263 reg = (panel->v_pulse_width << VSYNC_PULSE_WIDTH_OFFSET);
264 reg |= (panel->v_front_porch << V_FRONT_PORCH_OFFSET);
265 reg |= (panel->v_back_porch << V_BACK_PORCH_OFFSET);
266 DWRITE4(sc,VIDTCON0,reg);
267
268 reg = (panel->h_pulse_width << HSYNC_PULSE_WIDTH_OFFSET);
269 reg |= (panel->h_front_porch << H_FRONT_PORCH_OFFSET);
270 reg |= (panel->h_back_porch << H_BACK_PORCH_OFFSET);
271 DWRITE4(sc,VIDTCON1,reg);
272
273 reg = ((panel->width - 1) << HOZVAL_OFFSET);
274 reg |= ((panel->height - 1) << LINEVAL_OFFSET);
275 DWRITE4(sc,VIDTCON2,reg);
276
279 printf("set pbase\n");
280 printf("vbase is 0x%08x\n", sc->sc_info.fb_vbase);
281 printf("pbase is 0x%08x\n", sc->sc_info.fb_pbase);
282
283 WRITE4(sc,VIDW00ADD0B0, sc->sc_info.fb_pbase);
284 WRITE4(sc,VIDW00ADD1B0, sc->sc_info.fb_pbase + sc->sc_info.fb_size);
285 WRITE4(sc,VIDW00ADD2, panel->width * 2);
286
287 reg = ((panel->width - 1) << OSD_RIGHTBOTX_F_OFFSET);
288 reg |= ((panel->height - 1) << OSD_RIGHTBOTY_F_OFFSET);
289 WRITE4(sc,VIDOSD0B,reg);
290

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277 WRITE4(sc,VIDW00ADD0B0, sc->sc_info.fb_pbase);
278 WRITE4(sc,VIDW00ADD1B0, sc->sc_info.fb_pbase + sc->sc_info.fb_size);
279 WRITE4(sc,VIDW00ADD2, panel->width * 2);
280
281 reg = ((panel->width - 1) << OSD_RIGHTBOTX_F_OFFSET);
282 reg |= ((panel->height - 1) << OSD_RIGHTBOTY_F_OFFSET);
283 WRITE4(sc,VIDOSD0B,reg);
284

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