1/*-
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
| 1/*-
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
|
33__FBSDID("$FreeBSD: stable/10/sys/arm/mv/orion/db88f5xxx.c 259329 2013-12-13 20:43:11Z ian $");
| 33__FBSDID("$FreeBSD: stable/10/sys/arm/mv/orion/db88f5xxx.c 266386 2014-05-18 00:32:35Z ian $");
|
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38#include <sys/kernel.h>
39
40#include <vm/vm.h>
41#include <vm/pmap.h>
42
43#include <machine/bus.h>
44#include <machine/intr.h>
45#include <machine/pte.h>
46#include <machine/vmparam.h>
47
48#include <arm/mv/mvreg.h>
49#include <arm/mv/mvvar.h>
50#include <arm/mv/mvwin.h>
51
52/*
53 * Virtual address space layout:
54 * -----------------------------
55 * 0x0000_0000 - 0xbfff_ffff : user process
56 *
57 * 0xc040_0000 - virtual_avail : kernel reserved (text, data, page tables
58 * : structures, ARM stacks etc.)
59 * virtual_avail - 0xefff_ffff : KVA (virtual_avail is typically < 0xc0a0_0000)
60 * 0xf000_0000 - 0xf0ff_ffff : no-cache allocation area (16MB)
61 * 0xf100_0000 - 0xf10f_ffff : SoC integrated devices registers range (1MB)
62 * 0xf110_0000 - 0xf11f_ffff : PCI-Express I/O space (1MB)
63 * 0xf120_0000 - 0xf12f_ffff : PCI I/O space (1MB)
64 * 0xf130_0000 - 0xf52f_ffff : PCI-Express memory space (64MB)
65 * 0xf530_0000 - 0xf92f_ffff : PCI memory space (64MB)
66 * 0xf930_0000 - 0xfffe_ffff : unused (~108MB)
67 * 0xffff_0000 - 0xffff_0fff : 'high' vectors page (4KB)
68 * 0xffff_1000 - 0xffff_1fff : ARM_TP_ADDRESS/RAS page (4KB)
69 * 0xffff_2000 - 0xffff_ffff : unused (~55KB)
70 */
71
72
73#if 0
74int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin);
75
76/* Static device mappings. */
77const struct pmap_devmap pmap_devmap[] = {
78 /*
79 * Map the on-board devices VA == PA so that we can access them
80 * with the MMU on or off.
81 */
82 { /* SoC integrated peripherals registers range */
83 MV_BASE,
84 MV_PHYS_BASE,
85 MV_SIZE,
86 VM_PROT_READ | VM_PROT_WRITE,
| 34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38#include <sys/kernel.h>
39
40#include <vm/vm.h>
41#include <vm/pmap.h>
42
43#include <machine/bus.h>
44#include <machine/intr.h>
45#include <machine/pte.h>
46#include <machine/vmparam.h>
47
48#include <arm/mv/mvreg.h>
49#include <arm/mv/mvvar.h>
50#include <arm/mv/mvwin.h>
51
52/*
53 * Virtual address space layout:
54 * -----------------------------
55 * 0x0000_0000 - 0xbfff_ffff : user process
56 *
57 * 0xc040_0000 - virtual_avail : kernel reserved (text, data, page tables
58 * : structures, ARM stacks etc.)
59 * virtual_avail - 0xefff_ffff : KVA (virtual_avail is typically < 0xc0a0_0000)
60 * 0xf000_0000 - 0xf0ff_ffff : no-cache allocation area (16MB)
61 * 0xf100_0000 - 0xf10f_ffff : SoC integrated devices registers range (1MB)
62 * 0xf110_0000 - 0xf11f_ffff : PCI-Express I/O space (1MB)
63 * 0xf120_0000 - 0xf12f_ffff : PCI I/O space (1MB)
64 * 0xf130_0000 - 0xf52f_ffff : PCI-Express memory space (64MB)
65 * 0xf530_0000 - 0xf92f_ffff : PCI memory space (64MB)
66 * 0xf930_0000 - 0xfffe_ffff : unused (~108MB)
67 * 0xffff_0000 - 0xffff_0fff : 'high' vectors page (4KB)
68 * 0xffff_1000 - 0xffff_1fff : ARM_TP_ADDRESS/RAS page (4KB)
69 * 0xffff_2000 - 0xffff_ffff : unused (~55KB)
70 */
71
72
73#if 0
74int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin);
75
76/* Static device mappings. */
77const struct pmap_devmap pmap_devmap[] = {
78 /*
79 * Map the on-board devices VA == PA so that we can access them
80 * with the MMU on or off.
81 */
82 { /* SoC integrated peripherals registers range */
83 MV_BASE,
84 MV_PHYS_BASE,
85 MV_SIZE,
86 VM_PROT_READ | VM_PROT_WRITE,
|
87 PTE_NOCACHE,
| 87 PTE_DEVICE,
|
88 },
89 { /* PCIE I/O */
90 MV_PCIE_IO_BASE,
91 MV_PCIE_IO_PHYS_BASE,
92 MV_PCIE_IO_SIZE,
93 VM_PROT_READ | VM_PROT_WRITE,
| 88 },
89 { /* PCIE I/O */
90 MV_PCIE_IO_BASE,
91 MV_PCIE_IO_PHYS_BASE,
92 MV_PCIE_IO_SIZE,
93 VM_PROT_READ | VM_PROT_WRITE,
|
94 PTE_NOCACHE,
| 94 PTE_DEVICE,
|
95 },
96 { /* PCIE Memory */
97 MV_PCIE_MEM_BASE,
98 MV_PCIE_MEM_PHYS_BASE,
99 MV_PCIE_MEM_SIZE,
100 VM_PROT_READ | VM_PROT_WRITE,
| 95 },
96 { /* PCIE Memory */
97 MV_PCIE_MEM_BASE,
98 MV_PCIE_MEM_PHYS_BASE,
99 MV_PCIE_MEM_SIZE,
100 VM_PROT_READ | VM_PROT_WRITE,
|
101 PTE_NOCACHE,
| 101 PTE_DEVICE,
|
102 },
103 { /* PCI I/O */
104 MV_PCI_IO_BASE,
105 MV_PCI_IO_PHYS_BASE,
106 MV_PCI_IO_SIZE,
107 VM_PROT_READ | VM_PROT_WRITE,
| 102 },
103 { /* PCI I/O */
104 MV_PCI_IO_BASE,
105 MV_PCI_IO_PHYS_BASE,
106 MV_PCI_IO_SIZE,
107 VM_PROT_READ | VM_PROT_WRITE,
|
108 PTE_NOCACHE,
| 108 PTE_DEVICE,
|
109 },
110 { /* PCI Memory */
111 MV_PCI_MEM_BASE,
112 MV_PCI_MEM_PHYS_BASE,
113 MV_PCI_MEM_SIZE,
114 VM_PROT_READ | VM_PROT_WRITE,
| 109 },
110 { /* PCI Memory */
111 MV_PCI_MEM_BASE,
112 MV_PCI_MEM_PHYS_BASE,
113 MV_PCI_MEM_SIZE,
114 VM_PROT_READ | VM_PROT_WRITE,
|
115 PTE_NOCACHE,
| 115 PTE_DEVICE,
|
116 },
117 { /* 7-seg LED */
118 MV_DEV_CS0_BASE,
119 MV_DEV_CS0_PHYS_BASE,
120 MV_DEV_CS0_SIZE,
121 VM_PROT_READ | VM_PROT_WRITE,
| 116 },
117 { /* 7-seg LED */
118 MV_DEV_CS0_BASE,
119 MV_DEV_CS0_PHYS_BASE,
120 MV_DEV_CS0_SIZE,
121 VM_PROT_READ | VM_PROT_WRITE,
|
122 PTE_NOCACHE,
| 122 PTE_DEVICE,
|
123 },
124 { 0, 0, 0, 0, 0, }
125};
126
127/*
128 * The pci_irq_map table consists of 3 columns:
129 * - PCI slot number (less than zero means ANY).
130 * - PCI IRQ pin (less than zero means ANY).
131 * - PCI IRQ (less than zero marks end of table).
132 *
133 * IRQ number from the first matching entry is used to configure PCI device
134 */
135
136/* PCI IRQ Map for DB-88F5281 */
137const struct obio_pci_irq_map pci_irq_map[] = {
138 { 7, -1, GPIO2IRQ(12) },
139 { 8, -1, GPIO2IRQ(13) },
140 { 9, -1, GPIO2IRQ(13) },
141 { -1, -1, -1 }
142};
143
144/* PCI IRQ Map for DB-88F5182 */
145const struct obio_pci_irq_map pci_irq_map[] = {
146 { 7, -1, GPIO2IRQ(0) },
147 { 8, -1, GPIO2IRQ(1) },
148 { 9, -1, GPIO2IRQ(1) },
149 { -1, -1, -1 }
150};
151#endif
152
153#if 0
154/*
155 * mv_gpio_config row structure:
156 * <GPIO number>, <GPIO flags>, <GPIO mode>
157 *
158 * - GPIO pin number (less than zero marks end of table)
159 * - GPIO flags:
160 * MV_GPIO_BLINK
161 * MV_GPIO_POLAR_LOW
162 * MV_GPIO_EDGE
163 * MV_GPIO_LEVEL
164 * - GPIO mode:
165 * 1 - Output, set to HIGH.
166 * 0 - Output, set to LOW.
167 * -1 - Input.
168 */
169
170/* GPIO Configuration for DB-88F5281 */
171const struct gpio_config mv_gpio_config[] = {
172 { 12, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
173 { 13, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
174 { -1, -1, -1 }
175};
176
177#if 0
178/* GPIO Configuration for DB-88F5182 */
179const struct gpio_config mv_gpio_config[] = {
180 { 0, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
181 { 1, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
182 { -1, -1, -1 }
183};
184#endif
185
186#endif
| 123 },
124 { 0, 0, 0, 0, 0, }
125};
126
127/*
128 * The pci_irq_map table consists of 3 columns:
129 * - PCI slot number (less than zero means ANY).
130 * - PCI IRQ pin (less than zero means ANY).
131 * - PCI IRQ (less than zero marks end of table).
132 *
133 * IRQ number from the first matching entry is used to configure PCI device
134 */
135
136/* PCI IRQ Map for DB-88F5281 */
137const struct obio_pci_irq_map pci_irq_map[] = {
138 { 7, -1, GPIO2IRQ(12) },
139 { 8, -1, GPIO2IRQ(13) },
140 { 9, -1, GPIO2IRQ(13) },
141 { -1, -1, -1 }
142};
143
144/* PCI IRQ Map for DB-88F5182 */
145const struct obio_pci_irq_map pci_irq_map[] = {
146 { 7, -1, GPIO2IRQ(0) },
147 { 8, -1, GPIO2IRQ(1) },
148 { 9, -1, GPIO2IRQ(1) },
149 { -1, -1, -1 }
150};
151#endif
152
153#if 0
154/*
155 * mv_gpio_config row structure:
156 * <GPIO number>, <GPIO flags>, <GPIO mode>
157 *
158 * - GPIO pin number (less than zero marks end of table)
159 * - GPIO flags:
160 * MV_GPIO_BLINK
161 * MV_GPIO_POLAR_LOW
162 * MV_GPIO_EDGE
163 * MV_GPIO_LEVEL
164 * - GPIO mode:
165 * 1 - Output, set to HIGH.
166 * 0 - Output, set to LOW.
167 * -1 - Input.
168 */
169
170/* GPIO Configuration for DB-88F5281 */
171const struct gpio_config mv_gpio_config[] = {
172 { 12, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
173 { 13, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
174 { -1, -1, -1 }
175};
176
177#if 0
178/* GPIO Configuration for DB-88F5182 */
179const struct gpio_config mv_gpio_config[] = {
180 { 0, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
181 { 1, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
182 { -1, -1, -1 }
183};
184#endif
185
186#endif
|