1/*-
2 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
3 * Copyright (c) 2010 The FreeBSD Foundation
4 * Copyright (c) 2010-2012 Semihalf
5 * All rights reserved.
6 *
7 * Developed by Semihalf.
8 *
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34 * SUCH DAMAGE.
35 */
36
37/*
38 * Marvell integrated PCI/PCI-Express controller driver.
39 */
40
41#include <sys/cdefs.h>
42__FBSDID("$FreeBSD: head/sys/arm/mv/mv_pci.c 240489 2012-09-14 09:57:41Z gber $");
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/kernel.h>
47#include <sys/lock.h>
48#include <sys/malloc.h>
49#include <sys/module.h>
50#include <sys/mutex.h>
51#include <sys/queue.h>
52#include <sys/bus.h>
53#include <sys/rman.h>
54#include <sys/endian.h>
55
56#include <vm/vm.h>
57#include <vm/pmap.h>
58
59#include <dev/fdt/fdt_common.h>
60#include <dev/ofw/ofw_bus.h>
61#include <dev/ofw/ofw_bus_subr.h>
62#include <dev/pci/pcivar.h>
63#include <dev/pci/pcireg.h>
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68
69#include <machine/resource.h>
70#include <machine/bus.h>
71
72#include <arm/mv/mvreg.h>
73#include <arm/mv/mvvar.h>
74#include <arm/mv/mvwin.h>
75
76#define PCI_CFG_ENA (1 << 31)
77#define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16)
78#define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11)
79#define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8)
80#define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc)
81
82#define PCI_REG_CFG_ADDR 0x0C78
83#define PCI_REG_CFG_DATA 0x0C7C
84#define PCI_REG_P2P_CONF 0x1D14
85
86#define PCIE_REG_CFG_ADDR 0x18F8
87#define PCIE_REG_CFG_DATA 0x18FC
88#define PCIE_REG_CONTROL 0x1A00
89#define PCIE_CTRL_LINK1X 0x00000001
90#define PCIE_REG_STATUS 0x1A04
91#define PCIE_REG_IRQ_MASK 0x1910
92
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122 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
123 int sc_io_win_attr;
124
125 struct resource *sc_res;
126 bus_space_handle_t sc_bsh;
127 bus_space_tag_t sc_bst;
128 int sc_rid;
129
130 int sc_busnr; /* Host bridge bus number */
131 int sc_devnr; /* Host bridge device number */
132 int sc_type;
133 int sc_mode; /* Endpoint / Root Complex */
134
135 struct fdt_pci_intr sc_intr_info;
136};
137
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161static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
162static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t);
163
164static int mv_pcib_maxslots(device_t);
165static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
166static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
167 uint32_t, int);
168static int mv_pcib_route_interrupt(device_t, device_t, int);
169
170/*
171 * Bus interface definitions.
172 */
173static device_method_t mv_pcib_methods[] = {
174 /* Device interface */
175 DEVMETHOD(device_probe, mv_pcib_probe),
176 DEVMETHOD(device_attach, mv_pcib_attach),
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185 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
186 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
187
188 /* pcib interface */
189 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots),
190 DEVMETHOD(pcib_read_config, mv_pcib_read_config),
191 DEVMETHOD(pcib_write_config, mv_pcib_write_config),
192 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt),
193
194 /* OFW bus interface */
195 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
196 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
197 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
198 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
199 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
200
201 DEVMETHOD_END
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313 device_add_child(self, "pci", -1);
314 } else {
315 sc->sc_devnr = 1;
316 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
317 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS);
318 device_add_child(self, "pci_ep", -1);
319 }
320
321 return (bus_generic_attach(self));
322
323error:
324 /* XXX SYS_RES_ should be released here */
325 rman_fini(&sc->sc_mem_rman);
326 rman_fini(&sc->sc_io_rman);
327
328 return (err);
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922 int error;
923
924 if ((error = fdt_pci_intr_info(node, &sc->sc_intr_info)) != 0)
925 return (error);
926
927 return (0);
928}
929
2 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
3 * Copyright (c) 2010 The FreeBSD Foundation
4 * Copyright (c) 2010-2012 Semihalf
5 * All rights reserved.
6 *
7 * Developed by Semihalf.
8 *
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34 * SUCH DAMAGE.
35 */
36
37/*
38 * Marvell integrated PCI/PCI-Express controller driver.
39 */
40
41#include <sys/cdefs.h>
42__FBSDID("$FreeBSD: head/sys/arm/mv/mv_pci.c 240489 2012-09-14 09:57:41Z gber $");
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/kernel.h>
47#include <sys/lock.h>
48#include <sys/malloc.h>
49#include <sys/module.h>
50#include <sys/mutex.h>
51#include <sys/queue.h>
52#include <sys/bus.h>
53#include <sys/rman.h>
54#include <sys/endian.h>
55
56#include <vm/vm.h>
57#include <vm/pmap.h>
58
59#include <dev/fdt/fdt_common.h>
60#include <dev/ofw/ofw_bus.h>
61#include <dev/ofw/ofw_bus_subr.h>
62#include <dev/pci/pcivar.h>
63#include <dev/pci/pcireg.h>
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68
69#include <machine/resource.h>
70#include <machine/bus.h>
71
72#include <arm/mv/mvreg.h>
73#include <arm/mv/mvvar.h>
74#include <arm/mv/mvwin.h>
75
76#define PCI_CFG_ENA (1 << 31)
77#define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16)
78#define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11)
79#define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8)
80#define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc)
81
82#define PCI_REG_CFG_ADDR 0x0C78
83#define PCI_REG_CFG_DATA 0x0C7C
84#define PCI_REG_P2P_CONF 0x1D14
85
86#define PCIE_REG_CFG_ADDR 0x18F8
87#define PCIE_REG_CFG_DATA 0x18FC
88#define PCIE_REG_CONTROL 0x1A00
89#define PCIE_CTRL_LINK1X 0x00000001
90#define PCIE_REG_STATUS 0x1A04
91#define PCIE_REG_IRQ_MASK 0x1910
92
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122 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
123 int sc_io_win_attr;
124
125 struct resource *sc_res;
126 bus_space_handle_t sc_bsh;
127 bus_space_tag_t sc_bst;
128 int sc_rid;
129
130 int sc_busnr; /* Host bridge bus number */
131 int sc_devnr; /* Host bridge device number */
132 int sc_type;
133 int sc_mode; /* Endpoint / Root Complex */
134
135 struct fdt_pci_intr sc_intr_info;
136};
137
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161static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
162static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t);
163
164static int mv_pcib_maxslots(device_t);
165static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
166static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
167 uint32_t, int);
168static int mv_pcib_route_interrupt(device_t, device_t, int);
169
170/*
171 * Bus interface definitions.
172 */
173static device_method_t mv_pcib_methods[] = {
174 /* Device interface */
175 DEVMETHOD(device_probe, mv_pcib_probe),
176 DEVMETHOD(device_attach, mv_pcib_attach),
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185 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
186 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
187
188 /* pcib interface */
189 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots),
190 DEVMETHOD(pcib_read_config, mv_pcib_read_config),
191 DEVMETHOD(pcib_write_config, mv_pcib_write_config),
192 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt),
193
194 /* OFW bus interface */
195 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
196 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
197 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
198 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
199 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
200
201 DEVMETHOD_END
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313 device_add_child(self, "pci", -1);
314 } else {
315 sc->sc_devnr = 1;
316 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
317 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS);
318 device_add_child(self, "pci_ep", -1);
319 }
320
321 return (bus_generic_attach(self));
322
323error:
324 /* XXX SYS_RES_ should be released here */
325 rman_fini(&sc->sc_mem_rman);
326 rman_fini(&sc->sc_io_rman);
327
328 return (err);
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922 int error;
923
924 if ((error = fdt_pci_intr_info(node, &sc->sc_intr_info)) != 0)
925 return (error);
926
927 return (0);
928}
929