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lpc_machdep.c (259365) lpc_machdep.c (266084)
1/*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without

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34 *
35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
36 */
37
38#include "opt_ddb.h"
39#include "opt_platform.h"
40
41#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without

--- 25 unchanged lines hidden (view full) ---

34 *
35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
36 */
37
38#include "opt_ddb.h"
39#include "opt_platform.h"
40
41#include <sys/cdefs.h>
42__FBSDID("$FreeBSD: stable/10/sys/arm/lpc/lpc_machdep.c 259365 2013-12-14 00:16:08Z ian $");
42__FBSDID("$FreeBSD: stable/10/sys/arm/lpc/lpc_machdep.c 266084 2014-05-14 19:18:58Z ian $");
43
44#define _ARM32_BUS_DMA_PRIVATE
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/bus.h>
48
49#include <vm/vm.h>
50#include <vm/pmap.h>
51
52#include <machine/bus.h>
43
44#define _ARM32_BUS_DMA_PRIVATE
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/bus.h>
48
49#include <vm/vm.h>
50#include <vm/pmap.h>
51
52#include <machine/bus.h>
53#include <machine/fdt.h>
53#include <machine/devmap.h>
54#include <machine/machdep.h>
55
56#include <arm/lpc/lpcreg.h>
57#include <arm/lpc/lpcvar.h>
58
59#include <dev/fdt/fdt_common.h>
54#include <machine/devmap.h>
55#include <machine/machdep.h>
56
57#include <arm/lpc/lpcreg.h>
58#include <arm/lpc/lpcvar.h>
59
60#include <dev/fdt/fdt_common.h>
60#include <dev/ic/ns16550.h>
61
62vm_offset_t
63initarm_lastaddr(void)
64{
65
61
62vm_offset_t
63initarm_lastaddr(void)
64{
65
66 return (fdt_immr_va);
66 return (arm_devmap_lastaddr());
67}
68
69void
70initarm_early_init(void)
71{
67}
68
69void
70initarm_early_init(void)
71{
72
73 if (fdt_immr_addr(LPC_DEV_BASE) != 0)
74 while (1);
75}
76
77void
78initarm_gpio_init(void)
79{
80
81 /*
82 * Set initial values of GPIO output ports
83 */
84 platform_gpio_init();
85}
86
87void
88initarm_late_init(void)
89{
90}
91
72}
73
74void
75initarm_gpio_init(void)
76{
77
78 /*
79 * Set initial values of GPIO output ports
80 */
81 platform_gpio_init();
82}
83
84void
85initarm_late_init(void)
86{
87}
88
92#define FDT_DEVMAP_MAX (1 + 2 + 1 + 1)
93static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
94 { 0, 0, 0, 0, 0, }
95};
96
97/*
89/*
98 * Construct pmap_devmap[] with DT-derived config data.
90 * Add a single static device mapping.
91 * The values used were taken from the ranges property of the SoC node in the
92 * dts file when this code was converted to arm_devmap_add_entry().
99 */
100int
101initarm_devmap_init(void)
102{
103
93 */
94int
95initarm_devmap_init(void)
96{
97
104 /*
105 * IMMR range.
106 */
107 fdt_devmap[0].pd_va = fdt_immr_va;
108 fdt_devmap[0].pd_pa = fdt_immr_pa;
109 fdt_devmap[0].pd_size = fdt_immr_size;
110 fdt_devmap[0].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
111 fdt_devmap[0].pd_cache = PTE_NOCACHE;
112
113 arm_devmap_register_table(&fdt_devmap[0]);
98 arm_devmap_add_entry(LPC_DEV_PHYS_BASE, LPC_DEV_SIZE);
114 return (0);
115}
116
117struct arm32_dma_range *
118bus_dma_get_range(void)
119{
120
121 return (NULL);

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126{
127
128 return (0);
129}
130
131void
132cpu_reset(void)
133{
99 return (0);
100}
101
102struct arm32_dma_range *
103bus_dma_get_range(void)
104{
105
106 return (NULL);

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111{
112
113 return (0);
114}
115
116void
117cpu_reset(void)
118{
119 bus_space_tag_t bst;
120 bus_space_handle_t bsh;
121
122 bst = fdtbus_bs_tag;
123
134 /* Enable WDT */
124 /* Enable WDT */
135 bus_space_write_4(fdtbus_bs_tag,
136 LPC_CLKPWR_BASE, LPC_CLKPWR_TIMCLK_CTRL,
125 bus_space_map(bst, LPC_CLKPWR_PHYS_BASE, LPC_CLKPWR_SIZE, 0, &bsh);
126 bus_space_write_4(bst, bsh, LPC_CLKPWR_TIMCLK_CTRL,
137 LPC_CLKPWR_TIMCLK_CTRL_WATCHDOG);
127 LPC_CLKPWR_TIMCLK_CTRL_WATCHDOG);
128 bus_space_unmap(bst, bsh, LPC_CLKPWR_SIZE);
138
139 /* Instant assert of RESETOUT_N with pulse length 1ms */
129
130 /* Instant assert of RESETOUT_N with pulse length 1ms */
140 bus_space_write_4(fdtbus_bs_tag, LPC_WDTIM_BASE, LPC_WDTIM_PULSE, 13000);
141 bus_space_write_4(fdtbus_bs_tag, LPC_WDTIM_BASE, LPC_WDTIM_MCTRL, 0x70);
131 bus_space_map(bst, LPC_WDTIM_PHYS_BASE, LPC_WDTIM_SIZE, 0, &bsh);
132 bus_space_write_4(bst, bsh, LPC_WDTIM_PULSE, 13000);
133 bus_space_write_4(bst, bsh, LPC_WDTIM_MCTRL, 0x70);
134 bus_space_unmap(bst, bsh, LPC_WDTIM_SIZE);
142
135
143 for (;;);
136 for (;;)
137 continue;
144}
145
138}
139