| cpufunc.h (266058) | cpufunc.h (266203) |
|---|---|
| 1/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3/*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 24 unchanged lines hidden (view full) --- 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * | 1/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3/*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 24 unchanged lines hidden (view full) --- 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * |
| 41 * $FreeBSD: stable/10/sys/arm/include/cpufunc.h 266058 2014-05-14 17:40:18Z ian $ | 41 * $FreeBSD: stable/10/sys/arm/include/cpufunc.h 266203 2014-05-16 00:14:50Z ian $ |
| 42 */ 43 44#ifndef _MACHINE_CPUFUNC_H_ 45#define _MACHINE_CPUFUNC_H_ 46 47#ifdef _KERNEL 48 49#include <sys/types.h> --- 49 unchanged lines hidden (view full) --- 99 * Invalidate I-cache range 100 * 101 * Note that the ARM term for "write-back" is "clean". We use 102 * the term "write-back" since it's a more common way to describe 103 * the operation. 104 * 105 * There are some rules that must be followed: 106 * | 42 */ 43 44#ifndef _MACHINE_CPUFUNC_H_ 45#define _MACHINE_CPUFUNC_H_ 46 47#ifdef _KERNEL 48 49#include <sys/types.h> --- 49 unchanged lines hidden (view full) --- 99 * Invalidate I-cache range 100 * 101 * Note that the ARM term for "write-back" is "clean". We use 102 * the term "write-back" since it's a more common way to describe 103 * the operation. 104 * 105 * There are some rules that must be followed: 106 * |
| 107 * ID-cache Invalidate All: 108 * Unlike other functions, this one must never write back. 109 * It is used to intialize the MMU when it is in an unknown 110 * state (such as when it may have lines tagged as valid 111 * that belong to a previous set of mappings). 112 * |
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| 107 * I-cache Synch (all or range): 108 * The goal is to synchronize the instruction stream, 109 * so you may beed to write-back dirty D-cache blocks 110 * first. If a range is requested, and you can't 111 * synchronize just a range, you have to hit the whole 112 * thing. 113 * 114 * D-cache Write-Back and Invalidate range: --- 18 unchanged lines hidden (view full) --- 133 void (*cf_icache_sync_all) (void); 134 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 135 136 void (*cf_dcache_wbinv_all) (void); 137 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 138 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 139 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 140 | 113 * I-cache Synch (all or range): 114 * The goal is to synchronize the instruction stream, 115 * so you may beed to write-back dirty D-cache blocks 116 * first. If a range is requested, and you can't 117 * synchronize just a range, you have to hit the whole 118 * thing. 119 * 120 * D-cache Write-Back and Invalidate range: --- 18 unchanged lines hidden (view full) --- 139 void (*cf_icache_sync_all) (void); 140 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 141 142 void (*cf_dcache_wbinv_all) (void); 143 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 144 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 145 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 146 |
| 147 void (*cf_idcache_inv_all) (void); |
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| 141 void (*cf_idcache_wbinv_all) (void); 142 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 143 void (*cf_l2cache_wbinv_all) (void); 144 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 145 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 146 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 147 148 /* Other functions */ --- 84 unchanged lines hidden (view full) --- 233#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 234#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 235 236#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 237#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 238#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 239#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 240 | 148 void (*cf_idcache_wbinv_all) (void); 149 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 150 void (*cf_l2cache_wbinv_all) (void); 151 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 152 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 153 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 154 155 /* Other functions */ --- 84 unchanged lines hidden (view full) --- 240#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 241#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 242 243#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 244#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 245#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 246#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 247 |
| 248#define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() |
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| 241#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 242#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 243#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 244#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 245#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 246#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 247 248#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() --- 241 unchanged lines hidden (view full) --- 490void armv6_icache_sync_all (void); 491void armv6_icache_sync_range (vm_offset_t, vm_size_t); 492 493void armv6_dcache_wbinv_all (void); 494void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); 495void armv6_dcache_inv_range (vm_offset_t, vm_size_t); 496void armv6_dcache_wb_range (vm_offset_t, vm_size_t); 497 | 249#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 250#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 251#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 252#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 253#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 254#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 255 256#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() --- 241 unchanged lines hidden (view full) --- 498void armv6_icache_sync_all (void); 499void armv6_icache_sync_range (vm_offset_t, vm_size_t); 500 501void armv6_dcache_wbinv_all (void); 502void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); 503void armv6_dcache_inv_range (vm_offset_t, vm_size_t); 504void armv6_dcache_wb_range (vm_offset_t, vm_size_t); 505 |
| 506void armv6_idcache_inv_all (void); |
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| 498void armv6_idcache_wbinv_all (void); 499void armv6_idcache_wbinv_range (vm_offset_t, vm_size_t); 500 501void armv7_setttb (u_int); 502void armv7_tlb_flushID (void); 503void armv7_tlb_flushID_SE (u_int); 504void armv7_icache_sync_range (vm_offset_t, vm_size_t); 505void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); | 507void armv6_idcache_wbinv_all (void); 508void armv6_idcache_wbinv_range (vm_offset_t, vm_size_t); 509 510void armv7_setttb (u_int); 511void armv7_tlb_flushID (void); 512void armv7_tlb_flushID_SE (u_int); 513void armv7_icache_sync_range (vm_offset_t, vm_size_t); 514void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); |
| 515void armv7_idcache_inv_all (void); |
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| 506void armv7_dcache_wbinv_all (void); 507void armv7_idcache_wbinv_all (void); 508void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); 509void armv7_dcache_inv_range (vm_offset_t, vm_size_t); 510void armv7_dcache_wb_range (vm_offset_t, vm_size_t); 511void armv7_cpu_sleep (int); 512void armv7_setup (char *string); 513void armv7_context_switch (void); --- 68 unchanged lines hidden (view full) --- 582 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 583 584void armv4_tlb_flushID (void); 585void armv4_tlb_flushI (void); 586void armv4_tlb_flushD (void); 587void armv4_tlb_flushD_SE (u_int va); 588 589void armv4_drain_writebuf (void); | 516void armv7_dcache_wbinv_all (void); 517void armv7_idcache_wbinv_all (void); 518void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); 519void armv7_dcache_inv_range (vm_offset_t, vm_size_t); 520void armv7_dcache_wb_range (vm_offset_t, vm_size_t); 521void armv7_cpu_sleep (int); 522void armv7_setup (char *string); 523void armv7_context_switch (void); --- 68 unchanged lines hidden (view full) --- 592 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 593 594void armv4_tlb_flushID (void); 595void armv4_tlb_flushI (void); 596void armv4_tlb_flushD (void); 597void armv4_tlb_flushD_SE (u_int va); 598 599void armv4_drain_writebuf (void); |
| 600void armv4_idcache_inv_all (void); |
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| 590#endif 591 592#if defined(CPU_IXP12X0) 593void ixp12x0_drain_readbuf (void); 594void ixp12x0_context_switch (void); 595void ixp12x0_setup (char *string); 596#endif 597 --- 174 unchanged lines hidden --- | 601#endif 602 603#if defined(CPU_IXP12X0) 604void ixp12x0_drain_readbuf (void); 605void ixp12x0_context_switch (void); 606void ixp12x0_setup (char *string); 607#endif 608 --- 174 unchanged lines hidden --- |