| cpufunc.h (256281) | cpufunc.h (266046) |
|---|---|
| 1/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3/*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 24 unchanged lines hidden (view full) --- 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * | 1/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3/*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 24 unchanged lines hidden (view full) --- 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * |
| 41 * $FreeBSD: stable/10/sys/arm/include/cpufunc.h 244480 2012-12-20 04:32:02Z gonzo $ | 41 * $FreeBSD: stable/10/sys/arm/include/cpufunc.h 266046 2014-05-14 16:32:27Z ian $ |
| 42 */ 43 44#ifndef _MACHINE_CPUFUNC_H_ 45#define _MACHINE_CPUFUNC_H_ 46 47#ifdef _KERNEL 48 49#include <sys/types.h> --- 133 unchanged lines hidden (view full) --- 183#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 184#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 185#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 186#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 187 188#else 189void tlb_broadcast(int); 190 | 42 */ 43 44#ifndef _MACHINE_CPUFUNC_H_ 45#define _MACHINE_CPUFUNC_H_ 46 47#ifdef _KERNEL 48 49#include <sys/types.h> --- 133 unchanged lines hidden (view full) --- 183#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 184#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 185#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 186#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 187 188#else 189void tlb_broadcast(int); 190 |
| 191#ifdef CPU_CORTEXA | 191#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) |
| 192#define TLB_BROADCAST /* No need to explicitely send an IPI */ 193#else 194#define TLB_BROADCAST tlb_broadcast(7) 195#endif 196 197#define cpu_tlb_flushID() do { \ 198 cpufuncs.cf_tlb_flushID(); \ 199 TLB_BROADCAST; \ --- 277 unchanged lines hidden (view full) --- 477void arm11_tlb_flushI (void); 478void arm11_tlb_flushD (void); 479void arm11_tlb_flushD_SE (u_int va); 480 481void arm11_drain_writebuf (void); 482 483void pj4b_setttb (u_int); 484 | 192#define TLB_BROADCAST /* No need to explicitely send an IPI */ 193#else 194#define TLB_BROADCAST tlb_broadcast(7) 195#endif 196 197#define cpu_tlb_flushID() do { \ 198 cpufuncs.cf_tlb_flushID(); \ 199 TLB_BROADCAST; \ --- 277 unchanged lines hidden (view full) --- 477void arm11_tlb_flushI (void); 478void arm11_tlb_flushD (void); 479void arm11_tlb_flushD_SE (u_int va); 480 481void arm11_drain_writebuf (void); 482 483void pj4b_setttb (u_int); 484 |
| 485void pj4b_icache_sync_range (vm_offset_t, vm_size_t); 486 487void pj4b_dcache_wbinv_range (vm_offset_t, vm_size_t); 488void pj4b_dcache_inv_range (vm_offset_t, vm_size_t); 489void pj4b_dcache_wb_range (vm_offset_t, vm_size_t); 490 491void pj4b_idcache_wbinv_range (vm_offset_t, vm_size_t); 492 | |
| 493void pj4b_drain_readbuf (void); 494void pj4b_flush_brnchtgt_all (void); 495void pj4b_flush_brnchtgt_va (u_int); 496void pj4b_sleep (int); 497 498void armv6_icache_sync_all (void); 499void armv6_icache_sync_range (vm_offset_t, vm_size_t); 500 --- 17 unchanged lines hidden (view full) --- 518void armv7_dcache_wb_range (vm_offset_t, vm_size_t); 519void armv7_cpu_sleep (int); 520void armv7_setup (char *string); 521void armv7_context_switch (void); 522void armv7_drain_writebuf (void); 523void armv7_sev (void); 524u_int armv7_auxctrl (u_int, u_int); 525void pj4bv7_setup (char *string); | 485void pj4b_drain_readbuf (void); 486void pj4b_flush_brnchtgt_all (void); 487void pj4b_flush_brnchtgt_va (u_int); 488void pj4b_sleep (int); 489 490void armv6_icache_sync_all (void); 491void armv6_icache_sync_range (vm_offset_t, vm_size_t); 492 --- 17 unchanged lines hidden (view full) --- 510void armv7_dcache_wb_range (vm_offset_t, vm_size_t); 511void armv7_cpu_sleep (int); 512void armv7_setup (char *string); 513void armv7_context_switch (void); 514void armv7_drain_writebuf (void); 515void armv7_sev (void); 516u_int armv7_auxctrl (u_int, u_int); 517void pj4bv7_setup (char *string); |
| 526void pj4bv6_setup (char *string); | |
| 527void pj4b_config (void); 528 529int get_core_id (void); 530 531void armadaxp_idcache_wbinv_all (void); 532 533void cortexa_setup (char *); 534#endif --- 246 unchanged lines hidden --- | 518void pj4b_config (void); 519 520int get_core_id (void); 521 522void armadaxp_idcache_wbinv_all (void); 523 524void cortexa_setup (char *); 525#endif --- 246 unchanged lines hidden --- |