| armreg.h (266341) | armreg.h (278613) |
|---|---|
| 1/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * --- 21 unchanged lines hidden (view full) --- 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * | 1/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * --- 21 unchanged lines hidden (view full) --- 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * |
| 38 * $FreeBSD: stable/10/sys/arm/include/armreg.h 266341 2014-05-17 19:37:04Z ian $ | 38 * $FreeBSD: stable/10/sys/arm/include/armreg.h 278613 2015-02-12 03:50:33Z ian $ |
| 39 */ 40 41#ifndef MACHINE_ARMREG_H 42#define MACHINE_ARMREG_H 43 44#define INSN_SIZE 4 45#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 46#define PSR_MODE 0x0000001f /* mode mask */ | 39 */ 40 41#ifndef MACHINE_ARMREG_H 42#define MACHINE_ARMREG_H 43 44#define INSN_SIZE 4 45#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 46#define PSR_MODE 0x0000001f /* mode mask */ |
| 47#define PSR_USR26_MODE 0x00000000 48#define PSR_FIQ26_MODE 0x00000001 49#define PSR_IRQ26_MODE 0x00000002 50#define PSR_SVC26_MODE 0x00000003 | |
| 51#define PSR_USR32_MODE 0x00000010 52#define PSR_FIQ32_MODE 0x00000011 53#define PSR_IRQ32_MODE 0x00000012 54#define PSR_SVC32_MODE 0x00000013 | 47#define PSR_USR32_MODE 0x00000010 48#define PSR_FIQ32_MODE 0x00000011 49#define PSR_IRQ32_MODE 0x00000012 50#define PSR_SVC32_MODE 0x00000013 |
| 51#define PSR_MON32_MODE 0x00000016 |
|
| 55#define PSR_ABT32_MODE 0x00000017 | 52#define PSR_ABT32_MODE 0x00000017 |
| 53#define PSR_HYP32_MODE 0x0000001a |
|
| 56#define PSR_UND32_MODE 0x0000001b 57#define PSR_SYS32_MODE 0x0000001f 58#define PSR_32_MODE 0x00000010 | 54#define PSR_UND32_MODE 0x0000001b 55#define PSR_SYS32_MODE 0x0000001f 56#define PSR_32_MODE 0x00000010 |
| 59#define PSR_FLAGS 0xf0000000 /* flags */ | 57#define PSR_T 0x00000020 /* Instruction set bit */ 58#define PSR_F 0x00000040 /* FIQ disable bit */ 59#define PSR_I 0x00000080 /* IRQ disable bit */ 60#define PSR_A 0x00000100 /* Imprecise abort bit */ 61#define PSR_E 0x00000200 /* Data endianess bit */ 62#define PSR_GE 0x000f0000 /* Greater than or equal to bits */ 63#define PSR_J 0x01000000 /* Java bit */ 64#define PSR_Q 0x08000000 /* Sticky overflow bit */ 65#define PSR_V 0x10000000 /* Overflow bit */ 66#define PSR_C 0x20000000 /* Carry bit */ 67#define PSR_Z 0x40000000 /* Zero bit */ 68#define PSR_N 0x80000000 /* Negative bit */ 69#define PSR_FLAGS 0xf0000000 /* Flags mask. */ |
| 60 | 70 |
| 61#define PSR_C_bit (1 << 29) /* carry */ 62 | |
| 63/* The high-order byte is always the implementor */ 64#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 65#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 66#define CPU_ID_DEC 0x44000000 /* 'D' */ 67#define CPU_ID_INTEL 0x69000000 /* 'i' */ 68#define CPU_ID_TI 0x54000000 /* 'T' */ 69#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 70 --- 159 unchanged lines hidden (view full) --- 230#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 231#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 232#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 233#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 234#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 235#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 236#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 237#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ | 71/* The high-order byte is always the implementor */ 72#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 73#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 74#define CPU_ID_DEC 0x44000000 /* 'D' */ 75#define CPU_ID_INTEL 0x69000000 /* 'i' */ 76#define CPU_ID_TI 0x54000000 /* 'T' */ 77#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 78 --- 159 unchanged lines hidden (view full) --- 238#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 239#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 240#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 241#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 242#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 243#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 244#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 245#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ |
| 246#define CPU_CONTROL_SW_ENABLE 0x00000400 /* SW: SWP instruction enable */ |
|
| 238#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 239#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 240#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 241#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 242#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ | 247#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 248#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 249#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 250#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 251#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ |
| 252#define CPU_CONTROL_HAF_ENABLE 0x00020000 /* HA: Hardware Access Flag Enable */ |
|
| 243#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 244#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 245#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ | 253#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 254#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 255#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ |
| 256#define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ 257#define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ |
|
| 246#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ | 258#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ |
| 247#define CPU_CONTROL_AF_ENABLE 0x20000000 /* Access Flag enable */ | 259#define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ 260#define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: TEX Remap*/ 261#define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access Flag enable */ 262#define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ |
| 248 249#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 250 251/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 252#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 253#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 254#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 255#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ --- 100 unchanged lines hidden (view full) --- 356#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 357#define FAULT_PERM_S 0x0d /* Permission -- Section */ 358#define FAULT_PERM_P 0x0f /* Permission -- Page */ 359 360#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 361#define FAULT_EXTERNAL 0x400 /* External abort (armv6+) */ 362#define FAULT_WNR 0x800 /* Write-not-Read access (armv6+) */ 363 | 263 264#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 265 266/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 267#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 268#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 269#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 270#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ --- 100 unchanged lines hidden (view full) --- 371#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 372#define FAULT_PERM_S 0x0d /* Permission -- Section */ 373#define FAULT_PERM_P 0x0f /* Permission -- Page */ 374 375#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 376#define FAULT_EXTERNAL 0x400 /* External abort (armv6+) */ 377#define FAULT_WNR 0x800 /* Write-not-Read access (armv6+) */ 378 |
| 379/* Fault status register definitions - v6+ */ 380#define FSR_STATUS_TO_IDX(fsr) (((fsr) & 0xF) | \ 381 (((fsr) & (1 << 10)>> (10 - 4)))) 382#define FSR_LPAE (1 << 9) /* LPAE indicator */ 383#define FSR_WNR (1 << 11) /* Write-not-Read access */ 384#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/ 385#define FSR_CM (1 << 13) /* Cache maintenance fault */ 386 387 |
|
| 364/* 365 * Address of the vector page, low and high versions. 366 */ 367#ifndef __ASSEMBLER__ 368#define ARM_VECTORS_LOW 0x00000000U 369#define ARM_VECTORS_HIGH 0xffff0000U 370#else 371#define ARM_VECTORS_LOW 0 --- 21 unchanged lines hidden --- | 388/* 389 * Address of the vector page, low and high versions. 390 */ 391#ifndef __ASSEMBLER__ 392#define ARM_VECTORS_LOW 0x00000000U 393#define ARM_VECTORS_HIGH 0xffff0000U 394#else 395#define ARM_VECTORS_LOW 0 --- 21 unchanged lines hidden --- |