| vf_ccm.c (266152) | vf_ccm.c (266203) |
|---|---|
| 1/*- 2 * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 16 unchanged lines hidden (view full) --- 25 */ 26 27/* 28 * Vybrid Family Clock Controller Module (CCM) 29 * Chapter 10, Vybrid Reference Manual, Rev. 5, 07/2013 30 */ 31 32#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 16 unchanged lines hidden (view full) --- 25 */ 26 27/* 28 * Vybrid Family Clock Controller Module (CCM) 29 * Chapter 10, Vybrid Reference Manual, Rev. 5, 07/2013 30 */ 31 32#include <sys/cdefs.h> |
| 33__FBSDID("$FreeBSD: stable/10/sys/arm/freescale/vybrid/vf_ccm.c 266152 2014-05-15 16:11:06Z ian $"); | 33__FBSDID("$FreeBSD: stable/10/sys/arm/freescale/vybrid/vf_ccm.c 266203 2014-05-16 00:14:50Z ian $"); |
| 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/kernel.h> 39#include <sys/module.h> 40#include <sys/malloc.h> 41#include <sys/rman.h> --- 117 unchanged lines hidden (view full) --- 159 uint32_t div_shift; 160 uint32_t div_val; 161 uint32_t sel_reg; 162 uint32_t sel_mask; 163 uint32_t sel_shift; 164 uint32_t sel_val; 165}; 166 | 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/kernel.h> 39#include <sys/module.h> 40#include <sys/malloc.h> 41#include <sys/rman.h> --- 117 unchanged lines hidden (view full) --- 159 uint32_t div_shift; 160 uint32_t div_val; 161 uint32_t sel_reg; 162 uint32_t sel_mask; 163 uint32_t sel_shift; 164 uint32_t sel_val; 165}; 166 |
| 167static struct clk ipg_clk = { 168 .reg = CCM_CACRR, 169 .enable_reg = 0, 170 .div_mask = IPG_CLK_DIV_MASK, 171 .div_shift = IPG_CLK_DIV_SHIFT, 172 .div_val = 1, /* Divide by 2 */ 173 .sel_reg = 0, 174 .sel_mask = 0, 175 .sel_shift = 0, 176 .sel_val = 0, 177}; 178 |
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| 167/* 168 PLL4 clock divider (before switching the clocks should be gated) 169 000 Divide by 1 (only if PLL frequency less than or equal to 650 MHz) 170 001 Divide by 4 171 010 Divide by 6 172 011 Divide by 8 173 100 Divide by 10 174 101 Divide by 12 --- 130 unchanged lines hidden (view full) --- 305}; 306 307struct clock_entry { 308 char *name; 309 struct clk *clk; 310}; 311 312static struct clock_entry clock_map[] = { | 179/* 180 PLL4 clock divider (before switching the clocks should be gated) 181 000 Divide by 1 (only if PLL frequency less than or equal to 650 MHz) 182 001 Divide by 4 183 010 Divide by 6 184 011 Divide by 8 185 100 Divide by 10 186 101 Divide by 12 --- 130 unchanged lines hidden (view full) --- 317}; 318 319struct clock_entry { 320 char *name; 321 struct clk *clk; 322}; 323 324static struct clock_entry clock_map[] = { |
| 325 {"ipg", &ipg_clk}, |
|
| 313 {"pll4", &pll4_clk}, 314 {"sai3", &sai3_clk}, 315 {"cko1", &cko1_clk}, 316 {"esdhc0", &esdhc0_clk}, 317 {"esdhc1", &esdhc1_clk}, 318 {"qspi0", &qspi0_clk}, 319 {"dcu0", &dcu0_clk}, 320 {"enet", &enet_clk}, --- 168 unchanged lines hidden --- | 326 {"pll4", &pll4_clk}, 327 {"sai3", &sai3_clk}, 328 {"cko1", &cko1_clk}, 329 {"esdhc0", &esdhc0_clk}, 330 {"esdhc1", &esdhc1_clk}, 331 {"qspi0", &qspi0_clk}, 332 {"dcu0", &dcu0_clk}, 333 {"enet", &enet_clk}, --- 168 unchanged lines hidden --- |