| imx6_mp.c (262427) | imx6_mp.c (266203) |
|---|---|
| 1/*- 2 * Copyright (c) 2014 Juergen Weiss <weiss@uni-mainz.de> 3 * Copyright (c) 2014 Ian Lepore <ian@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 11 unchanged lines hidden (view full) --- 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2014 Juergen Weiss <weiss@uni-mainz.de> 3 * Copyright (c) 2014 Ian Lepore <ian@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 11 unchanged lines hidden (view full) --- 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
| 28__FBSDID("$FreeBSD: head/sys/arm/freescale/imx/imx6_mp.c 262427 2014-02-24 03:51:31Z ian $"); | 28__FBSDID("$FreeBSD: stable/10/sys/arm/freescale/imx/imx6_mp.c 266203 2014-05-16 00:14:50Z ian $"); |
| 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/bus.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/smp.h> 35 36#include <machine/smp.h> --- 71 unchanged lines hidden (view full) --- 108 int i; 109 110 if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0) 111 panic("Couldn't map the SCU\n"); 112 if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0) 113 panic("Couldn't map the system reset controller (SRC)\n"); 114 115 /* | 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/bus.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/smp.h> 35 36#include <machine/smp.h> --- 71 unchanged lines hidden (view full) --- 108 int i; 109 110 if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0) 111 panic("Couldn't map the SCU\n"); 112 if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0) 113 panic("Couldn't map the system reset controller (SRC)\n"); 114 115 /* |
| 116 * Invalidate SCU cache tags. The 0x0000fff0 constant invalidates all 117 * ways on all cores 1-3 (leaving core 0 alone). Per the ARM docs, it's 118 * harmless to write to the bits for cores that are not present. | 116 * Invalidate SCU cache tags. The 0x0000ffff constant invalidates all 117 * ways on all cores 0-3. Per the ARM docs, it's harmless to write to 118 * the bits for cores that are not present. |
| 119 */ | 119 */ |
| 120 bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000fff0); | 120 bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff); |
| 121 122 /* 123 * Erratum ARM/MP: 764369 (problems with cache maintenance). 124 * Setting the "disable-migratory bit" in the undocumented SCU 125 * Diagnostic Control Register helps work around the problem. 126 */ 127 val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL); 128 bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, 129 val | SCU_DIAG_DISABLE_MIGBIT); 130 | 121 122 /* 123 * Erratum ARM/MP: 764369 (problems with cache maintenance). 124 * Setting the "disable-migratory bit" in the undocumented SCU 125 * Diagnostic Control Register helps work around the problem. 126 */ 127 val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL); 128 bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, 129 val | SCU_DIAG_DISABLE_MIGBIT); 130 |
| 131 /* Enable the SCU. */ | 131 /* 132 * Enable the SCU, then clean the cache on this core. After these two 133 * operations the cache tag ram in the SCU is coherent with the contents 134 * of the cache on this core. The other cores aren't running yet so 135 * their caches can't contain valid data yet, but we've initialized 136 * their SCU tag ram above, so they will be coherent from startup. 137 */ |
| 132 val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG); 133 bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, 134 val | SCU_CONTROL_ENABLE); | 138 val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG); 139 bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, 140 val | SCU_CONTROL_ENABLE); |
| 135 | |
| 136 cpu_idcache_wbinv_all(); | 141 cpu_idcache_wbinv_all(); |
| 137 cpu_l2cache_wbinv_all(); | |
| 138 139 /* 140 * For each AP core, set the entry point address and argument registers, 141 * and set the core-enable and core-reset bits in the control register. 142 */ 143 val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG); 144 for (i=1; i < mp_ncpus; i++) { 145 bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i, --- 21 unchanged lines hidden --- | 142 143 /* 144 * For each AP core, set the entry point address and argument registers, 145 * and set the core-enable and core-reset bits in the control register. 146 */ 147 val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG); 148 for (i=1; i < mp_ncpus; i++) { 149 bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i, --- 21 unchanged lines hidden --- |