| at91sam9g45.c (238788) | at91sam9g45.c (239190) |
|---|---|
| 1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * Copyright (c) 2010 Greg Ansley. All rights reserved. 4 * Copyright (c) 2012 Andrew Turner. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 12 unchanged lines hidden (view full) --- 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * Copyright (c) 2010 Greg Ansley. All rights reserved. 4 * Copyright (c) 2012 Andrew Turner. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 12 unchanged lines hidden (view full) --- 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> |
| 29__FBSDID("$FreeBSD: head/sys/arm/at91/at91sam9g45.c 238788 2012-07-26 08:01:25Z andrew $"); | 29__FBSDID("$FreeBSD: head/sys/arm/at91/at91sam9g45.c 239190 2012-08-11 05:45:19Z imp $"); |
| 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/kernel.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37 --- 82 unchanged lines hidden (view full) --- 120 DEVICE("spi", SPI1, 1), 121 DEVICE("ate", EMAC, 0), 122 DEVICE("macb", EMAC, 0), 123 DEVICE("nand", NAND, 0), 124 DEVICE("ohci", OHCI, 0), 125 { 0, 0, 0, 0, 0 } 126}; 127 | 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/kernel.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37 --- 82 unchanged lines hidden (view full) --- 120 DEVICE("spi", SPI1, 1), 121 DEVICE("ate", EMAC, 0), 122 DEVICE("macb", EMAC, 0), 123 DEVICE("nand", NAND, 0), 124 DEVICE("ohci", OHCI, 0), 125 { 0, 0, 0, 0, 0 } 126}; 127 |
| 128static uint32_t 129at91_pll_outa(int freq) 130{ 131 132 switch (freq / 10000000) { 133 case 747 ... 801: return ((1 << 29) | (0 << 14)); 134 case 697 ... 746: return ((1 << 29) | (1 << 14)); 135 case 647 ... 696: return ((1 << 29) | (2 << 14)); 136 case 597 ... 646: return ((1 << 29) | (3 << 14)); 137 case 547 ... 596: return ((1 << 29) | (4 << 14)); 138 case 497 ... 546: return ((1 << 29) | (5 << 14)); 139 case 447 ... 496: return ((1 << 29) | (6 << 14)); 140 case 397 ... 446: return ((1 << 29) | (7 << 14)); 141 default: return (1 << 29); 142 } 143} 144 | |
| 145static void 146at91_clock_init(void) 147{ 148 struct at91_pmc_clock *clk; 149 150 /* Update USB host port clock info */ 151 clk = at91_pmc_clock_ref("uhpck"); 152 clk->pmc_mask = PMC_SCER_UHP_SAM9; --- 4 unchanged lines hidden (view full) --- 157 clk->pll_min_in = SAM9G45_PLL_A_MIN_IN_FREQ; /* 2 MHz */ 158 clk->pll_max_in = SAM9G45_PLL_A_MAX_IN_FREQ; /* 32 MHz */ 159 clk->pll_min_out = SAM9G45_PLL_A_MIN_OUT_FREQ; /* 400 MHz */ 160 clk->pll_max_out = SAM9G45_PLL_A_MAX_OUT_FREQ; /* 800 MHz */ 161 clk->pll_mul_shift = SAM9G45_PLL_A_MUL_SHIFT; 162 clk->pll_mul_mask = SAM9G45_PLL_A_MUL_MASK; 163 clk->pll_div_shift = SAM9G45_PLL_A_DIV_SHIFT; 164 clk->pll_div_mask = SAM9G45_PLL_A_DIV_MASK; | 128static void 129at91_clock_init(void) 130{ 131 struct at91_pmc_clock *clk; 132 133 /* Update USB host port clock info */ 134 clk = at91_pmc_clock_ref("uhpck"); 135 clk->pmc_mask = PMC_SCER_UHP_SAM9; --- 4 unchanged lines hidden (view full) --- 140 clk->pll_min_in = SAM9G45_PLL_A_MIN_IN_FREQ; /* 2 MHz */ 141 clk->pll_max_in = SAM9G45_PLL_A_MAX_IN_FREQ; /* 32 MHz */ 142 clk->pll_min_out = SAM9G45_PLL_A_MIN_OUT_FREQ; /* 400 MHz */ 143 clk->pll_max_out = SAM9G45_PLL_A_MAX_OUT_FREQ; /* 800 MHz */ 144 clk->pll_mul_shift = SAM9G45_PLL_A_MUL_SHIFT; 145 clk->pll_mul_mask = SAM9G45_PLL_A_MUL_MASK; 146 clk->pll_div_shift = SAM9G45_PLL_A_DIV_SHIFT; 147 clk->pll_div_mask = SAM9G45_PLL_A_DIV_MASK; |
| 165 clk->set_outb = at91_pll_outa; | 148 clk->set_outb = at91_pmc_800mhz_plla_outb; |
| 166 at91_pmc_clock_deref(clk); 167} 168 169static struct at91_soc_data soc_data = { 170 .soc_delay = at91_pit_delay, 171 .soc_reset = at91_rst_cpu_reset, 172 .soc_clock_init = at91_clock_init, 173 .soc_irq_prio = at91_irq_prio, 174 .soc_children = at91_devs, 175}; 176 177AT91_SOC(AT91_T_SAM9G45, &soc_data); | 149 at91_pmc_clock_deref(clk); 150} 151 152static struct at91_soc_data soc_data = { 153 .soc_delay = at91_pit_delay, 154 .soc_reset = at91_rst_cpu_reset, 155 .soc_clock_init = at91_clock_init, 156 .soc_irq_prio = at91_irq_prio, 157 .soc_children = at91_devs, 158}; 159 160AT91_SOC(AT91_T_SAM9G45, &soc_data); |