| at91sam9g20.c (238397) | at91sam9g20.c (239190) |
|---|---|
| 1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * Copyright (c) 2010 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * Copyright (c) 2010 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
| 28__FBSDID("$FreeBSD: head/sys/arm/at91/at91sam9g20.c 238397 2012-07-12 13:45:58Z imp $"); | 28__FBSDID("$FreeBSD: head/sys/arm/at91/at91sam9g20.c 239190 2012-08-11 05:45:19Z imp $"); |
| 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/malloc.h> 35#include <sys/module.h> 36 --- 80 unchanged lines hidden (view full) --- 117 DEVICE("spi", SPI1, 1), 118 DEVICE("ate", EMAC, 0), 119 DEVICE("macb", EMAC, 0), 120 DEVICE("nand", NAND, 0), 121 DEVICE("ohci", OHCI, 0), 122 { 0, 0, 0, 0, 0 } 123}; 124 | 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/malloc.h> 35#include <sys/module.h> 36 --- 80 unchanged lines hidden (view full) --- 117 DEVICE("spi", SPI1, 1), 118 DEVICE("ate", EMAC, 0), 119 DEVICE("macb", EMAC, 0), 120 DEVICE("nand", NAND, 0), 121 DEVICE("ohci", OHCI, 0), 122 { 0, 0, 0, 0, 0 } 123}; 124 |
| 125static uint32_t 126at91_pll_outa(int freq) 127{ 128 129 switch (freq / 10000000) { 130 case 747 ... 801: return ((1 << 29) | (0 << 14)); 131 case 697 ... 746: return ((1 << 29) | (1 << 14)); 132 case 647 ... 696: return ((1 << 29) | (2 << 14)); 133 case 597 ... 646: return ((1 << 29) | (3 << 14)); 134 case 547 ... 596: return ((1 << 29) | (1 << 14)); 135 case 497 ... 546: return ((1 << 29) | (2 << 14)); 136 case 447 ... 496: return ((1 << 29) | (3 << 14)); 137 case 397 ... 446: return ((1 << 29) | (4 << 14)); 138 default: return (1 << 29); 139 } 140} 141 142static uint32_t 143at91_pll_outb(int freq) 144{ 145 146 return (0); 147} 148 | |
| 149static void 150at91_clock_init(void) 151{ 152 struct at91_pmc_clock *clk; 153 154 /* Update USB device port clock info */ 155 clk = at91_pmc_clock_ref("udpck"); 156 clk->pmc_mask = PMC_SCER_UDP_SAM9; --- 9 unchanged lines hidden (view full) --- 166 clk->pll_min_in = SAM9G20_PLL_A_MIN_IN_FREQ; /* 2 MHz */ 167 clk->pll_max_in = SAM9G20_PLL_A_MAX_IN_FREQ; /* 32 MHz */ 168 clk->pll_min_out = SAM9G20_PLL_A_MIN_OUT_FREQ; /* 400 MHz */ 169 clk->pll_max_out = SAM9G20_PLL_A_MAX_OUT_FREQ; /* 800 MHz */ 170 clk->pll_mul_shift = SAM9G20_PLL_A_MUL_SHIFT; 171 clk->pll_mul_mask = SAM9G20_PLL_A_MUL_MASK; 172 clk->pll_div_shift = SAM9G20_PLL_A_DIV_SHIFT; 173 clk->pll_div_mask = SAM9G20_PLL_A_DIV_MASK; | 125static void 126at91_clock_init(void) 127{ 128 struct at91_pmc_clock *clk; 129 130 /* Update USB device port clock info */ 131 clk = at91_pmc_clock_ref("udpck"); 132 clk->pmc_mask = PMC_SCER_UDP_SAM9; --- 9 unchanged lines hidden (view full) --- 142 clk->pll_min_in = SAM9G20_PLL_A_MIN_IN_FREQ; /* 2 MHz */ 143 clk->pll_max_in = SAM9G20_PLL_A_MAX_IN_FREQ; /* 32 MHz */ 144 clk->pll_min_out = SAM9G20_PLL_A_MIN_OUT_FREQ; /* 400 MHz */ 145 clk->pll_max_out = SAM9G20_PLL_A_MAX_OUT_FREQ; /* 800 MHz */ 146 clk->pll_mul_shift = SAM9G20_PLL_A_MUL_SHIFT; 147 clk->pll_mul_mask = SAM9G20_PLL_A_MUL_MASK; 148 clk->pll_div_shift = SAM9G20_PLL_A_DIV_SHIFT; 149 clk->pll_div_mask = SAM9G20_PLL_A_DIV_MASK; |
| 174 clk->set_outb = at91_pll_outa; | 150 clk->set_outb = at91_pmc_800mhz_plla_outb; |
| 175 at91_pmc_clock_deref(clk); 176 177 clk = at91_pmc_clock_ref("pllb"); 178 clk->pll_min_in = SAM9G20_PLL_B_MIN_IN_FREQ; /* 2 MHz */ 179 clk->pll_max_in = SAM9G20_PLL_B_MAX_IN_FREQ; /* 32 MHz */ 180 clk->pll_min_out = SAM9G20_PLL_B_MIN_OUT_FREQ; /* 30 MHz */ 181 clk->pll_max_out = SAM9G20_PLL_B_MAX_OUT_FREQ; /* 100 MHz */ 182 clk->pll_mul_shift = SAM9G20_PLL_B_MUL_SHIFT; 183 clk->pll_mul_mask = SAM9G20_PLL_B_MUL_MASK; 184 clk->pll_div_shift = SAM9G20_PLL_B_DIV_SHIFT; 185 clk->pll_div_mask = SAM9G20_PLL_B_DIV_MASK; | 151 at91_pmc_clock_deref(clk); 152 153 clk = at91_pmc_clock_ref("pllb"); 154 clk->pll_min_in = SAM9G20_PLL_B_MIN_IN_FREQ; /* 2 MHz */ 155 clk->pll_max_in = SAM9G20_PLL_B_MAX_IN_FREQ; /* 32 MHz */ 156 clk->pll_min_out = SAM9G20_PLL_B_MIN_OUT_FREQ; /* 30 MHz */ 157 clk->pll_max_out = SAM9G20_PLL_B_MAX_OUT_FREQ; /* 100 MHz */ 158 clk->pll_mul_shift = SAM9G20_PLL_B_MUL_SHIFT; 159 clk->pll_mul_mask = SAM9G20_PLL_B_MUL_MASK; 160 clk->pll_div_shift = SAM9G20_PLL_B_DIV_SHIFT; 161 clk->pll_div_mask = SAM9G20_PLL_B_DIV_MASK; |
| 186 clk->set_outb = at91_pll_outb; | 162 clk->set_outb = at91_pmc_800mhz_pllb_outb; |
| 187 at91_pmc_clock_deref(clk); 188} 189 190static struct at91_soc_data soc_data = { 191 .soc_delay = at91_pit_delay, 192 .soc_reset = at91_rst_cpu_reset, 193 .soc_clock_init = at91_clock_init, 194 .soc_irq_prio = at91_irq_prio, 195 .soc_children = at91_devs, 196}; 197 198AT91_SOC(AT91_T_SAM9G20, &soc_data); | 163 at91_pmc_clock_deref(clk); 164} 165 166static struct at91_soc_data soc_data = { 167 .soc_delay = at91_pit_delay, 168 .soc_reset = at91_rst_cpu_reset, 169 .soc_clock_init = at91_clock_init, 170 .soc_irq_prio = at91_irq_prio, 171 .soc_children = at91_devs, 172}; 173 174AT91_SOC(AT91_T_SAM9G20, &soc_data); |