| at91sam9g20.c (238376) | at91sam9g20.c (238389) |
|---|---|
| 1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * Copyright (c) 2010 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * Copyright (c) 2010 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
| 28__FBSDID("$FreeBSD: head/sys/arm/at91/at91sam9g20.c 238376 2012-07-11 20:17:14Z imp $"); | 28__FBSDID("$FreeBSD: head/sys/arm/at91/at91sam9g20.c 238389 2012-07-12 02:58:45Z imp $"); |
| 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/malloc.h> 35#include <sys/module.h> 36 --- 9 unchanged lines hidden (view full) --- 46#include <arm/at91/at91_pmcreg.h> 47#include <arm/at91/at91_pmcvar.h> 48#include <arm/at91/at91_rstreg.h> 49 50struct at91sam9_softc { 51 device_t dev; 52 bus_space_tag_t sc_st; 53 bus_space_handle_t sc_sh; | 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/malloc.h> 35#include <sys/module.h> 36 --- 9 unchanged lines hidden (view full) --- 46#include <arm/at91/at91_pmcreg.h> 47#include <arm/at91/at91_pmcvar.h> 48#include <arm/at91/at91_rstreg.h> 49 50struct at91sam9_softc { 51 device_t dev; 52 bus_space_tag_t sc_st; 53 bus_space_handle_t sc_sh; |
| 54 bus_space_handle_t sc_sys_sh; 55 bus_space_handle_t sc_aic_sh; | |
| 56 bus_space_handle_t sc_matrix_sh; 57}; 58 59/* 60 * Standard priority levels for the system. 0 is lowest and 7 is highest. 61 * These values are the ones Atmel uses for its Linux port 62 */ 63static const int at91_irq_prio[32] = --- 122 unchanged lines hidden (view full) --- 186 return (0); 187} 188 189static int 190at91_attach(device_t dev) 191{ 192 struct at91_pmc_clock *clk; 193 struct at91sam9_softc *sc = device_get_softc(dev); | 54 bus_space_handle_t sc_matrix_sh; 55}; 56 57/* 58 * Standard priority levels for the system. 0 is lowest and 7 is highest. 59 * These values are the ones Atmel uses for its Linux port 60 */ 61static const int at91_irq_prio[32] = --- 122 unchanged lines hidden (view full) --- 184 return (0); 185} 186 187static int 188at91_attach(device_t dev) 189{ 190 struct at91_pmc_clock *clk; 191 struct at91sam9_softc *sc = device_get_softc(dev); |
| 194 int i; 195 | |
| 196 struct at91_softc *at91sc = device_get_softc(device_get_parent(dev)); | 192 struct at91_softc *at91sc = device_get_softc(device_get_parent(dev)); |
| 193 uint32_t i; |
|
| 197 198 sc->sc_st = at91sc->sc_st; 199 sc->sc_sh = at91sc->sc_sh; 200 sc->dev = dev; 201 | 194 195 sc->sc_st = at91sc->sc_st; 196 sc->sc_sh = at91sc->sc_sh; 197 sc->dev = dev; 198 |
| 202 /* 203 * XXX These values work for the RM9200, SAM926[01], and SAM9G20 204 * will have to fix this when we want to support anything else. XXX 205 */ 206 if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9G20_SYS_BASE, 207 AT91SAM9G20_SYS_SIZE, &sc->sc_sys_sh) != 0) 208 panic("Enable to map system registers"); 209 210 if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9G20_AIC_BASE, 211 AT91SAM9G20_AIC_SIZE, &sc->sc_aic_sh) != 0) 212 panic("Enable to map system registers"); 213 214 /* XXX Hack to tell atmelarm about the AIC */ 215 at91sc->sc_aic_sh = sc->sc_aic_sh; 216 217 for (i = 0; i < 32; i++) { 218 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR + 219 i * 4, i); 220 /* Priority. */ 221 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4, 222 at91_irq_prio[i]); 223 if (i < 8) 224 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_EOICR, 225 1); 226 } 227 228 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SPU, 32); 229 /* No debug. */ 230 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_DCR, 0); 231 /* Disable and clear all interrupts. */ 232 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff); 233 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff); 234 | |
| 235 if (bus_space_subregion(sc->sc_st, sc->sc_sh, 236 AT91SAM9G20_MATRIX_BASE, AT91SAM9G20_MATRIX_SIZE, 237 &sc->sc_matrix_sh) != 0) 238 panic("Enable to map matrix registers"); 239 240 /* activate NAND*/ 241 i = bus_space_read_4(sc->sc_st, sc->sc_matrix_sh, 242 AT91SAM9G20_EBICSA); --- 53 unchanged lines hidden (view full) --- 296}; 297 298static devclass_t at91sam9_devclass; 299 300DRIVER_MODULE(at91sam, atmelarm, at91sam9_driver, at91sam9_devclass, 0, 0); 301 302static struct at91_soc_data soc_data = { 303 .soc_delay = at91_pit_delay, | 199 if (bus_space_subregion(sc->sc_st, sc->sc_sh, 200 AT91SAM9G20_MATRIX_BASE, AT91SAM9G20_MATRIX_SIZE, 201 &sc->sc_matrix_sh) != 0) 202 panic("Enable to map matrix registers"); 203 204 /* activate NAND*/ 205 i = bus_space_read_4(sc->sc_st, sc->sc_matrix_sh, 206 AT91SAM9G20_EBICSA); --- 53 unchanged lines hidden (view full) --- 260}; 261 262static devclass_t at91sam9_devclass; 263 264DRIVER_MODULE(at91sam, atmelarm, at91sam9_driver, at91sam9_devclass, 0, 0); 265 266static struct at91_soc_data soc_data = { 267 .soc_delay = at91_pit_delay, |
| 304 .soc_reset = at91_rst_cpu_reset | 268 .soc_reset = at91_rst_cpu_reset, 269 .soc_irq_prio = at91_irq_prio, |
| 305}; 306 307AT91_SOC(AT91_T_SAM9G20, &soc_data); | 270}; 271 272AT91_SOC(AT91_T_SAM9G20, &soc_data); |