| at91rm92reg.h (155324) | at91rm92reg.h (156829) |
|---|---|
| 1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 8 unchanged lines hidden (view full) --- 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 | 1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 8 unchanged lines hidden (view full) --- 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 |
| 25/* $FreeBSD: head/sys/arm/at91/at91rm92reg.h 155324 2006-02-04 23:32:13Z imp $ */ | 25/* $FreeBSD: head/sys/arm/at91/at91rm92reg.h 156829 2006-03-18 01:38:25Z imp $ */ |
| 26 27#ifndef AT91RM92REG_H_ 28#define AT91RM92REG_H_ 29/* 30 * Memory map, from datasheet : 31 * 0x00000000 - 0x0ffffffff : Internal Memories 32 * 0x10000000 - 0x1ffffffff : Chip Select 0 33 * 0x20000000 - 0x2ffffffff : Chip Select 1 --- 164 unchanged lines hidden (view full) --- 198#define PIOD_PPUSR (0xa00 + 104) /* Pad pull-up status register */ 199#define PIOD_ASR (0xa00 + 112) /* Select A register */ 200#define PIOD_BSR (0xa00 + 116) /* Select B register */ 201#define PIOD_ABSR (0xa00 + 120) /* AB Select status register */ 202#define PIOD_OWER (0xa00 + 160) /* Output Write enable register */ 203#define PIOD_OWDR (0xa00 + 164) /* Output write disable register */ 204#define PIOD_OWSR (0xa00 + 168) /* Output write status register */ 205 | 26 27#ifndef AT91RM92REG_H_ 28#define AT91RM92REG_H_ 29/* 30 * Memory map, from datasheet : 31 * 0x00000000 - 0x0ffffffff : Internal Memories 32 * 0x10000000 - 0x1ffffffff : Chip Select 0 33 * 0x20000000 - 0x2ffffffff : Chip Select 1 --- 164 unchanged lines hidden (view full) --- 198#define PIOD_PPUSR (0xa00 + 104) /* Pad pull-up status register */ 199#define PIOD_ASR (0xa00 + 112) /* Select A register */ 200#define PIOD_BSR (0xa00 + 116) /* Select B register */ 201#define PIOD_ABSR (0xa00 + 120) /* AB Select status register */ 202#define PIOD_OWER (0xa00 + 160) /* Output Write enable register */ 203#define PIOD_OWDR (0xa00 + 164) /* Output write disable register */ 204#define PIOD_OWSR (0xa00 + 168) /* Output write status register */ 205 |
| 206/* 207 * PIO 208 */ 209#define AT91RM92_PIOA_BASE 0xffff400 210#define AT91RM92_PIO_SIZE 0x200 211#define AT91RM92_PIOB_BASE 0xffff600 212#define AT91RM92_PIOC_BASE 0xffff800 213#define AT91RM92_PIOD_BASE 0xffffa00 214 215/* 216 * PMC 217 */ 218#define AT91RM92_PMC_BASE 0xffffc00 219#define AT91RM92_PMC_SIZE 0x100 220 |
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| 206/* IRQs : */ 207/* 208 * 0: AIC 209 * 1: System peripheral (System timer, RTC, DBGU) 210 * 2: PIO Controller A 211 * 3: PIO Controller B 212 * 4: PIO Controller C 213 * 5: PIO Controller D --- 48 unchanged lines hidden (view full) --- 262#define AT91RM92_IRQ_TC4 21 263#define AT91RM92_IRQ_TC5 22 264#define AT91RM92_IRQ_UHP 23 265#define AT91RM92_IRQ_EMAC 24 266#define AT91RM92_IRQ_AIC_BASE 25 267 268/* Timer */ 269 | 221/* IRQs : */ 222/* 223 * 0: AIC 224 * 1: System peripheral (System timer, RTC, DBGU) 225 * 2: PIO Controller A 226 * 3: PIO Controller B 227 * 4: PIO Controller C 228 * 5: PIO Controller D --- 48 unchanged lines hidden (view full) --- 277#define AT91RM92_IRQ_TC4 21 278#define AT91RM92_IRQ_TC5 22 279#define AT91RM92_IRQ_UHP 23 280#define AT91RM92_IRQ_EMAC 24 281#define AT91RM92_IRQ_AIC_BASE 25 282 283/* Timer */ 284 |
| 285#define AT91RM92_AIC_BASE 0xffff000 286#define AT91RM92_AIC_SIZE 0x200 287 288#define AT91RM92_DBGU_BASE 0xffff200 289#define AT91RM92_DBGU_SIZE 0x200 290 291#define AT91RM92_RTC_BASE 0xffffe00 292#define AT91RM92_RTC_SIZE 0x100 293 294#define AT91RM92_MC_BASE 0xfffff00 295#define AT91RM92_MC_SIZE 0x100 296 |
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| 270#define AT91RM92_ST_BASE 0xffffd00 271#define AT91RM92_ST_SIZE 0x100 272 273#define AT91RM92_SPI_BASE 0xffe0000 274#define AT91RM92_SPI_SIZE 0x4000 275#define AT91RM92_SPI_PDC 0xffe0100 276 277#define AT91RM92_SSC0_BASE 0xffd0000 --- 16 unchanged lines hidden (view full) --- 294#define AT91RM92_MCI_BASE 0xffb4000 295#define AT91RM92_MCI_PDC 0xffb4100 296#define AT91RM92_MCI_SIZE 0x4000 297 298#define AT91RM92_UDP_BASE 0xffb0000 299#define AT91RM92_UDP_SIZE 0x4000 300 301#define AT91RM92_TC0_BASE 0xffa0000 | 297#define AT91RM92_ST_BASE 0xffffd00 298#define AT91RM92_ST_SIZE 0x100 299 300#define AT91RM92_SPI_BASE 0xffe0000 301#define AT91RM92_SPI_SIZE 0x4000 302#define AT91RM92_SPI_PDC 0xffe0100 303 304#define AT91RM92_SSC0_BASE 0xffd0000 --- 16 unchanged lines hidden (view full) --- 321#define AT91RM92_MCI_BASE 0xffb4000 322#define AT91RM92_MCI_PDC 0xffb4100 323#define AT91RM92_MCI_SIZE 0x4000 324 325#define AT91RM92_UDP_BASE 0xffb0000 326#define AT91RM92_UDP_SIZE 0x4000 327 328#define AT91RM92_TC0_BASE 0xffa0000 |
| 302#define AT91RM92_TC0_SIZE 0x4000 | 329#define AT91RM92_TC_SIZE 0x4000 |
| 303#define AT91RM92_TC0C0_BASE 0xffa0000 304#define AT91RM92_TC0C1_BASE 0xffa0040 305#define AT91RM92_TC0C2_BASE 0xffa0080 306 307#define AT91RM92_TC1_BASE 0xffa4000 | 330#define AT91RM92_TC0C0_BASE 0xffa0000 331#define AT91RM92_TC0C1_BASE 0xffa0040 332#define AT91RM92_TC0C2_BASE 0xffa0080 333 334#define AT91RM92_TC1_BASE 0xffa4000 |
| 308#define AT91RM92_TC1_SIZE 0x4000 | |
| 309#define AT91RM92_TC1C0_BASE 0xffa4000 310#define AT91RM92_TC1C1_BASE 0xffa4040 311#define AT91RM92_TC1C2_BASE 0xffa4080 312 313#define AT91RM92_OHCI_BASE 0x00300000 314#define AT91RM92_OHCI_SIZE 0x00100000 315 | 335#define AT91RM92_TC1C0_BASE 0xffa4000 336#define AT91RM92_TC1C1_BASE 0xffa4040 337#define AT91RM92_TC1C2_BASE 0xffa4080 338 339#define AT91RM92_OHCI_BASE 0x00300000 340#define AT91RM92_OHCI_SIZE 0x00100000 341 |
| 316/* Pio definitions */ 317#define AT91RM92_PIO_PA0 (1 << 0) 318#define AT91RM92_PA0_MISO (AT91RM92_PIO_PA0) /* SPI Master In Slave */ 319#define AT91RM92_PA0_PCK3 (AT91RM92_PIO_PA0) /* PMC Programmable Clock Output 3 */ 320#define AT91RM92_PIO_PA1 (1 << 1) 321#define AT91RM92_PA1_MOSI (AT91RM92_PIO_PA1) /* SPI Master Out Slave */ 322#define AT91RM92_PA1_PCK0 (AT91RM92_PIO_PA1) /* PMC Programmable Clock Output 0 */ 323#define AT91RM92_PIO_PA2 (1 << 2) 324#define AT91RM92_PA2_SPCK (AT91RM92_PIO_PA2) /* SPI Serial Clock */ 325#define AT91RM92_PA2_IRQ4 (AT91RM92_PIO_PA2) /* AIC Interrupt Input 4 */ 326#define AT91RM92_PIO_PA3 (1 << 3) 327#define AT91RM92_PA3_NPCS0 (AT91RM92_PIO_PA3) /* SPI Peripheral Chip Select 0 */ 328#define AT91RM92_PA3_IRQ5 (AT91RM92_PIO_PA3) /* AIC Interrupt Input 5 */ 329#define AT91RM92_PIO_PA4 (1 << 4) 330#define AT91RM92_PA4_NPCS1 (AT91RM92_PIO_PA4) /* SPI Peripheral Chip Select 1 */ 331#define AT91RM92_PA4_PCK1 (AT91RM92_PIO_PA4) /* PMC Programmable Clock Output 1 */ 332#define AT91RM92_PIO_PA5 (1 << 5) 333#define AT91RM92_PA5_NPCS2 (AT91RM92_PIO_PA5) /* SPI Peripheral Chip Select 2 */ 334#define AT91RM92_PA5_TXD3 (AT91RM92_PIO_PA5) /* USART 3 Transmit Data */ 335#define AT91RM92_PIO_PA6 (1 << 6) 336#define AT91RM92_PA6_NPCS3 (AT91RM92_PIO_PA6) /* SPI Peripheral Chip Select 3 */ 337#define AT91RM92_PA6_RXD3 (AT91RM92_PIO_PA6) /* USART 3 Receive Data */ 338#define AT91RM92_PIO_PA7 (1 << 7) 339#define AT91RM92_PA7_ETXCK_EREFC (AT91RM92_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */ 340#define AT91RM92_PA7_PCK2 (AT91RM92_PIO_PA7) /* PMC Programmable Clock 2 */ 341#define AT91RM92_PIO_PA8 (1 << 8) 342#define AT91RM92_PA8_ETXEN (AT91RM92_PIO_PA8) /* Ethernet MAC Transmit Enable */ 343#define AT91RM92_PA8_MCCDB (AT91RM92_PIO_PA8) /* Multimedia Card B Command */ 344#define AT91RM92_PIO_PA9 (1 << 9) 345#define AT91RM92_PA9_ETX0 (AT91RM92_PIO_PA9) /* Ethernet MAC Transmit Data 0 */ 346#define AT91RM92_PA9_MCDB0 (AT91RM92_PIO_PA9) /* Multimedia Card B Data 0 */ 347#define AT91RM92_PIO_PA10 (1 << 10) 348#define AT91RM92_PA10_ETX1 (AT91RM92_PIO_PA10) /* Ethernet MAC Transmit Data 1 */ 349#define AT91RM92_PA10_MCDB1 (AT91RM92_PIO_PA10) /* Multimedia Card B Data 1 */ 350#define AT91RM92_PIO_PA11 (1 << 11) 351#define AT91RM92_PA11_ECRS_ECRSDV (AT91RM92_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ 352#define AT91RM92_PA11_MCDB2 (AT91RM92_PIO_PA11) /* Multimedia Card B Data 2 */ 353#define AT91RM92_PIO_PA12 (1 << 12) 354#define AT91RM92_PA12_ERX0 (AT91RM92_PIO_PA12) /* Ethernet MAC Receive Data 0 */ 355#define AT91RM92_PA12_MCDB3 (AT91RM92_PIO_PA12) /* Multimedia Card B Data 3 */ 356#define AT91RM92_PIO_PA13 (1 << 13) 357#define AT91RM92_PA13_ERX1 (AT91RM92_PIO_PA13) /* Ethernet MAC Receive Data 1 */ 358#define AT91RM92_PA13_TCLK0 (AT91RM92_PIO_PA13) /* Timer Counter 0 external clock input */ 359#define AT91RM92_PIO_PA14 (1 << 14) 360#define AT91RM92_PA14_ERXER (AT91RM92_PIO_PA14) /* Ethernet MAC Receive Error */ 361#define AT91RM92_PA14_TCLK1 (AT91RM92_PIO_PA14) /* Timer Counter 1 external clock input */ 362#define AT91RM92_PIO_PA15 (1 << 15) 363#define AT91RM92_PA15_EMDC (AT91RM92_PIO_PA15) /* Ethernet MAC Management Data Clock */ 364#define AT91RM92_PA15_TCLK2 (AT91RM92_PIO_PA15) /* Timer Counter 2 external clock input */ 365#define AT91RM92_PIO_PA16 (1 << 16) 366#define AT91RM92_PA16_EMDIO (AT91RM92_PIO_PA16) /* Ethernet MAC Management Data Input/Output */ 367#define AT91RM92_PA16_IRQ6 (AT91RM92_PIO_PA16) /* AIC Interrupt input 6 */ 368#define AT91RM92_PIO_PA17 (1 << 17) 369#define AT91RM92_PA17_TXD0 (AT91RM92_PIO_PA17) /* USART 0 Transmit Data */ 370#define AT91RM92_PA17_TIOA0 (AT91RM92_PIO_PA17) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ 371#define AT91RM92_PIO_PA18 (1 << 18) 372#define AT91RM92_PA18_RXD0 (AT91RM92_PIO_PA18) /* USART 0 Receive Data */ 373#define AT91RM92_PA18_TIOB0 (AT91RM92_PIO_PA18) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ 374#define AT91RM92_PIO_PA19 (1 << 19) 375#define AT91RM92_PA19_SCK0 (AT91RM92_PIO_PA19) /* USART 0 Serial Clock */ 376#define AT91RM92_PA19_TIOA1 (AT91RM92_PIO_PA19) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ 377#define AT91RM92_PIO_PA20 (1 << 20) 378#define AT91RM92_PA20_CTS0 (AT91RM92_PIO_PA20) /* USART 0 Clear To Send */ 379#define AT91RM92_PA20_TIOB1 (AT91RM92_PIO_PA20) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ 380#define AT91RM92_PIO_PA21 (1 << 21) 381#define AT91RM92_PA21_RTS0 (AT91RM92_PIO_PA21) /* USART 0 Ready To Send */ 382#define AT91RM92_PA21_TIOA2 (AT91RM92_PIO_PA21) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ 383#define AT91RM92_PIO_PA22 (1 << 22) 384#define AT91RM92_PA22_RXD2 (AT91RM92_PIO_PA22) /* USART 2 Receive Data */ 385#define AT91RM92_PA22_TIOB2 (AT91RM92_PIO_PA22) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ 386#define AT91RM92_PIO_PA23 (1 << 23) 387#define AT91RM92_PA23_TXD2 (AT91RM92_PIO_PA23) /* USART 2 Transmit Data */ 388#define AT91RM92_PA23_IRQ3 (AT91RM92_PIO_PA23) /* Interrupt input 3 */ 389#define AT91RM92_PIO_PA24 (1 << 24) 390#define AT91RM92_PA24_SCK2 (AT91RM92_PIO_PA24) /* USART 2 Serial Clock */ 391#define AT91RM92_PA24_PCK1 (AT91RM92_PIO_PA24) /* PMC Programmable Clock Output 1 */ 392#define AT91RM92_PIO_PA25 (1 << 25) 393#define AT91RM92_PA25_TWD (AT91RM92_PIO_PA25) /* TWI Two-wire Serial Data */ 394#define AT91RM92_PA25_IRQ2 (AT91RM92_PIO_PA25) /* Interrupt input 2 */ 395#define AT91RM92_PIO_PA26 (1 << 26) 396#define AT91RM92_PA26_TWCK (AT91RM92_PIO_PA26) /* TWI Two-wire Serial Clock */ 397#define AT91RM92_PA26_IRQ1 (AT91RM92_PIO_PA26) /* Interrupt input 1 */ 398#define AT91RM92_PIO_PA27 (1 << 27) 399#define AT91RM92_PA27_MCCK (AT91RM92_PIO_PA27) /* Multimedia Card Clock */ 400#define AT91RM92_PA27_TCLK3 (AT91RM92_PIO_PA27) /* Timer Counter 3 External Clock Input */ 401#define AT91RM92_PIO_PA28 (1 << 28) 402#define AT91RM92_PA28_MCCDA (AT91RM92_PIO_PA28) /* Multimedia Card A Command */ 403#define AT91RM92_PA28_TCLK4 (AT91RM92_PIO_PA28) /* Timer Counter 4 external Clock Input */ 404#define AT91RM92_PIO_PA29 (1 << 29) 405#define AT91RM92_PA29_MCDA0 (AT91RM92_PIO_PA29) /* Multimedia Card A Data 0 */ 406#define AT91RM92_PA29_TCLK5 (AT91RM92_PIO_PA29) /* Timer Counter 5 external clock input */ 407#define AT91RM92_PIO_PA30 (1 << 30) 408#define AT91RM92_PA30_DRXD (AT91RM92_PIO_PA30) /* DBGU Debug Receive Data */ 409#define AT91RM92_PA30_CTS2 (AT91RM92_PIO_PA30) /* USART 2 Clear To Send */ 410#define AT91RM92_PIO_PA31 (1 << 31) 411#define AT91RM92_PA31_DTXD (AT91RM92_PIO_PA31) /* DBGU Debug Transmit Data */ 412#define AT91RM92_PA31_RTS2 (AT91RM92_PIO_PA31) /* USART 2 Ready To Send */ 413 414#define AT91RM92_PIO_PB0 (1 << 0) 415#define AT91RM92_PB0_TF0 (AT91RM92_PIO_PB0) /* SSC Transmit Frame Sync 0 */ 416#define AT91RM92_PB0_RTS3 (AT91RM92_PIO_PB0) /* USART 3 Ready To Send */ 417#define AT91RM92_PIO_PB1 (1 << 1) 418#define AT91RM92_PB1_TK0 (AT91RM92_PIO_PB1) /* SSC Transmit Clock 0 */ 419#define AT91RM92_PB1_CTS3 (AT91RM92_PIO_PB1) /* USART 3 Clear To Send */ 420#define AT91RM92_PIO_PB2 (1 << 2) 421#define AT91RM92_PB2_TD0 (AT91RM92_PIO_PB2) /* SSC Transmit data */ 422#define AT91RM92_PB2_SCK3 (AT91RM92_PIO_PB2) /* USART 3 Serial Clock */ 423#define AT91RM92_PIO_PB3 (1 << 3) 424#define AT91RM92_PB3_RD0 (AT91RM92_PIO_PB3) /* SSC Receive Data */ 425#define AT91RM92_PB3_MCDA1 (AT91RM92_PIO_PB3) /* Multimedia Card A Data 1 */ 426#define AT91RM92_PIO_PB4 (1 << 4) 427#define AT91RM92_PB4_RK0 (AT91RM92_PIO_PB4) /* SSC Receive Clock */ 428#define AT91RM92_PB4_MCDA2 (AT91RM92_PIO_PB4) /* Multimedia Card A Data 2 */ 429#define AT91RM92_PIO_PB5 (1 << 5) 430#define AT91RM92_PB5_RF0 (AT91RM92_PIO_PB5) /* SSC Receive Frame Sync 0 */ 431#define AT91RM92_PB5_MCDA3 (AT91RM92_PIO_PB5) /* Multimedia Card A Data 3 */ 432#define AT91RM92_PIO_PB6 (1 << 6) 433#define AT91RM92_PB6_TF1 (AT91RM92_PIO_PB6) /* SSC Transmit Frame Sync 1 */ 434#define AT91RM92_PB6_TIOA3 (AT91RM92_PIO_PB6) /* Timer Counter 4 Multipurpose Timer I/O Pin A */ 435#define AT91RM92_PIO_PB7 (1 << 7) 436#define AT91RM92_PB7_TK1 (AT91RM92_PIO_PB7) /* SSC Transmit Clock 1 */ 437#define AT91RM92_PB7_TIOB3 (AT91RM92_PIO_PB7) /* Timer Counter 3 Multipurpose Timer I/O Pin B */ 438#define AT91RM92_PIO_PB8 (1 << 8) 439#define AT91RM92_PB8_TD1 (AT91RM92_PIO_PB8) /* SSC Transmit Data 1 */ 440#define AT91RM92_PB8_TIOA4 (AT91RM92_PIO_PB8) /* Timer Counter 4 Multipurpose Timer I/O Pin A */ 441#define AT91RM92_PIO_PB9 (1 << 9) 442#define AT91RM92_PB9_RD1 (AT91RM92_PIO_PB9) /* SSC Receive Data 1 */ 443#define AT91RM92_PB9_TIOB4 (AT91RM92_PIO_PB9) /* Timer Counter 4 Multipurpose Timer I/O Pin B */ 444#define AT91RM92_PIO_PB10 (1 << 10) 445#define AT91RM92_PB10_RK1 (AT91RM92_PIO_PB10) /* SSC Receive Clock 1 */ 446#define AT91RM92_PB10_TIOA5 (AT91RM92_PIO_PB10) /* Timer Counter 5 Multipurpose Timer I/O Pin A */ 447#define AT91RM92_PIO_PB11 (1 << 11) 448#define AT91RM92_PB11_RF1 (AT91RM92_PIO_PB11) /* SSC Receive Frame Sync 1 */ 449#define AT91RM92_PB11_TIOB5 (AT91RM92_PIO_PB11) /* Timer Counter 5 Multipurpose Timer I/O Pin B */ 450#define AT91RM92_PIO_PB12 (1 << 12) 451#define AT91RM92_PB12_TF2 (AT91RM92_PIO_PB12) /* SSC Transmit Frame Sync 2 */ 452#define AT91RM92_PB12_ETX2 (AT91RM92_PIO_PB12) /* Ethernet MAC Transmit Data 2 */ 453#define AT91RM92_PIO_PB13 (1 << 13) 454#define AT91RM92_PB13_TK2 (AT91RM92_PIO_PB13) /* SSC Transmit Clock 2 */ 455#define AT91RM92_PB13_ETX3 (AT91RM92_PIO_PB13) /* Ethernet MAC Transmit Data 3 */ 456#define AT91RM92_PIO_PB14 (1 << 14) 457#define AT91RM92_PB14_TD2 (AT91RM92_PIO_PB14) /* SSC Transmit Data 2 */ 458#define AT91RM92_PB14_ETXER (AT91RM92_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */ 459#define AT91RM92_PIO_PB15 (1 << 15) 460#define AT91RM92_PB15_RD2 (AT91RM92_PIO_PB15) /* SSC Receive Data 2 */ 461#define AT91RM92_PB15_ERX2 (AT91RM92_PIO_PB15) /* Ethernet MAC Receive Data 2 */ 462#define AT91RM92_PIO_PB16 (1 << 16) 463#define AT91RM92_PB16_RK2 (AT91RM92_PIO_PB16) /* SSC Receive Clock 2 */ 464#define AT91RM92_PB16_ERX3 (AT91RM92_PIO_PB16) /* Ethernet MAC Receive Data 3 */ 465#define AT91RM92_PIO_PB17 (1 << 17) 466#define AT91RM92_PB17_RF2 (AT91RM92_PIO_PB17) /* SSC Receive Frame Sync 2 */ 467#define AT91RM92_PB17_ERXDV (AT91RM92_PIO_PB17) /* Ethernet MAC Receive Data Valid */ 468#define AT91RM92_PIO_PB18 (1 << 18) 469#define AT91RM92_PB18_RI1 (AT91RM92_PIO_PB18) /* USART 1 Ring Indicator */ 470#define AT91RM92_PB18_ECOL (AT91RM92_PIO_PB18) /* Ethernet MAC Collision Detected */ 471#define AT91RM92_PIO_PB19 (1 << 19) 472#define AT91RM92_PB19_DTR1 (AT91RM92_PIO_PB19) /* USART 1 Data Terminal ready */ 473#define AT91RM92_PB19_ERXCK (AT91RM92_PIO_PB19) /* Ethernet MAC Receive Clock */ 474#define AT91RM92_PIO_PB20 (1 << 20) 475#define AT91RM92_PB20_TXD1 (AT91RM92_PIO_PB20) /* USART 1 Transmit Data */ 476#define AT91RM92_PIO_PB21 (1 << 21) 477#define AT91RM92_PB21_RXD1 (AT91RM92_PIO_PB21) /* USART 1 Receive Data */ 478#define AT91RM92_PIO_PB22 (1 << 22) 479#define AT91RM92_PB22_SCK1 (AT91RM92_PIO_PB22) /* USART 1 Serial Clock */ 480#define AT91RM92_PIO_PB23 (1 << 23) 481#define AT91RM92_PB23_DCD1 (AT91RM92_PIO_PB23) /* USART 1 Data Carrier Detect */ 482#define AT91RM92_PIO_PB24 (1 << 24) 483#define AT91RM92_PB24_CTS1 (AT91RM92_PIO_PB24) /* USART 1 Clear To Send */ 484#define AT91RM92_PIO_PB25 (1 << 25) 485#define AT91RM92_PB25_DSR1 (AT91RM92_PIO_PB25) /* USART 1 Data Set ready */ 486#define AT91RM92_PB25_EF100 (AT91RM92_PIO_PB25) /* Ethernet MAC Force 100 Mbits/sec */ 487#define AT91RM92_PIO_PB26 (1 << 26) 488#define AT91RM92_PB26_RTS1 (AT91RM92_PIO_PB26) /* USART 1 Ready To Send */ 489#define AT91RM92_PIO_PB27 (1 << 27) 490#define AT91RM92_PB27_PCK0 (AT91RM92_PIO_PB27) /* PMC Programmable Clock Output 0 */ 491#define AT91RM92_PIO_PB28 (1 << 28) 492#define AT91RM92_PB28_FIQ (AT91RM92_PIO_PB28) /* AIC Fast Interrupt Input */ 493#define AT91RM92_PIO_PB29 (1 << 29) 494#define AT91RM92_PB29_IRQ0 (AT91RM92_PIO_PB29) /* Interrupt input 0 */ 495 496#define AT91RM92_PIO_PC0 (1 << 0) 497#define AT91RM92_PC0_BFCK (AT91RM92_PIO_PC0) /* Burst Flash Clock */ 498#define AT91RM92_PIO_PC1 (1 << 1) 499#define AT91RM92_PC1_BFRDY_SMOE (AT91RM92_PIO_PC1) /* Burst Flash Ready */ 500#define AT91RM92_PIO_PC2 (1 << 2) 501#define AT91RM92_PC2_BFAVD (AT91RM92_PIO_PC2) /* Burst Flash Address Valid */ 502#define AT91RM92_PIO_PC3 (1 << 3) 503#define AT91RM92_PC3_BFBAA_SMWE (AT91RM92_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */ 504#define AT91RM92_PIO_PC4 (1 << 4) 505#define AT91RM92_PC4_BFOE (AT91RM92_PIO_PC4) /* Burst Flash Output Enable */ 506#define AT91RM92_PIO_PC5 (1 << 5) 507#define AT91RM92_PC5_BFWE (AT91RM92_PIO_PC5) /* Burst Flash Write Enable */ 508#define AT91RM92_PIO_PC6 (1 << 6) 509#define AT91RM92_PC6_NWAIT (AT91RM92_PIO_PC6) /* NWAIT */ 510#define AT91RM92_PIO_PC7 (1 << 7) 511#define AT91RM92_PC7_A23 (AT91RM92_PIO_PC7) /* Address Bus[23] */ 512#define AT91RM92_PIO_PC8 (1 << 8) 513#define AT91RM92_PC8_A24 (AT91RM92_PIO_PC8) /* Address Bus[24] */ 514#define AT91RM92_PIO_PC9 (1 << 9) 515#define AT91RM92_PC9_A25_CFRNW (AT91RM92_PIO_PC9) /* Address Bus[25] / Compact Flash Read Not Write */ 516#define AT91RM92_PIO_PC10 (1 << 10) 517#define AT91RM92_PC10_NCS4_CFCS (AT91RM92_PIO_PC10) /* Compact Flash Chip Select */ 518#define AT91RM92_PIO_PC11 (1 << 11) 519#define AT91RM92_PC11_NCS5_CFCE1 (AT91RM92_PIO_PC11) /* Chip Select 5 / Compact Flash Chip Enable 1 */ 520#define AT91RM92_PIO_PC12 (1 << 12) 521#define AT91RM92_PC12_NCS6_CFCE2(AT91RM92_PIO_PC12) /* Chip Select 6 / Compact Flash Chip Enable 2 */ 522#define AT91RM92_PIO_PC13 (1 << 13) 523#define AT91RM92_PC13_NCS7 (AT91RM92_PIO_PC13) /* Chip Select 7 */ 524#define AT91RM92_PIO_PC14 (1 << 14) 525#define AT91RM92_PIO_PC15 (1 << 15) 526#define AT91RM92_PIO_PC16 (1 << 16) 527#define AT91RM92_PC16_D16 (AT91RM92_PIO_PC16) /* Data Bus [16] */ 528#define AT91RM92_PIO_PC17 (1 << 17) 529#define AT91RM92_PC17_D17 (AT91RM92_PIO_PC17) /* Data Bus [17] */ 530#define AT91RM92_PIO_PC18 (1 << 18) 531#define AT91RM92_PC18_D18 (AT91RM92_PIO_PC18) /* Data Bus [18] */ 532#define AT91RM92_PIO_PC19 (1 << 19) 533#define AT91RM92_PC19_D19 (AT91RM92_PIO_PC19) /* Data Bus [19] */ 534#define AT91RM92_PIO_PC20 (1 << 20) 535#define AT91RM92_PC20_D20 (AT91RM92_PIO_PC20) /* Data Bus [20] */ 536#define AT91RM92_PIO_PC21 (1 << 21) 537#define AT91RM92_PC21_D21 (AT91RM92_PIO_PC21) /* Data Bus [21] */ 538#define AT91RM92_PIO_PC22 (1 << 22) 539#define AT91RM92_PC22_D22 (AT91RM92_PIO_PC22) /* Data Bus [22] */ 540#define AT91RM92_PIO_PC23 (1 << 23) 541#define AT91RM92_PC23_D23 (AT91RM92_PIO_PC23) /* Data Bus [23] */ 542#define AT91RM92_PIO_PC24 (1 << 24) 543#define AT91RM92_PC24_D24 (AT91RM92_PIO_PC24) /* Data Bus [24] */ 544#define AT91RM92_PIO_PC25 (1 << 25) 545#define AT91RM92_PC25_D25 (AT91RM92_PIO_PC25) /* Data Bus [25] */ 546#define AT91RM92_PIO_PC26 (1 << 26) 547#define AT91RM92_PC26_D26 (AT91RM92_PIO_PC26) /* Data Bus [26] */ 548#define AT91RM92_PIO_PC27 (1 << 27) 549#define AT91RM92_PC27_D27 (AT91RM92_PIO_PC27) /* Data Bus [27] */ 550#define AT91RM92_PIO_PC28 (1 << 28) 551#define AT91RM92_PC28_D28 (AT91RM92_PIO_PC28) /* Data Bus [28] */ 552#define AT91RM92_PIO_PC29 (1 << 29) 553#define AT91RM92_PC29_D29 (AT91RM92_PIO_PC29) /* Data Bus [29] */ 554#define AT91RM92_PIO_PC30 (1 << 30) 555#define AT91RM92_PC30_D30 (AT91RM92_PIO_PC30) /* Data Bus [30] */ 556#define AT91RM92_PIO_PC31 (1 << 31) 557#define AT91RM92_PC31_D31 (AT91RM92_PIO_PC31) /* Data Bus [31] */ 558 559#define AT91RM92_PIO_PD0 (1 << 0) 560#define AT91RM92_PD0_ETX0 (AT91RM92_PIO_PD0) /* Ethernet MAC Transmit Data 0 */ 561#define AT91RM92_PIO_PD1 (1 << 1) 562#define AT91RM92_PD1_ETX1 (AT91RM92_PIO_PD1) /* Ethernet MAC Transmit Data 1 */ 563#define AT91RM92_PIO_PD2 (1 << 2) 564#define AT91RM92_PD2_ETX2 (AT91RM92_PIO_PD2) /* Ethernet MAC Transmit Data 2 */ 565#define AT91RM92_PIO_PD3 (1 << 3) 566#define AT91RM92_PD3_ETX3 (AT91RM92_PIO_PD3) /* Ethernet MAC Transmit Data 3 */ 567#define AT91RM92_PIO_PD4 (1 << 4) 568#define AT91RM92_PD4_ETXEN (AT91RM92_PIO_PD4) /* Ethernet MAC Transmit Enable */ 569#define AT91RM92_PIO_PD5 (1 << 5) 570#define AT91RM92_PD5_ETXER (AT91RM92_PIO_PD5) /* Ethernet MAC Transmit Coding Error */ 571#define AT91RM92_PIO_PD6 (1 << 6) 572#define AT91RM92_PD6_DTXD (AT91RM92_PIO_PD6) /* DBGU Debug Transmit Data */ 573#define AT91RM92_PIO_PD7 (1 << 7) 574#define AT91RM92_PD7_PCK0 (AT91RM92_PIO_PD7) /* PMC Programmable Clock Output 0 */ 575#define AT91RM92_PD7_TSYNC (AT91RM92_PIO_PD7) /* ETM Synchronization signal */ 576#define AT91RM92_PIO_PD8 (1 << 8) 577#define AT91RM92_PD8_PCK1 (AT91RM92_PIO_PD8) /* PMC Programmable Clock Output 1 */ 578#define AT91RM92_PD8_TCLK (AT91RM92_PIO_PD8) /* ETM Trace Clock signal */ 579#define AT91RM92_PIO_PD9 (1 << 9) 580#define AT91RM92_PD9_PCK2 (AT91RM92_PIO_PD9) /* PMC Programmable Clock 2 */ 581#define AT91RM92_PD9_TPS0 (AT91RM92_PIO_PD9) /* ETM ARM9 pipeline status 0 */ 582#define AT91RM92_PIO_PD10 (1 << 10) 583#define AT91RM92_PD10_PCK3 (AT91RM92_PIO_PD10) /* PMC Programmable Clock Output 3 */ 584#define AT91RM92_PD10_TPS1 (AT91RM92_PIO_PD10) /* ETM ARM9 pipeline status 1 */ 585#define AT91RM92_PIO_PD11 (1 << 11) 586#define AT91RM92_PD11_TPS2 (AT91RM92_PIO_PD11) /* ETM ARM9 pipeline status 2 */ 587#define AT91RM92_PIO_PD12 (1 << 12) 588#define AT91RM92_PD12_TPK0 (AT91RM92_PIO_PD12) /* ETM Trace Packet 0 */ 589#define AT91RM92_PIO_PD13 (1 << 13) 590#define AT91RM92_PD13_TPK1 (AT91RM92_PIO_PD13) /* ETM Trace Packet 1 */ 591#define AT91RM92_PIO_PD14 (1 << 14) 592#define AT91RM92_PD14_TPK2 (AT91RM92_PIO_PD14) /* ETM Trace Packet 2 */ 593#define AT91RM92_PIO_PD15 (1 << 15) 594#define AT91RM92_PD15_TD0 (AT91RM92_PIO_PD15) /* SSC Transmit data */ 595#define AT91RM92_PD15_TPK3 (AT91RM92_PIO_PD15) /* ETM Trace Packet 3 */ 596#define AT91RM92_PIO_PD16 (1 << 16) 597#define AT91RM92_PD16_TD1 (AT91RM92_PIO_PD16) /* SSC Transmit Data 1 */ 598#define AT91RM92_PD16_TPK4 (AT91RM92_PIO_PD16) /* ETM Trace Packet 4 */ 599#define AT91RM92_PIO_PD17 (1 << 17) 600#define AT91RM92_PD17_TD2 (AT91RM92_PIO_PD17) /* SSC Transmit Data 2 */ 601#define AT91RM92_PD17_TPK5 (AT91RM92_PIO_PD17) /* ETM Trace Packet 5 */ 602#define AT91RM92_PIO_PD18 (1 << 18) 603#define AT91RM92_PD18_NPCS1 (AT91RM92_PIO_PD18) /* SPI Peripheral Chip Select 1 */ 604#define AT91RM92_PD18_TPK6 (AT91RM92_PIO_PD18) /* ETM Trace Packet 6 */ 605#define AT91RM92_PIO_PD19 (1 << 19) 606#define AT91RM92_PD19_NPCS2 (AT91RM92_PIO_PD19) /* SPI Peripheral Chip Select 2 */ 607#define AT91RM92_PD19_TPK7 (AT91RM92_PIO_PD19) /* ETM Trace Packet 7 */ 608#define AT91RM92_PIO_PD20 (1 << 20) 609#define AT91RM92_PD20_NPCS3 (AT91RM92_PIO_PD20) /* SPI Peripheral Chip Select 3 */ 610#define AT91RM92_PD20_TPK8 (AT91RM92_PIO_PD20) /* ETM Trace Packet 8 */ 611#define AT91RM92_PIO_PD21 (1 << 21) 612#define AT91RM92_PD21_RTS0 (AT91RM92_PIO_PD21) /* Usart 0 Ready To Send */ 613#define AT91RM92_PD21_TPK9 (AT91RM92_PIO_PD21) /* ETM Trace Packet 9 */ 614#define AT91RM92_PIO_PD22 (1 << 22) 615#define AT91RM92_PD22_RTS1 (AT91RM92_PIO_PD22) /* Usart 0 Ready To Send */ 616#define AT91RM92_PD22_TPK10 (AT91RM92_PIO_PD22) /* ETM Trace Packet 10 */ 617#define AT91RM92_PIO_PD23 (1 << 23) 618#define AT91RM92_PD23_RTS2 (AT91RM92_PIO_PD23) /* USART 2 Ready To Send */ 619#define AT91RM92_PD23_TPK11 (AT91RM92_PIO_PD23) /* ETM Trace Packet 11 */ 620#define AT91RM92_PIO_PD24 (1 << 24) 621#define AT91RM92_PD24_RTS3 (AT91RM92_PIO_PD24) /* USART 3 Ready To Send */ 622#define AT91RM92_PD24_TPK12 (AT91RM92_PIO_PD24) /* ETM Trace Packet 12 */ 623#define AT91RM92_PIO_PD25 (1 << 25) 624#define AT91RM92_PD25_DTR1 (AT91RM92_PIO_PD25) /* USART 1 Data Terminal ready */ 625#define AT91RM92_PD25_TPK13 (AT91RM92_PIO_PD25) /* ETM Trace Packet 13 */ 626#define AT91RM92_PIO_PD26 (1 << 26) 627#define AT91RM92_PD26_TPK14 (AT91RM92_PIO_PD26) /* ETM Trace Packet 14 */ 628#define AT91RM92_PIO_PD27 (1 << 27) 629#define AT91RM92_PD27_TPK15 (AT91RM92_PIO_PD27) /* ETM Trace Packet 15 */ 630 | |
| 631#define AT91C_MASTER_CLOCK 60000000 632 633#endif /* AT91RM92REG_H_ */ | 342#define AT91C_MASTER_CLOCK 60000000 343 344#endif /* AT91RM92REG_H_ */ |