| at91_twireg.h (213496) | at91_twireg.h (234281) |
|---|---|
| 1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 9 unchanged lines hidden (view full) --- 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 | 1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 9 unchanged lines hidden (view full) --- 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 |
| 26/* $FreeBSD: head/sys/arm/at91/at91_twireg.h 213496 2010-10-06 22:25:21Z cognet $ */ | 26/* $FreeBSD: head/sys/arm/at91/at91_twireg.h 234281 2012-04-14 11:29:32Z marius $ */ |
| 27 28#ifndef ARM_AT91_AT91_TWIREG_H | 27 28#ifndef ARM_AT91_AT91_TWIREG_H |
| 29#define ARM_AT91_AT91_TWIREG_H | 29#define ARM_AT91_AT91_TWIREG_H |
| 30 | 30 |
| 31#define TWI_CR 0x00 /* TWI Control Register */ 32#define TWI_MMR 0x04 /* TWI Master Mode Register */ 33#define TWI_SMR 0x08 /* TWI Master Mode Register */ 34#define TWI_IADR 0x0c /* TWI Internal Address Register */ 35#define TWI_CWGR 0x10 /* TWI Clock Waveform Generator Reg */ | 31#define TWI_CR 0x00 /* TWI Control Register */ 32#define TWI_MMR 0x04 /* TWI Master Mode Register */ 33#define TWI_SMR 0x08 /* TWI Master Mode Register */ 34#define TWI_IADR 0x0c /* TWI Internal Address Register */ 35#define TWI_CWGR 0x10 /* TWI Clock Waveform Generator Reg */ |
| 36 /* 0x14 reserved */ 37 /* 0x18 reserved */ 38 /* 0x1c reserved */ | 36 /* 0x14 reserved */ 37 /* 0x18 reserved */ 38 /* 0x1c reserved */ |
| 39#define TWI_SR 0x20 /* TWI Status Register */ 40#define TWI_IER 0x24 /* TWI Interrupt Enable Register */ 41#define TWI_IDR 0x28 /* TWI Interrupt Disable Register */ 42#define TWI_IMR 0x2c /* TWI Interrupt Mask Register */ 43#define TWI_RHR 0x30 /* TWI Receiver Holding Register */ 44#define TWI_THR 0x34 /* TWI Transmit Holding Register */ | 39#define TWI_SR 0x20 /* TWI Status Register */ 40#define TWI_IER 0x24 /* TWI Interrupt Enable Register */ 41#define TWI_IDR 0x28 /* TWI Interrupt Disable Register */ 42#define TWI_IMR 0x2c /* TWI Interrupt Mask Register */ 43#define TWI_RHR 0x30 /* TWI Receiver Holding Register */ 44#define TWI_THR 0x34 /* TWI Transmit Holding Register */ |
| 45 46/* TWI_CR */ | 45 46/* TWI_CR */ |
| 47#define TWI_CR_START (1U << 0) /* Send a start */ 48#define TWI_CR_STOP (1U << 1) /* Send a stop */ 49#define TWI_CR_MSEN (1U << 2) /* Master Transfer Enable */ 50#define TWI_CR_MSDIS (1U << 3) /* Master Transfer Disable */ 51#define TWI_CR_SVEN (1U << 4) /* Slave Transfer Enable */ 52#define TWI_CR_SVDIS (1U << 5) /* Slave Transfer Disable */ 53#define TWI_CR_SWRST (1U << 7) /* Software Reset */ | 47#define TWI_CR_START (1U << 0) /* Send a start */ 48#define TWI_CR_STOP (1U << 1) /* Send a stop */ 49#define TWI_CR_MSEN (1U << 2) /* Master Transfer Enable */ 50#define TWI_CR_MSDIS (1U << 3) /* Master Transfer Disable */ 51#define TWI_CR_SVEN (1U << 4) /* Slave Transfer Enable */ 52#define TWI_CR_SVDIS (1U << 5) /* Slave Transfer Disable */ 53#define TWI_CR_SWRST (1U << 7) /* Software Reset */ |
| 54 55/* TWI_MMR */ 56/* TWI_SMR */ | 54 55/* TWI_MMR */ 56/* TWI_SMR */ |
| 57#define TWI_MMR_IADRSZ(n) ((n) << 8) /* Set size of transfer */ 58#define TWI_MMR_MWRITE 0U /* Master Read Direction */ 59#define TWI_MMR_MREAD (1U << 12) /* Master Read Direction */ 60#define TWI_MMR_DADR(n) ((n) << 15) /* Device Address */ | 57#define TWI_MMR_IADRSZ(n) ((n) << 8) /* Set size of transfer */ 58#define TWI_MMR_MWRITE 0U /* Master Read Direction */ 59#define TWI_MMR_MREAD (1U << 12) /* Master Read Direction */ 60#define TWI_MMR_DADR(n) ((n) << 15) /* Device Address */ |
| 61 62/* TWI_CWGR */ | 61 62/* TWI_CWGR */ |
| 63#define TWI_CWGR_CKDIV(x) ((x) << 16) /* Clock Divider */ 64#define TWI_CWGR_CHDIV(x) ((x) << 8) /* Clock High Divider */ 65#define TWI_CWGR_CLDIV(x) ((x) << 0) /* Clock Low Divider */ 66#define TWI_CWGR_DIV(rate) \ 67 (at91_is_sam9() ? \ 68 ((at91_master_clock /(4*(rate))) - 3) : \ 69 ((at91_master_clock /(4*(rate))) - 2)) | 63#define TWI_CWGR_CKDIV(x) ((x) << 16) /* Clock Divider */ 64#define TWI_CWGR_CHDIV(x) ((x) << 8) /* Clock High Divider */ 65#define TWI_CWGR_CLDIV(x) ((x) << 0) /* Clock Low Divider */ 66#define TWI_CWGR_DIV(rate) \ 67 (at91_is_sam9() ? \ 68 ((at91_master_clock / (4 * (rate))) - 3) : \ 69 ((at91_master_clock / (4 * (rate))) - 2)) |
| 70 71/* TWI_SR */ 72/* TWI_IER */ 73/* TWI_IDR */ 74/* TWI_IMR */ | 70 71/* TWI_SR */ 72/* TWI_IER */ 73/* TWI_IDR */ 74/* TWI_IMR */ |
| 75#define TWI_SR_TXCOMP (1U << 0) /* Transmission Completed */ 76#define TWI_SR_RXRDY (1U << 1) /* Receive Holding Register Ready */ 77#define TWI_SR_TXRDY (1U << 2) /* Transmit Holding Register Ready */ 78#define TWI_SR_SVREAD (1U << 3) /* Slave Read */ 79#define TWI_SR_SVACC (1U << 4) /* Slave Access */ 80#define TWI_SR_GCACC (1U << 5) /* General Call Access */ 81#define TWI_SR_OVRE (1U << 6) /* Overrun error */ 82#define TWI_SR_UNRE (1U << 7) /* Underrun Error */ 83#define TWI_SR_NACK (1U << 8) /* Not Acknowledged */ 84#define TWI_SR_ARBLST (1U << 9) /* Arbitration Lost */ | 75#define TWI_SR_TXCOMP (1U << 0) /* Transmission Completed */ 76#define TWI_SR_RXRDY (1U << 1) /* Receive Holding Register Ready */ 77#define TWI_SR_TXRDY (1U << 2) /* Transmit Holding Register Ready */ 78#define TWI_SR_SVREAD (1U << 3) /* Slave Read */ 79#define TWI_SR_SVACC (1U << 4) /* Slave Access */ 80#define TWI_SR_GCACC (1U << 5) /* General Call Access */ 81#define TWI_SR_OVRE (1U << 6) /* Overrun error */ 82#define TWI_SR_UNRE (1U << 7) /* Underrun Error */ 83#define TWI_SR_NACK (1U << 8) /* Not Acknowledged */ 84#define TWI_SR_ARBLST (1U << 9) /* Arbitration Lost */ |
| 85 86#endif /* ARM_AT91_AT91_TWIREG_H */ | 85 86#endif /* ARM_AT91_AT91_TWIREG_H */ |