26c26
< /* $FreeBSD: head/sys/arm/at91/at91_twireg.h 213496 2010-10-06 22:25:21Z cognet $ */
---
> /* $FreeBSD: head/sys/arm/at91/at91_twireg.h 234281 2012-04-14 11:29:32Z marius $ */
29c29
< #define ARM_AT91_AT91_TWIREG_H
---
> #define ARM_AT91_AT91_TWIREG_H
31,35c31,35
< #define TWI_CR 0x00 /* TWI Control Register */
< #define TWI_MMR 0x04 /* TWI Master Mode Register */
< #define TWI_SMR 0x08 /* TWI Master Mode Register */
< #define TWI_IADR 0x0c /* TWI Internal Address Register */
< #define TWI_CWGR 0x10 /* TWI Clock Waveform Generator Reg */
---
> #define TWI_CR 0x00 /* TWI Control Register */
> #define TWI_MMR 0x04 /* TWI Master Mode Register */
> #define TWI_SMR 0x08 /* TWI Master Mode Register */
> #define TWI_IADR 0x0c /* TWI Internal Address Register */
> #define TWI_CWGR 0x10 /* TWI Clock Waveform Generator Reg */
39,44c39,44
< #define TWI_SR 0x20 /* TWI Status Register */
< #define TWI_IER 0x24 /* TWI Interrupt Enable Register */
< #define TWI_IDR 0x28 /* TWI Interrupt Disable Register */
< #define TWI_IMR 0x2c /* TWI Interrupt Mask Register */
< #define TWI_RHR 0x30 /* TWI Receiver Holding Register */
< #define TWI_THR 0x34 /* TWI Transmit Holding Register */
---
> #define TWI_SR 0x20 /* TWI Status Register */
> #define TWI_IER 0x24 /* TWI Interrupt Enable Register */
> #define TWI_IDR 0x28 /* TWI Interrupt Disable Register */
> #define TWI_IMR 0x2c /* TWI Interrupt Mask Register */
> #define TWI_RHR 0x30 /* TWI Receiver Holding Register */
> #define TWI_THR 0x34 /* TWI Transmit Holding Register */
47,53c47,53
< #define TWI_CR_START (1U << 0) /* Send a start */
< #define TWI_CR_STOP (1U << 1) /* Send a stop */
< #define TWI_CR_MSEN (1U << 2) /* Master Transfer Enable */
< #define TWI_CR_MSDIS (1U << 3) /* Master Transfer Disable */
< #define TWI_CR_SVEN (1U << 4) /* Slave Transfer Enable */
< #define TWI_CR_SVDIS (1U << 5) /* Slave Transfer Disable */
< #define TWI_CR_SWRST (1U << 7) /* Software Reset */
---
> #define TWI_CR_START (1U << 0) /* Send a start */
> #define TWI_CR_STOP (1U << 1) /* Send a stop */
> #define TWI_CR_MSEN (1U << 2) /* Master Transfer Enable */
> #define TWI_CR_MSDIS (1U << 3) /* Master Transfer Disable */
> #define TWI_CR_SVEN (1U << 4) /* Slave Transfer Enable */
> #define TWI_CR_SVDIS (1U << 5) /* Slave Transfer Disable */
> #define TWI_CR_SWRST (1U << 7) /* Software Reset */
57,60c57,60
< #define TWI_MMR_IADRSZ(n) ((n) << 8) /* Set size of transfer */
< #define TWI_MMR_MWRITE 0U /* Master Read Direction */
< #define TWI_MMR_MREAD (1U << 12) /* Master Read Direction */
< #define TWI_MMR_DADR(n) ((n) << 15) /* Device Address */
---
> #define TWI_MMR_IADRSZ(n) ((n) << 8) /* Set size of transfer */
> #define TWI_MMR_MWRITE 0U /* Master Read Direction */
> #define TWI_MMR_MREAD (1U << 12) /* Master Read Direction */
> #define TWI_MMR_DADR(n) ((n) << 15) /* Device Address */
63,69c63,69
< #define TWI_CWGR_CKDIV(x) ((x) << 16) /* Clock Divider */
< #define TWI_CWGR_CHDIV(x) ((x) << 8) /* Clock High Divider */
< #define TWI_CWGR_CLDIV(x) ((x) << 0) /* Clock Low Divider */
< #define TWI_CWGR_DIV(rate) \
< (at91_is_sam9() ? \
< ((at91_master_clock /(4*(rate))) - 3) : \
< ((at91_master_clock /(4*(rate))) - 2))
---
> #define TWI_CWGR_CKDIV(x) ((x) << 16) /* Clock Divider */
> #define TWI_CWGR_CHDIV(x) ((x) << 8) /* Clock High Divider */
> #define TWI_CWGR_CLDIV(x) ((x) << 0) /* Clock Low Divider */
> #define TWI_CWGR_DIV(rate) \
> (at91_is_sam9() ? \
> ((at91_master_clock / (4 * (rate))) - 3) : \
> ((at91_master_clock / (4 * (rate))) - 2))
75,84c75,84
< #define TWI_SR_TXCOMP (1U << 0) /* Transmission Completed */
< #define TWI_SR_RXRDY (1U << 1) /* Receive Holding Register Ready */
< #define TWI_SR_TXRDY (1U << 2) /* Transmit Holding Register Ready */
< #define TWI_SR_SVREAD (1U << 3) /* Slave Read */
< #define TWI_SR_SVACC (1U << 4) /* Slave Access */
< #define TWI_SR_GCACC (1U << 5) /* General Call Access */
< #define TWI_SR_OVRE (1U << 6) /* Overrun error */
< #define TWI_SR_UNRE (1U << 7) /* Underrun Error */
< #define TWI_SR_NACK (1U << 8) /* Not Acknowledged */
< #define TWI_SR_ARBLST (1U << 9) /* Arbitration Lost */
---
> #define TWI_SR_TXCOMP (1U << 0) /* Transmission Completed */
> #define TWI_SR_RXRDY (1U << 1) /* Receive Holding Register Ready */
> #define TWI_SR_TXRDY (1U << 2) /* Transmit Holding Register Ready */
> #define TWI_SR_SVREAD (1U << 3) /* Slave Read */
> #define TWI_SR_SVACC (1U << 4) /* Slave Access */
> #define TWI_SR_GCACC (1U << 5) /* General Call Access */
> #define TWI_SR_OVRE (1U << 6) /* Overrun error */
> #define TWI_SR_UNRE (1U << 7) /* Underrun Error */
> #define TWI_SR_NACK (1U << 8) /* Not Acknowledged */
> #define TWI_SR_ARBLST (1U << 9) /* Arbitration Lost */
< /* $FreeBSD: head/sys/arm/at91/at91_twireg.h 213496 2010-10-06 22:25:21Z cognet $ */
---
> /* $FreeBSD: head/sys/arm/at91/at91_twireg.h 234281 2012-04-14 11:29:32Z marius $ */
29c29
< #define ARM_AT91_AT91_TWIREG_H
---
> #define ARM_AT91_AT91_TWIREG_H
31,35c31,35
< #define TWI_CR 0x00 /* TWI Control Register */
< #define TWI_MMR 0x04 /* TWI Master Mode Register */
< #define TWI_SMR 0x08 /* TWI Master Mode Register */
< #define TWI_IADR 0x0c /* TWI Internal Address Register */
< #define TWI_CWGR 0x10 /* TWI Clock Waveform Generator Reg */
---
> #define TWI_CR 0x00 /* TWI Control Register */
> #define TWI_MMR 0x04 /* TWI Master Mode Register */
> #define TWI_SMR 0x08 /* TWI Master Mode Register */
> #define TWI_IADR 0x0c /* TWI Internal Address Register */
> #define TWI_CWGR 0x10 /* TWI Clock Waveform Generator Reg */
39,44c39,44
< #define TWI_SR 0x20 /* TWI Status Register */
< #define TWI_IER 0x24 /* TWI Interrupt Enable Register */
< #define TWI_IDR 0x28 /* TWI Interrupt Disable Register */
< #define TWI_IMR 0x2c /* TWI Interrupt Mask Register */
< #define TWI_RHR 0x30 /* TWI Receiver Holding Register */
< #define TWI_THR 0x34 /* TWI Transmit Holding Register */
---
> #define TWI_SR 0x20 /* TWI Status Register */
> #define TWI_IER 0x24 /* TWI Interrupt Enable Register */
> #define TWI_IDR 0x28 /* TWI Interrupt Disable Register */
> #define TWI_IMR 0x2c /* TWI Interrupt Mask Register */
> #define TWI_RHR 0x30 /* TWI Receiver Holding Register */
> #define TWI_THR 0x34 /* TWI Transmit Holding Register */
47,53c47,53
< #define TWI_CR_START (1U << 0) /* Send a start */
< #define TWI_CR_STOP (1U << 1) /* Send a stop */
< #define TWI_CR_MSEN (1U << 2) /* Master Transfer Enable */
< #define TWI_CR_MSDIS (1U << 3) /* Master Transfer Disable */
< #define TWI_CR_SVEN (1U << 4) /* Slave Transfer Enable */
< #define TWI_CR_SVDIS (1U << 5) /* Slave Transfer Disable */
< #define TWI_CR_SWRST (1U << 7) /* Software Reset */
---
> #define TWI_CR_START (1U << 0) /* Send a start */
> #define TWI_CR_STOP (1U << 1) /* Send a stop */
> #define TWI_CR_MSEN (1U << 2) /* Master Transfer Enable */
> #define TWI_CR_MSDIS (1U << 3) /* Master Transfer Disable */
> #define TWI_CR_SVEN (1U << 4) /* Slave Transfer Enable */
> #define TWI_CR_SVDIS (1U << 5) /* Slave Transfer Disable */
> #define TWI_CR_SWRST (1U << 7) /* Software Reset */
57,60c57,60
< #define TWI_MMR_IADRSZ(n) ((n) << 8) /* Set size of transfer */
< #define TWI_MMR_MWRITE 0U /* Master Read Direction */
< #define TWI_MMR_MREAD (1U << 12) /* Master Read Direction */
< #define TWI_MMR_DADR(n) ((n) << 15) /* Device Address */
---
> #define TWI_MMR_IADRSZ(n) ((n) << 8) /* Set size of transfer */
> #define TWI_MMR_MWRITE 0U /* Master Read Direction */
> #define TWI_MMR_MREAD (1U << 12) /* Master Read Direction */
> #define TWI_MMR_DADR(n) ((n) << 15) /* Device Address */
63,69c63,69
< #define TWI_CWGR_CKDIV(x) ((x) << 16) /* Clock Divider */
< #define TWI_CWGR_CHDIV(x) ((x) << 8) /* Clock High Divider */
< #define TWI_CWGR_CLDIV(x) ((x) << 0) /* Clock Low Divider */
< #define TWI_CWGR_DIV(rate) \
< (at91_is_sam9() ? \
< ((at91_master_clock /(4*(rate))) - 3) : \
< ((at91_master_clock /(4*(rate))) - 2))
---
> #define TWI_CWGR_CKDIV(x) ((x) << 16) /* Clock Divider */
> #define TWI_CWGR_CHDIV(x) ((x) << 8) /* Clock High Divider */
> #define TWI_CWGR_CLDIV(x) ((x) << 0) /* Clock Low Divider */
> #define TWI_CWGR_DIV(rate) \
> (at91_is_sam9() ? \
> ((at91_master_clock / (4 * (rate))) - 3) : \
> ((at91_master_clock / (4 * (rate))) - 2))
75,84c75,84
< #define TWI_SR_TXCOMP (1U << 0) /* Transmission Completed */
< #define TWI_SR_RXRDY (1U << 1) /* Receive Holding Register Ready */
< #define TWI_SR_TXRDY (1U << 2) /* Transmit Holding Register Ready */
< #define TWI_SR_SVREAD (1U << 3) /* Slave Read */
< #define TWI_SR_SVACC (1U << 4) /* Slave Access */
< #define TWI_SR_GCACC (1U << 5) /* General Call Access */
< #define TWI_SR_OVRE (1U << 6) /* Overrun error */
< #define TWI_SR_UNRE (1U << 7) /* Underrun Error */
< #define TWI_SR_NACK (1U << 8) /* Not Acknowledged */
< #define TWI_SR_ARBLST (1U << 9) /* Arbitration Lost */
---
> #define TWI_SR_TXCOMP (1U << 0) /* Transmission Completed */
> #define TWI_SR_RXRDY (1U << 1) /* Receive Holding Register Ready */
> #define TWI_SR_TXRDY (1U << 2) /* Transmit Holding Register Ready */
> #define TWI_SR_SVREAD (1U << 3) /* Slave Read */
> #define TWI_SR_SVACC (1U << 4) /* Slave Access */
> #define TWI_SR_GCACC (1U << 5) /* General Call Access */
> #define TWI_SR_OVRE (1U << 6) /* Overrun error */
> #define TWI_SR_UNRE (1U << 7) /* Underrun Error */
> #define TWI_SR_NACK (1U << 8) /* Not Acknowledged */
> #define TWI_SR_ARBLST (1U << 9) /* Arbitration Lost */